Reconfigurable hardware implementation of K-nearest neighbor algorithm on FPGA

Abstract

Nowadays, Machine Learning is commonly integrated into most daily life applications in various fields. The K Nearest Neighbor (KNN), which is a robust Machine Learning algorithm, is traditionally used in classification tasks for its simplicity and training-less nature. Hardware accelerators such as FPGAs and ASICs are greatly needed to meet the increased requirements of performance for these applications. It is well known that ASICs are non-programmable and only fabricated once with high expenses, this makes the fabrication of a complete chip for a specific classification problem inefficient. As a better alternative to this challenge, in this work, a reconfigurable hardware architecture of the KNN algorithm is proposed where the employed dataset, the algorithm parameters, and the distance metric used to evaluate the nearest neighbors are all updatable after fabrication, in the ASIC case, or after programming, in the FPGA case. The architecture is also made flexible to accommodate different memory requirements and allow variable arithmetic type and precision selection. Both parameters can be adjusted before fabrication to account only for the expected memory requirement and the fixed point precision required or floating point arithmetic if needed. The proposed architecture is realized on the Genesys 2 board based on Xilinx’s Kintex-7 FPGA. The results obtained from the experiment are consistent with those obtained from the simulation and software analysis. The proposed realization reaches a frequency of up to around 110 MHz and a power consumption of less than 0.4 watts