Reconfigurable Finite Impulse Response Research Articles

Digital Aided Analog Data Acquisition for Telemetry

This paper tackles the limitations in the current data acquisition system through the integration of a equiripple Finite Impulse Response (FIR) filter. The inclusion of this digital filter eliminates the necessity for physical component alterations, thereby increasing the system’s adaptability and versatility in telemetry applications. The FIR filter’s ability to adjust passband, stopband, and sampling frequencies allows for seamless reconfiguration without the need for hardware modifications, representing a substantial enhancement compared to the constraints of the previous system. Additionally, the equiripple design guarantees minimal variations in passband and stopband ripples, thereby optimizing overall filter performance. An important aspect of the proposed solution is the implementation of shift-and-add multiplier architecture for the FIR filter, which contributes to a reduction in hardware complexity and resource requirements, ultimately leading to a more efficient system. The adoption of MATLAB’s robust filter design tools, coupled with subsequent verification through SIMULINK simulations, has played a pivotal role in successfully realizing the proposed design. To sum up, this project has efficiently addressed the identified issues by introducing a reconfigurable FIR filter solution that not only enhances the flexibility, performance, and user friendliness of the data acquisition system in telemetry applications but also showcases the potential for broader applications in various signal processing domain.

Low-complexity reconfigurable FIR lowpass equalizers for polynomial channel models

This paper introduces realizations of a reconfigurable finite-impulse-response (FIR) filter for simultaneous equalization and lowpass filtering. The main advantage of the proposed solutions is computational complexity reduction compared to existing solutions for a given performance, which leads to reduced hardware complexity. The proposed structures employ properties of both a variable bandwidth (VBW) filter and a variable equalizer (VE) with variable coefficients. The overall transfer function of the proposed reconfigurable lowpass equalizer (RLPE) is a weighted linear combination of fixed subfilters where the weights are directly determined by the bandwidth and one or several parameters of the channel needed to be equalized. The paper provides design procedures based on minimax optimization and introduces a fast design method for the filter with several variable parameters that can substantially decrease the design time. Filter order estimation expressions as well as complexity expressions are presented for all proposed realizations. Design examples include comparison of the RLPE structures and a common approach of using a regular FIR equalization filter requiring online redesign when the bandwidth or channel characteristics are changed. It is shown that the number of general multiplications can be reduced up to 91% using the proposed RLPE.

An efficient reconfigurable FIR filter design with coefficient optimization using a modified bacterial foraging optimization algorithm

ABSTRACT The digital filters play a significant role in the field of digital signal processing (DSP). The finite impulse response (FIR) filter is an attractive choice because of the ease of design and good stability. The digital filters have a wide variety of applications such as signal processing, control systems, telecommunication, etc. They are better than the analogue filters due to their performance. In recent times, software radios have achieved attention owing to requirements for integrated and reconfigurable communication systems. Hence, reconfigurations have emerged as a significant problem in the designs of FIRs. To match the frequencies of DSP applications, higher-order FIRs are required. If length of filters rises, addition and multiplication operations also increase. This paper proposes an efficient hardware design of RFIR that employs modified bacterial foraging optimizations (MBFOs) and common sub-expression eliminations (CSEs) in its executions. MBFOs output restricted counts of filter coefficients with sums of signed-power-of-two (SPT) terms while maintaining the quality of filtered responses. On obtaining coefficients, eliminations are executed by CSEs where hardware complexities are determined in terms of adders. Model sim software validated RFIRs using the Verilog code. The proposed design of RFIRs was compared with existing designs in terms of power usages, frequencies and areas.

Low-Power Reconfigurable FIR Filter Design Based on Common Operation Sharing

This paper presents a low-power, fully reconfigurable finite impulse response (FIR) filter structure based on common operation sharing. Different from existing multiplexer(MUX)-based designs, the decoding of coefficients and compensation of negative-coefficient errors, which are the common operations for all the taps, are implemented by shared modules to reduce the overall hardware complexity. To validate the proposed structure, a proof-of-concept reconfigurable FIR filter is implemented and fabricated using 40 nm CMOS technology. Chip measurement results show that the proposed design is superior to existing methods in area-delay product and power performance, making it suitable for low-power filtering applications. The idea of sharing common operations for all taps can benefit the existing MUX-based filter techniques for further improvement of power and circuit complexity.

Design and Implementation of High Speed Low Power Decimation Filter for Hearing AID Applications

This work is focused on designing and implementing a decimation filter specifically intended for use in hearing aid applications. The filter utilizes distributed arithmetic (DA) and is described in this brief. Our proposal involves the development of a reconfigurable finite impulse response (FIR) filter, which utilizes both offset binary code (OBC) and binary distributed arithmetic (DA) techniques. Additionally, we utilize canonic signed digit (CSD) representation to develop decimation filters, which include the CIC filter, half band filter, and corrector filter. In this work, we have implemented a decimation filter using Matlab Simulink. We have utilized Xilinx Vivado 19.2 to execute the FIR filters, binary DA filters, and OBC DA-based filters. Our focus is on implementing these filters using VLSI architecture, in order to achieve low power consumption, reduced latency, less area, and fast speed.

Very large scale integration implementation of efficient finite impulse response filter architectures using novel distributed arithmetic for digital channelizer of software defined radio

AbstractAlways an efficient and low complexity reconfigurable filter architecture is required for the channel filters of digital channelizer in software‐defined radio (SDR). In this paper, a block‐based reconfigurable finite impulse response (FIR) filter is proposed using distributed arithmetic (DA) technique. The complexity of the conventional multiplier is replaced with the DA multiplication process, and the throughput of the entire filter is increased by block processing. Memory reuse is also achieved in the proposed direct form systolic FIR filter architecture due to parallel processing. The different bandwidth filters and the corresponding coefficients are stored in the look‐up tables (LUTs) concerning different channels of the digital channelizer. The proper channel selection is used to choose an appropriate filter and partial products are generated using offset binary coding (OBC). Next, the multiplication process is done by the proposed decomposed LUT‐based DA technique in the processing blocks of the filter. The proposed filter is coded by Verilog and synthesized by application specific integrated circuit (ASIC)‐based tools from Cadence in 45 nm CMOS technology. The performance parameters such as area, delay, power consumption, area‐delay product (ADP), and power delay product (PDP) are evaluated and compared with state‐of‐the‐art works. The ADP and PDP values are saved by 44.1% and 30% by the proposed OBC‐DA‐based filter architecture than the conventional DA‐based filter architecture, respectively.

Efficient FPGA Implementation of an RFIR Filter Using the APC–OMS Technique with WTM for High-Throughput Signal Processing

Nowadays, Finite Impulse Response (FIR) filters are used to change the attributes of a signal in the time or frequency domain. Among FIR filters, a reconfigurable filter has the advantage of changing the coefficient in real-time, while performing the operation. In this paper, the Anti-Symmetric Product Coding (APC) and Odd Multiple Storage (OMS) modules are utilized to implement the reconfigurable FIR filter (RFIR–APC–OMS). Herein, the APC–OMS module is used to reduce the area of the RFIR architecture. The performance of the RFIR–APC–OMS is analyzed in terms of: area, power, delay, LUT, flip flop, slices, and frequency. RFIR–APC–OMS has reduced 3.44% of area compared to the existing RFIR architecture employing the Dynamic Reconfigurable Partial Product Generator (DRPPG) module.

Design and Implementation of Hybrid Techniques and DA-based Reconfigurable FIR Filter Design for Noise Removal in EEG Signals on FPGA

Virtual Reality (VR) technology assists physically challenged personnel in their daily routine activities. The evolution of technology has enhanced the critical activities of people who use wheelchairs by extracting features through electroencephalogram (EEG) and promoting options for their choice for decision-making on their own. During extraction of EEG, signal artifacts may mislead the decision-making environment. Hence noise has to be removed with help of an FIR filter for accuracy. In this context utilization of finite impulse response (FIR) filters are so vital hence filters are incorporated with the hidden Markov model (HMM) and Gaussian mixture model (GMM) and supervised machine learning architecture of multirate support vector machine (SVM). The proposed EEG-based diagnosis system is a fully automated audio announcement system. The entire environment has been developed by Verilog HDL and MATLAB. Validated on Artix-7 FPGA development board and synthesized with Vivado Design Suite 2018.1. Obtained results exhibit an enhancement of 32% of signal-to-noise ratio (SNR),7% of mean square error (MSE), and 69% of abnormality recognition.

A Natively Fixed-Point Run-Time Reconfigurable FIR Filter Design Method for FPGA Hardware

We present a natively fixed-point filter design method that targets FPGA-based Reconfigurable Finite Impulse Response (RFIR) filters for Software Defined Radio applications. The Filter Designer is capable of reconfiguring cut-off frequencies on-the-fly at run-time; with other parameters, such as filter length and window type, configurable at compile-time. The ability to compute filter coefficients directly on FPGAs is compelling, as much lower latencies can be achieved when compared to RFIRs programmed with embedded processors. In this work we discuss several filter design techniques from the literature and investigate their suitability for implementation on FPGAs. A hybrid method combining window and frequency sampling methods is developed and implemented on a Xilinx Zynq-7000 SoC. We explore the limitations of designing filters in fixed-point arithmetic and consider the effects filter length and wordlength have on filter quality. Results show that the proposed algorithm generates good-quality filters that display stopband attenuation up to 88dB, transition bandwidths less than 1% of the sample rate, and low resource utilisation. Most notably, we found that our method is up to three orders of magnitude faster than an equivalent software implementation, with execution times as low as 2.52 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> , enabling radio applications in which latency is a principal constraint.

Implementation of Area Efficient Multiple Passband FIR Filter for 5G Applications

In television, mobile and digital signal processing applications, efficient multiband filters have great usage. The proposed architecture gives the Reconfigurable Finite Impulse Response (FIR) filter with multiple pass bands. Implementation of architecture utilizes FIR filter with control logic and frequency selection circuit. By adjusting the parameters of the filter, proper bandwidth of the pass band can be achieved and the ripple content in the pass band and stop band can be controlled. The efficient way to adjust the bandwidth is to choose the effective value of the filter length and coefficients. The area efficient multiple passband FIR filter using control logic has been proposed with order (n = 4 and 11). Target device that has been selected for implementation is Field Programmable Gate Array (FPGA) Virtex 4 Device. The Look-Up Tables (LUT) utilization for the implemented architecture with length of filter (n = 11) is observed to be 6%.

Area-Delay-Power Efficient VLSI Architecture of FIR Filter for Processing Seismic Signal

Low-complexity, high-speed and re-configurability are the primary requirements of the finite impulse response (FIR) filters employed for the processing of acquired seismic signal in real-time seismic-alert-system. The common sub-expression elimination (CSE) technique is employed widely to reduce the hardware complexity by minimizing the logic operators (LOs) and logic depths (LDs) in digital FIR filter. In this brief, a novel matrix grouped CSE (MCSE) algorithm has been proposed which outperforms the existing CSE algorithms in terms of LOs and LDs minimization. Moreover, a new half-unit biased (HUB) based rounding technique is incorporated in the proposed design to reduce the truncation error while maintaining low-complexity and the cut-set retiming technique is employed to reduce the critical-path-delay (CPD). Two hardware efficient FIR filter architectures (I and II) involving the proposed canonical signed digit (CSD) based MCSE algorithm, HUB rounding and cut-set retiming approach have been presented. Further, the architecture II represents a hardware efficient realization of a reconfigurable FIR filter. The hardware implementation of the architectures is performed on both FPGA and ASIC platforms. The hardware implementation of the proposed architecture I yields more than 25%, 49%, 38%, 36% and, 31% reduction in LOs, CPD, effective latency, area-delay-product (ADP) and, power-delay-product (PDP), respectively, over the state-of-the-art CSE based architectures. Whereas the reconfigurable architecture II exhibits nearly 48%, 12% and, 13% reduction in CPD, ADP and, PDP over the counterpart.

Design and implementation of pervasive DA based FIR filter and feeder register based multiplier for software definedradio networks

PurposeDigital signal processing (DSP) applications such as finite impulse response (FIR) filter, infinite impulse response and wavelet transformation functions are mainly constructed using multipliers and adders. The performance of any digital applications is dependent on larger size multipliers, area and power dissipation. To optimize power and area, an efficient zero product and feeder register-based multiplier (ZP and FRBM) is proposed. Another challenging task in multipliers is summation of partial products (PP), results in more delay. To address this issue, the modified parallel prefix adder (PPA) is incorporated in multiplier design. In this work, different methods are studied and analyzed for designing FIR filter, optimized with respect to area, power dissipation, speed, throughput, latency and hardware utilization.Design/methodology/approachThe distributed arithmetic (DA)-based reconfigurable FIR design is found to be suitable filter for software-defined radio (SDR) applications. The performance of adder and multipliers in DA-FIR filter restricts the area and power dissipation due to their complexity in terms of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by using PPA which is based on Ling equation. The MDA-RFIR filter is designed for higher filter length (N), i.e. N = 64 with 64 taps and this design is developed using Verilog hardware description language (HDL) and implemented on field-programmable gate array. The design is validated for SDR channel equalizer; both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of part name XC7A100tCSG324.FindingsThe MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency. The theoretical and practical comparisons have been done, and the practically obtained results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed product and energy efficiency are better about 3.5 times, 31, 45 and 29%, respectively.Originality/valueThe MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency.

Implementation of efficient reconfigurable FIR filter with control logic for 5G applications

Filters are used to achieve frequency selectivity on the spectrum of input signal. Due to the stability of finite impulse response (FIR) filters, they are used in most of the applications. In the conventional FIR filters, the frequency band is fixed and cannot be changed once it is designed. Hence, there is a necessity of an FIR filter with auto-adjustment of band width in modern day communication systems like 5G. The design of FIR filter requires more number of filter coefficients to get the desired bandwidth specification. This results in a large slice for field programmable gate array implementation. Here, it proposed a state machine to select different FIR filters with the designated set of coefficients. Each FIR filter is having different set of coefficients, and based on the frequency of the clock signal, the FIR filter is selected and thereby frequency selectivity can be achieved. The proposed method is to implement reconfigurable FIR (RFIR) filter with control logic for auto-adjustment of frequency selections to achieve better band width requirements. The filter order is initially selected as 4 and presented the simulation results. The order of the filter(n) increased to 24 for verifying the bandwidth selection. The proposed architecture is compared with the existing architecture with 16 bits and 11 taps. The proposed method saves 33.5% of look-up-tables (LUTs) compared to the existing methods. Simulation results presented are verified using Xilinx ISE design suite 14.7. The total number of four-input LUTs utilized are 630 for order(n) of the filter 24. Power consumed by the overall design is 195 mW.

Optimized DA-reconfigurable FIR filters for software defined radio channelizer applications

PurposeIn this paper, the authors present different methods for reconfigurable finite impulse response (RFIR) filter design. Distributed arithmetic (DA)-based reconfigurable FIR filter design is suitable for software-defined radio (SDR) applications. The main contribution of reconfiguration is reuse of registers, multipliers, adders and to optimize various parameters such as area, power dissipation, speed, throughput, latency and hardware utilizations of flip-flops and slices. Therefore, effective design of building blocks will be optimized for RFIR filter with all the above parameters.Design/methodology/approachThe modified, direct form register structure of FIR filter contributes the reuse concept and allows utilization of less number of registers and parallel computation operations. The disadvantage of DA and other conventional methods is delay increases proportionally with filter length. This is due to different partial products generated by adders. The usage of adder and multipliers in DA-FIR filter restricts the area and power dissipation because of their complexity of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by parallel prefix adder (PPA) usage based on Ling equation. PPA uses shift-add multiplication, which is a repetitive process of addition, and this process is known as Bypass Zero feed multiplicand in direct multiplication, and the proposed technique optimizes area-power product efficiently. The modified DA (MDA)-based RFIR filter is designed for 64 taps filter length (N). The design is developed by using Verilog hardware description language and implemented on field-programmable gate array. Also, this design validates SDR channel equalizer.FindingsBoth RFIR and SDR are integrated as single system and implemented on Artix-7 development board of XC7A100tCSG324 and exploited the advantages in area-delay, power-speed products and energy efficiency. The theoretical and practical comparisons have been carried out, and the results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed products and energy efficiency, which are improved by 14.5%, 23%, 6.5%, 34.2% and 21%, respectively.Originality/valueThe DA-based RFIR filter is validated using Chipscope Pro software tool on Artix-7 FPGA in Xilinx ISE design suite and compared constraint parameters with existing state-of-art results. It is also tested the filtering operation by applying the RFIR filter on Audio signals for removal of noisy signals and it is found that 95% of noise signals are filtered effectively.

Panda-type few-mode fiber-enabled microwave photonic filter with a reconfigurable finite impulse response.

Leveraging various physical dimensions of optical signals allows significant scaling of the transmission capacity for optical communications. Here we experimentally demonstrate a reconfigurable microwave photonic filter (MPF) enabled by both mode and polarization division multiplexing arising in a Panda-type few-mode fiber. The LP01x, LP01y, LP11x, and LP11y modes are used to realize optical true-time delay lines of the MPF, thus achieving a four-tap finite impulse response (FIR) with a free spectral range of around 2.22 GHz. Due to the employed delay between two orthogonal polarizations, the number of taps arising in its FIR can be doubled. Moreover, the reconfigurable FIR of the MPF can be achieved by loading the corresponding phase pattern onto a spatial light modulator. Finally, the low-pass FIR can be switched to the bandpass FIR due to the introduction of polarization modulation, indicating the flexible manipulation of the FIR for the multi-dimensional division multiplexing enabled MPF.

Efficient FPGA based architecture for high‐order FIR filtering using simultaneous DSP and LUT reduced utilization

This paper proposes an efficient high-order finite impulse response (FIR) filter structure for field programmable gate array (FPGA)-based applications with simultaneous digital signal processing (DSP) and look-up-table (LUT) reduced utilization. The real-time updating of the filter coefficients is also put into perspective. In order to perform these objectives, both the speed and the structure of FPGA are efficiently exploited. The gap between the required input sampling frequency and the FPGA allowed maximum frequency is managed to achieve additional computing sequences. Furthermore, the special structures of the FPGA Look-up-table Shift-Register (LUT-SR) and their internal connections are fully employed for pipelining and selecting the input samples. The FPGA Block RAMs (BRAMs) are employed for handling the reconfigurable filter coefficients, and the FPGA DSP slices are associated for computing the output data of the BRAMs and the multiplexers. To synchronize the BRAM unit addressing with the LUT multiplexer selection, a single unit is used for simultaneous control. The obtained results show that the proposed reconfigurable 16-tap FIR filter offers reductions of 79.3% and 74.4% of slice utilization over the hybrid variable size partitioning (VP-Hybrid) based structure and the Radix-2r based structure, respectively when implemented on a Xilinx Spartan-6 XC6SLX45 FPGA. Moreover, an improvement of efficiency is achieved compared to all reputed FPGA-based architectures.

A Low-Power VLSI Implementation of RFIR Filter Design using Radix-2 Algorithm with LCSLA

ABSTRACT The multimedia applications and mobile communication systems require an efficient reconfigurable finite impulse response (RFIR) filter designs for achieving low area, power, cost, and high speed of system operation. In this paper, an efficient RFIR filter is designed based on the Radix-2 algorithm and Look-up-table Carry Select Adder (Radix 2 – LCSLA). Generally, the RFIR filter is controlled by multiplier and adder, which improves the performances of the filter. Hence, this research work is mostly concentrated on the multiplier and adder design. Here, the radix-2 algorithm is used instead of normal multiplier for multiplication operation in the RFIR filter design. Additionally, CSLA and LCSLA approaches used in the Radix-2 structure for adding partial products. The LCSLA has achieved better performance compared to the normal CSLA approaches. In this paper, both the Radix-2 algorithm and LCSLA approach improved the performances of the proposed RFIR filter design. The proposed RFIR filter design was implemented in the Xilinx and Cadence RTL compiler by using the Verilog code. The RFIR-Radix 2-LCSLA filter design was verified in the Modelsim by utilizing the Verilog code. The experimental result showed that the RFIR-Radix 2-LCSLA methodology has improved the performance of ASIC and FPGA in the RFIR filter design up to 5–15% compared to the existing filter architecture: DA-RFIR and LC-CBA-RFIR methods.

Reconfigurable Microwave Photonic Filter Based on Long Period Gratings Inscribed in Multicore Fibers

We propose and experimentally demonstrate a reconfigurable finite impulse response microwave photonic filter (FIR-MPF) based on long period gratings (LPGs) inscribed in multicore fibers. By exploiting two dimensions of optical wavelength and space, intentional inter-core signal switching is realized. For the diversity of optical wavelength, we tune the operation wavelength to change the inter-core power coupling according to the wavelength-dependent characteristic of LPGs. On the other hand, for the diversity of space, we use directional bending of LPGs to achieve switchable spatial channel allocation. Both configurations can implement three different two-tap FIR-MPFs individually. We show a promising solution for reconfigurable radio frequency signal processing in potential with low cost and high efficiency.

Analysis and Implementation of High Performance Reconfigurable Finite Impulse Response Filter Using Distributed Arithmetic

The finite impulse response (FIR) digital filters are commonly used in many digital signal processing systems. For higher order filters the implementation of reconfigurable random access memory based FIR filter becomes costly and the speed is reduced. This research paper presents an efficient distributed arithmetic (DA) based approach for reduced area and low power implementation of the FIR filters whose filter coefficients are dynamic in nature. Due to the complexity in implementation of higher order filters, a portion of bit serial based computation in the look up table (LUT) is used. However the shared LUTs are used instead of RAM based LUTs, Shared LUTs involves the concept of LUT partitioning where the coefficients are split into vectors of smaller bit lengths which reduce the depth of the LUT. The possible partial DA results for these vectors are stored in register banks that are shared between multiple DA units. Since the register banks are shared, the area is effectively reduced. Hence an application specific integrated circuits implementation is used. When compared to the existing 256 tap FIR filter, the area has been reduced by 62.16% for vector bit length (M), M = 2 and by 75.84% for M = 4 and the power consumption has been reduced by 42.67% for M = 2 and by 64.02% for M = 4.

A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on CSD Decoded Vertical–Horizontal Common Sub-Expression Elimination Algorithm

This paper introduces a computationally efficient hardware architecture for reconfigurable multiple constant multiplication block, which functions according to the canonical signed digit (CSD)-based vertical and horizontal common sub-expression elimination (VHCSE) algorithm. In the proposed architecture, the CSD decoded coefficient along with 4-b common sub-expressions (CSs) in the vertical direction and 4- and 8-b CSs in the horizontal direction reduces the required number of full adder cells and the adder depths. This technique helps in reducing area consumption by decreasing the number of coefficient multiplier adders by 59% than that of the binary VHCSE (VHBCSE) algorithm. This technique helps in reducing the average switching activity of the adder blocks used in each coefficient multiplier block by 26.1%, 25.6%, and 21.3%, while compared with those of the 2- and 3-b binary CS elimination (BCSE) and VHBCSE algorithms, respectively. For different orders of filter, the proposed one delivers 57.5% and 61.9% improvement in area-power product (APP) on an average compared with the VHBCSE and mixed integer programming algorithms, respectively. Experimental results of differently specified finite impulse response (FIR) filters ranging from 10 to 100 taps and the coefficients of 8, 12, and 16 b show the improvements of 42.8%, 53.6%, and 37%, respectively, in the average gate count and 51.8%, 43.5%, and 36.7% less propagation delay than those of earlier canonical double-based number representation method. Moreover, in the metric made of APP divided by throughput, the proposed technique experiences 63.7% improvement on an average over that of faithfully rounded truncated multiple constant multiplication/accumulation technique of designing constant multiplier and demonstrates its suitability for implementing efficient reconfigurable FIR filter.