Reconfigurable Field Effect Transistor Research Articles

Preparation and characterization of silicon nanowires using SEM/FIB and TEM

Abstract Due to the electronic and structural properties of silicon, silicon nanowires have a great potential in nanoscale electronic devices and sensors. Silicon nanowires used for reconfigurable field effect transistors are designed, synthesized and characterized after each step in order to ensure excellent electrical and physical properties of the end product and to study various process parameters. In this study, silicon nanowire based reconfigurable field effect transistors are studied as as-grown “forests”, individually, oxidized and after forming Schottky junctions. The analysis is performed using scanning electron microscopy and transmission electron microscopy. Focused ion beam based preparation was carried out in the case of samples with Schottky junctions. This paper provides a comprehensive description of sample preparation and characterization of the nanowires.

Spacer Engineering-Based High-Performance Reconfigurable FET With Low OFF Current Characteristics

In this letter, we optimize and investigate for the first time the effect of source/drain spacer oxide on the performance of a dual gate ambipolar silicon nanowire field effect transistor. Using extensive 3-D TCAD simulations, we show that the OFF-state leakage can be reduced by more than two orders of magnitude owing to the combined use of HfO2 spacer and high- $\kappa $ gate dielectric, resulting in an enhanced ON/OFF current ratio $> 10^{11}$ for both n and p-FET as compared with reported values of $\sim 10^{9}$ . Comparing with the existing experimental dual and trigate ambipolar devices, 64.1% improvement in subthreshold slope for n-FET and 61.8% (40.9%) for n (p-FET) are observed. Having, an improvement in the ON-state current with $J_{D{\rm max}}$ of 767.51 (263.05) kA/cm $^{\mathrm {\mathbf {-2}}}$ for n-FET (pFET), the device promises excellent ultra low power logic performance, with ambipolarity.

TEM Study of Schottky Junctions in Reconfigurable Silicon Nanowire Devices

The physical and electrical properties of a silicon nanowire reconfigurable field effect transistor (RFETs) are determined by the Schottky junction between the participating phases. TEM studies on such junctions require a careful FIB‐based target preparation of thin lamellae with minimal ion‐beam induced damage. In the current study, the nickel silicide phase forming the Schottky junction with silicon is identified using EDX in the TEM, considering a calibration based on the Fourier transforms of the HRTEM micrographs of known diffraction patterns of the nickel silicide phases. The TEM lamellae are prepared using the so‐called lift‐out technique and low voltage Ga+ ion polishing to minimize the near‐surface amorphization. The structural and compositional data of the nickel silicide phase are needed for engineering the Schottky junction and corresponding theoretical modeling.