Reconfigurable Computing System Research Articles

High-Level Synthesis Toolchain "Theseus" for Multichip Reconfigurable Computer Systems

High-Level Synthesis Toolchain "Theseus" for Multichip Reconfigurable Computer Systems

Autotesting an Embedded Reconfigurable Computing System

Purpose of research. The main idea is to build a mathematical testing model that integrates different aspects of an embedded reconfigurable computing system and its interactions. This model provides an efficient representation of test scenarios and allows to analyse the dynamics of the reconfigurable computing system during testing. The paper also discusses methods for generating test sequences based on the properties of a finite state machine.Methods. The authors propose to represent the autotest as a finite state Mile machine, where states serve to store information about the current state of an embedded reconfigurable computing system. The input signal is the interaction with the system and the output signal is the system's response to the input signal. This approach allows to formalize the testing process and simplify the analysis of possible problems.Results. This paper discusses the application of automata theory in the context of automated testing of embedded reconfigurable computing systems. Automata theory provides effective methods and tools for analysis and simulation of discrete dynamic systems, which makes it suitable for automated testing tasks.Conclusion. The results show that the use of automata theory can significantly improve the quality and efficiency of automated testing of embedded reconfigurable computing systems. This approach provides a deeper analysis of the system and allows to detect and prevent potential problems that may arise during its operation.

Selection of the Protocol for Receiving Data Transmission and Development of an Algorithm for Selecting The "Master" Processor Module for a Reconfigurable Real-Time Computer Network

Purpose of research. Computing networks of a plurality of processor modules have existed for a long time, however, with the development of wireless technologies, the possibility of high-quality and inexpensive implementation of the idea of real-time reconfigurable computing networks (RRTCN) has emerged. The purpose of this work is to select a wireless data transmission network for the RRTCN and create an algorithm for the dynamic selection of the "master" processor module.Methods. The research methods of the work are based on the definitions of the theory of sets and graphs. In particular, a grapho-theoretical approach to distribution is taken as a basis, supplemented by the introduction of a system of criteria for a reconfigurable real-time computing system based on a wireless data transmission protocol.Results. In this paper, the most suitable data transfer protocol for the local RCSRV is selected, a developed mathematical model of changing a real-time computing system built on a wireless protocol is presented, and an algorithm for selecting the processor module (PM) of the RCSRV "master" is developed. The novelty of the work is the use of the distance matrix for the mathematical description of the change in the RRTCN and its use to determine the PM of the "master" in the aircraft.Conclusion. The developed algorithm for choosing the PM of the "master" RRTCN and the mathematical model of changing the position of the PM in a real-time computer system built on a wireless protocol allows organizing the optimal choice of the PM of the "master" in a reconfigurable computing system. On the basis of the presented mathematical model, in the future, it is possible to create a full-fledged mathematical model of the RRTCN and an algorithm for placing tasks in it.

МЕТОДИКА СОЗДАНИЯ ТОПОЛОГИЧЕСКИХ ОГРАНИЧЕНИЙ ПРИ ВЫСОКОЙ УТИЛИЗАЦИИ РЕСУРСОВ ПЛИС

In the paper we consider the problem of achieving high real performance of reconfigurablecomputer systems in implementing computationally expensive tasks from various problem areas.The parameters of the programs executed on reconfigurable systems determine their real performance.The main component of these programs is the computing data processing structures implementedas FPGA configuration files. At the same time, one of the key parameters of any computingstructure is the clock frequency of its operation, which directly affects its performance. However,there are several problems concerning the achievement of high clock rates, and they cannot be solvedwith the help of modern CAD tools. The reason is the non-optimal topological placement of functionalblocks of the computing structure within the field of FPGA primitives, especially with high resourceutilization. Due to this, the load on the FPGA switching matrix is increasing, and, as a result,the connections among functionally dependent FPGA primitives turn out to be much longer than isacceptable. In addition, excessive connection length is observed when tracing connections amongprimitives that are placed on different FPGA chips or are physically separated by on-chip peripherals.In the paper we describe a methodology which provides optimization of the placement of computingstructure elements on FPGA primitives, and minimizes the length of traces among primitives,and also minimizes the number of traces among physically separated FPGA topological sections.To prove the proposed methodology, we implemented the test task "FIR-filter" on a reconfigurablecomputer "Tertius." We have demonstrated the main problems concerning reaching the target clockrate and have described a method for their solution. Owing to our methodology, it is possible toincrease the clock rate; hence, the performance of Tertius will increase by 25% without revisingthe functional circuit of the task’s computing structure. According to our current research of thesuggested methodology and its efficiency, we claim that CAD tools, used for creating topologicalrestrictions and based on our methodology, will significantly reduce the time for developing programswith the required characteristics for reconfigurable computer systems.

Программные средства высокоуровневого синтеза для многокристальных реконфигурируемых вычислительных систем

The article describes an original complex of high-level synthesis that converts sequential programs into a circuit configuration of specialized hardware for reconfigurable computing systems. An absolutely parallel form, an information graph, is constructed from the original sequential program. Further, the graph is transformed into a resource-independent parallel–pipeline form — a personnel structure that can be adapted to various hardware resources. The transformation of the personnel structure into an information-equivalent structure, but occupying a smaller hardware resource, is performed using formalized methods of performance reduction, which allows you to automatically obtain a rational solution for a given multi-chip reconfigurable computing system. Unlike the known means of high-level synthesis, the result of the transformation is not the IP core of a computationally time-consuming fragment, but an automatically synchronized solution of an applied problem for all FPGA crystals of a reconfigurable computing system. Compared with parallelizing compilers, the number of analyzed variants of the synthesis of a rational solution is significantly less, which is a distinctive feature of the described complex. The application of high-level synthesis software is considered by the example of the problem of solving a system of linear algebraic equations by the Gauss method containing information-interdependent computational fragments with significantly different degrees of parallelism.

A new method for self-organized dynamic delay loop associated pipeline with reconfigurable computing system

<span>The minimization of propagation delay between pipeline stages is very important in wave propagation through pipeline-stages. The propagation delay can be minimized by minimizing the number of stages in a pipeline. In the proposed design a dynamic stage control is imparted in the pipeline. The propagation delay can be optimized in any type of pipeline by controlling number of stages dynamically. The pipeline interpretation helps a lot to overcome the flaws due to not ready sequence (NRS) and synchronization problems. It is observed that, in the pipeline design the basic and actively involved pipeline techniques are concerned with different challenges like clock, throughput, cell area, and sizes. As the data throughput increases the number of stages in pipeline also needs to be increased to meet the desired goal. In the case of unpredictable data speed, the definite number of pipeline stages creates severe problems. In this work a dynamic pipeline is integrated where the number of stages is dynamically changing depending up on data speed. In dynamic pipeline technique the circuit cell area of reconfigurable computing system (RCS) will be reduced dynamically at low-speed data transmission. In the high-speed data communication, the data speed is managed and controlled by dynamic delay loops.</span>

МЕТОД ОРГАНИЗАЦИИ ДИСКРЕТНО-СОБЫТИЙНЫХ ВЫЧИСЛЕНИЙ ДЛЯ ОБРАБОТКИ БОЛЬШИХ РАЗРЕЖЕННЫХ НЕСТРУКТУРИРОВАННЫХ МАТРИЦ НА РВС

Increasing models complexity objects and processes study, in different sphere of science andtechnology, set up plenty issues to necessary to use high-performance computing systems. Arraysmatrix processing by cluster multiprocessor computing systems in conjunction special methodsaimed at organizing parallel computations, basically obtain computing performance system isquite high. However, that computational efficiency is not observed for all types of matrices. Matrixstructure be in a position contain large amount of insignificant elements, large dimension andunstructured portrait. Calculation execute for described kind of matrices on cluster multiprocessorcomputing system couldn't achieve close peak performance. Considering that processing methodsleave out the complex structure of the matrix being processed. As a result, the performance of thesystem is significantly reduced. The development of cluster MCS methods doesn't allow for fullensure high performance for class of problems processing of large sparse unstructured matrices.Rigid architecture of processor commutation net doesn’t take into account the peculiarities of suchmatrices, and lead to non-uniformity loading processor. To achieve performance close the peakfor tasks large sparse unstructured matrices processing necessary to use reconfigurable computingsystems. RCS architecture allows adapting computation structure to the problem solved. Thismakes it possible to organize pipeline processing, such a way that computational resource RCSused only for informational significant operations. In addition using generally accepted methodsfor structural organization of high-performance computing for RCS, it is necessary to develop aformat for storing and transferring large sparse unstructured matrices, to determine the principlesof constructing basic matrix macro-operations and the possibility of organizing composite discrete-event matrix functions for solving applied problems. Сconsequently method founding laidallows organizing computations operands, which are large sparse unstructured matrices. Theapplication this method for organizing computations can significantly increase productivity, andprovide an increase in the efficiency of such a system.

FPGA-BASED DATA COMMUNICATION SYSTEM IN DIGITAL SIGNAL PROCESSING DEVICES WITH PHASED ANTENNA ARRAYS

The paper represents some engineering solutions which provide coherence and coherent data transmission in radar and communication systems with phased array with computing components designed on the principles of FPGA-based reconfigurable computer systems. We developed the coherent gathering methods of digitized data from the phased array antenna elements, and data transmission among the distributed components that perform coherent digital signal processing. To provide coherent data processing and transmission, we use the signal of clock reference signal and the CPU-time, centrally generated and transmitted into all nodes with the same delay. Generation of all control signals in the processing nodes are based on these two signals. For data transmission, we suggest to use high-speed optical links, which are the most reliable in environmental conditions. To transmit the digitized data from phased array antenna elements, we suggested using packet data transmission with data integrity control and time-linked digitized data. Also, we applied a mechanism to monitor the delay mismatch of packets transmitted via different links and to synchronize them in data receivers. The most probable emergency situations for the data transmission system are considered and methods of parrying and minimizing the impact of transmission errors on the formation of the result are proposed. The developed engineering solutions were tested on a real FPGA-based beam-forming device with simulation of emergency situations. Many hours of tests and runs showed that all emergency situations were successfully solved by the data communication system.

АНАЛИЗ ВОЗМОЖНОСТЕЙ СОВРЕМЕННЫХ ВЫЧИСЛИТЕЛЬНЫХ ТЕХНОЛОГИЙ ДЛЯ РАСЧЕТА ТОЧНЫХ ПРИБЛИЖЕНИЙ РАСПРЕДЕЛЕНИЙ ВЕРОЯТНОСТЕЙ ЗНАЧЕНИЙ СТАТИСТИК

In the paper we consider the solution of a computationally expensive problem such as calculationof statistics probability distribution with the help of modern computer technologies. To reducecomputational complexity and to provide a sufficient level of criteria efficiency not less thanthe specified threshold, we suggest to use Δ-exact approximations. To calculate exact approximations,we use the method of second order, based on solution of a system of linear equations. Owingto this method, it is possible to calculate exact approximations for the maximum values of sampleparameters for available computational resource. The most laborious part of the method of secondorder is the procedure of sequential detection of the vectors of possible solutions and test if thevectors belong to the set of solutions. The system solution set membership test for the vectors ofpossible solutions is data independent, so the algorithm can be data-parallelized. We give the algorithmcomplexity equation for calculation of exact approximations of statistics probability distributions.Using this equation, we calculated the complexity of modern practical problems for thesamples with the parameters (N, n) of the alphabet power and the sample size: (256,1280),(128,640), (128, 320), and (192,3200) for the accuracy of calculations =10-5. The computationalcomplexity is 9.68·1022-1.60·1052 operations, and its average value is about 4.55·1025 operations,the number of tested vectors is 6.50·1023-1.39·1050, and the number of solutions is 4.67·1012-5.60·1025, respectively. The total solution time for clock-round duration of calculations cannotexceed 30 days or 2.592·106 sec. For the obtained complexity evaluation, we analysed abilities ofmodern cluster computer systems based on general-purpose processors, graphic accelerators, andFPGA-based reconfigurable computer systems. For each technology, we determined the number ofcomputational nodes needed for calculation of exact approximations with the specified parametersduring the specified time. We proved that it is impossible to obtain a solution for the required parametersof exact approximations of statistics probability with the help of the reviewed moderncomputer technologies. In conclusion, we claim that it is necessary to analyse the abilities of advancedcomputer technologies based of quantum and photonic computers, and also hybrid computersystems for calculation of exact approximations of statistics probability distributions withthe specified parameters during reasonable time.

A quad-form clustered mapping approach for large-scale applications of reconfigurable computing systems

Reconfigurable Computing (RC) systems with hardware implementation feature demonstrated a promising solution for the demand of enormous processing power. However, RC systems suffer from long compilation phases when preparing large-scale applications to execute on reconfigurable hardware. In this paper, a novel quad-form clustered approach has been introduced to manage the hardware resources with low overhead and acceptable quality. For this purpose, two quad-form resource clustering and application partitioning algorithms are proposed to solve the entire mapping problem in intra and inter-cluster parts. Moreover, an analytical distance estimation is derived to properly manage clustered resources in the reconfigurable hardware. Several extensive experimental scenarios on both synthetic and real applications have been conducted to evaluate the effectiveness of the proposed approach in comparison with the state-of-art methods and the results showed that significant improvements have been achieved in terms of quality and time overhead for large-scale applications.

МЕТОДЫ ПРЕОБРАЗОВАНИЯ ВЫЧИСЛИТЕЛЬНЫХ СТРУКТУР С ОБРАТНЫМИ СВЯЗЯМИ ДЛЯ ЭФФЕКТИВНОЙ РЕАЛИЗАЦИИ НА РЕКОНФИГУРИРУЕМЫХ ВЫЧИСЛИТЕЛЬНЫХ СИСТЕМАХ

At present, various computer-aided (CAD) systems are used for solving tasks on reconfigurablecomputing systems (RCS). In most cases, they consist of two main parts: a compiler (translator),which translates the source code of a program into a graph-like information and computingstructure, and a synthesizer, which maps it on an FPGA architecture. As a rule, existing synthesizers process computing structures without any complex optimization. Therefore, the solution, generatedby the synthesizer, may contain inefficient fragments, which decrease a task solution speed.The most common examples of inefficient computing structures are fragments which implementrecursive expressions. The paper proposes transformation methods for recursive expressions(fragments with feedbacks), which allow automatically reduce the data supply interval when solvingtasks on reconfigurable computing systems. The methods are based on information-equivalenttransformations of the computing structure of the original task. For each transformation defined aset of rules that must be satisfied by the vertices of the computing structure. Applying rules allowsto perform equivalent transformations not only on simple data structures such as numbers, butalso on more complex structures (matrices, vectors, tensors, etc.). On the base of the simulationresults, the developed transformation methods of computing structures with feedbacks allow toreduce the task solving time about 2–5 times by reducing the data supply interval. The proposedmethods are implemented in a prototype of optimizing synthesizer.

Relation of the data transfer rate of a reconfigurable computer system to the amount of data transferred

This paper is devoted to real time reconfigurable computing systems. The theme of research study of speed of algorithm’s work with different parameters of the system and search of optimum parameters. The aim of the study is to check the dependence of the speed of the algorithm reconfigurable real-time computing system, depending on the volume of data being transmitted. The study was conducted using min-max methods, by trying the number of processors and the volume of data transferred to find the best option out of the presented ones. A pattern was found, how the time gain varied with increasing data volume and at which parameters it reached the highest performance.

THE PARALLEL-PIPELINED IMPLEMENTATION OF THE FRACTAL IMAGE COMPRESSION FOR RECONFIGURABLE COMPUTING SYSTEMS

The developed fractal image compression method, implemented for reconfigurable computing systems is described. The main idea parallel fractal image compression based on parallel execution pairwise comparison of domain and rank blocks. Achievement high performance occurs at the expense of simultaneously comparing maximum number of pairs. Implementation fractal image compression for reconfigurable computing systems has two critical resources, as number of input channels and FPGA Look-up Table (LUT). The main critical resource for fractal image compression is data channels, and implementation this task for reconfigurable computing systems requires parallel-pipeline computations organization replace parallel, preliminarily produced performance reduction parallel computational structure. The main critical resource for fractal image compression is data channels, and implementation this task for reconfigurable computing systems requires parallel-pipeline computations organization replace parallel computations organiation. For using parallel-pipeline computations organization, preliminarily have produce performance reduction parallel computational structure. Each operator has routed to computational structure sequentially (bit by bit) to save computational resources and reduces equipment downtime. Storing iterated functions system coefficients for image encoding has been introduced in data structure, which correlates between corresponding parameters the numbers of rank and domain blocks. Applying this approach for parallel-pipeline programs allows scaling computing structure to plurality programmable logic arrays (FPGAs). Task implementation on the reconfigurable computer system Tertius-2 containing eight FPGAs 15 000 times provides performed acceleration relatively with universal multi-core processor, and 18 – 25 times whit to existing solutions for FPGAs.

Software Models in VHDL Language as a Component of a Dispatching Subsystem of the Embedded Reconfigurable Computing System

The paper presents the results of research on the hardware implementation of dispatching functions of an embedded reconfigurable computing system with a single task queue and distributed task queues. The description of the dispatching subsystem component functioning at the hardware level was made in the VHDL language. The purpose and functionality of each unit implemented in the VHDL language is described. Debugging and testing of the developed software models for a dispatching subsystem of an embedded reconfigurable computing system is carried out and the results are analyzed. At the end, conclusions for the work are drawn.

Resilience analysis of multi-state systems with time-dependent behaviors

Most of existing resilience models assume that system performances are continuous. In this paper, we consider resilience modeling and analysis for multi-state systems, whose performances are characterized by discrete, rather than continuous variables. A non-homogeneous Semi-Markov reward process model is developed for resilience analysis of multi-state systems. In the developed model, system performance changes, caused by either disruptive events or system recoveries, are modeled as state transitions, and rewards are used to model financial losses incurred during and after the disruptions. Four resilience metrics are defined to quantify different aspects of resilience. As the developed model is non-homogeneous, it can capture time-dependent system behaviors and their impact on system resilience. An efficient resilience analysis algorithm is also designed based on linear interpolation and implemented using vectorization. The computational benefits of the developed algorithm are demonstrated through two numerical experiments. We apply the developed method on two practical case studies, an oil tank farm and a re-configurable computing system. The results show that the developed methods can quantify resilience of multi-state systems accurately and efficiently.

New iteration parallel-based method for solving graph NP-complete problems with reconfigurable computer systems

The paper presents a method of creating parallel-pipeline programs for reconfigurable computer systems based on iteration paralleling for the solution of graph NP-complete problems, which is different from others for processing the irregular sets with the elements accessed not by their addresses (like in arrays) but by values, the names of vertices and the graph arcs. It shows that the new iteration-parallel method is more efficient than the layer-parallel method when the available computing resource and the size of the solved graphs increase due to the significant reduction of the commutation connections.

Reconfigurable Microarchitecture-Based PMDC Prototype Development for IoT Edge Computing Utilization

in this article, a Reconfigurable Microarchi- tecture-based PMDC prototype is developed with the help of dynamic pipeline stages. The Reconfigurable Microarchitecture is intended for the Internet of Things (IoT) edge level computing utilization purposes. This microarchitecture is implemented using a reconfigurable computing system with the help of an FPGA board. The reconfigurable microarchitecture is used as a feedback circuit of the PMDC motor to come out with a developed speed control prototype that can be sufficiently integrated with IoT technology. The number of pipeline stages will dynamically change as per user speed requirements. Several methods of speed measurement are tested using different pipeline structures to find out an appropriate method for the IoT edge level. Resource utilization, throughput and latency for those methods are analyzed. Additionally, the reconfigurable microarchitecture gives dynamic power consumption which more suitable for IoT edge level computations. The Real-Time behavior of the developed prototype is carried out with a pseudo-random binary sequence (PRBS) test for its system identification, a particle swarm optimization (PSO) technique for its optimal controller design and edge level computations for its IoT integration procedure.

An Optimal Algorithm for Enumerating Connected Convex Subgraphs in Acyclic Digraphs

Reconfigurable computing system is emerging as an important computing system for satisfying the present and future computing demands in performance and flexibility. Extensible processor is a representative implementation of reconfigurable computing. In this context, custom instruction enumeration problem is one of the most computationally difficult problems involved in custom instruction synthesis for extensible processors. Custom instruction enumeration problem is essentially enumerating connected convex subgraphs from a given application graph. In this brief, we propose a provable optimal algorithm for enumerating connected convex subgraphs in acyclic digraphs in the sense of time complexity. The running time of the proposed algorithm is theoretically proved to be O(Σ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C∈CC(G)</sub> (|V(C)|+|E(C)|)), where CC(G) denotes the set of connected convex subgraphs in directed acyclic graph G, |V(C)| and |E(C)| denote the number of vertices and the number of edges in subgraph C respectively. Experimental results show that the proposed algorithm is more efficient than the state-of-the-art algorithms in terms of runtime.

Efficient Computation Techniques and Hardware Architectures for Unitary Transformations in Support of Quantum Algorithm Emulation

As the development of quantum computers progresses rapidly, continuous research efforts are ongoing for simulation and emulation of quantum algorithms on classical platforms. Software simulations require use of large-scale, costly, and resource-hungry supercomputers, while hardware emulators make use of fast Field-Programmable-Gate-Array (FPGA) accelerators, but are limited in accuracy and scalability. This work presents a cost-effective FPGA-based emulation platform that demonstrates improved scalability, accuracy, and throughput compared to existing FPGA-based emulators. In this work, speed and area trade-offs between different proposed emulation architectures and computation techniques are investigated. For example, stream-based computation is proposed that greatly reduces resource utilization, improves system scalability in terms of the number of emulated quantum bits, and allows for dynamically changing algorithm inputs. The proposed techniques assume that the unitary transformation of the quantum algorithm is known, and the matrix values can be pre-computed or generated dynamically. 32-bit floating-point precision is used for high accuracy and the architectures are fully pipelined to ensure high throughput. As case studies for emulation, the quantum Fourier transform and Grover’s search algorithms are investigated and quantum circuits for multi-pattern Grover’s search are also proposed. Experimental evaluation and analysis of the emulation architectures and computation techniques are provided for the investigated quantum algorithms. The emulation framework is prototyped on a high-performance reconfigurable computing (HPRC) system and the results show quantitative improvement over existing FPGA-based emulators.

Physically Unclonable and Reconfigurable Computing System (PURCS) for Hardware Security Applications

A physically unclonable and reconfigurable computing system is introduced which provides both logic locking and authentication of devices. A chaotic oscillator is required to generate the chaotic signals and can produce different Boolean functions using different tuning parameters, including a control bit, iteration number, threshold voltage, and bifurcation parameter. The aim of this article is to build a hybrid computing system with the mixed implementation of standard logic gates and reconfigurable chaos-based logic gates. The tuning parameters of the oscillator make up the secret key for logic locking. Process variation due to fabrication can be leveraged to generate unique keys for each chip. The whole computing system exhibits physical unclonable function (PUF) characteristics and can be used to generate challenge–response pairs (CRPs) for authenticating devices. We have used ISCAS’85 combinational benchmark circuits to demonstrate the results. The Hamming distance between correct and wrong outputs is calculated to ensure that 50% of the output bits are flipped when the wrong key is applied. A Boolean SAT attack has been carried out on the system and it displays exponential complexity with an increase in the total number of chaos gates and key size of each chaos gate. The hybrid system demonstrates near-ideal PUF metrics, including uniqueness, uniformity, and bit aliasing. Common machine learning attacks have been executed on the CRPs generated from the whole system and results show that the proposed chaos-based PUF is robust against modeling attacks. The hybrid system has significantly less overhead compared to traditional systems containing both logic locking and PUF circuitry.