Reconfigurable Computing System Research Articles

Reconfigurable computer systems: from the first FPGAstowards liquid cooling systems

The paper covers the history of development of design technologies of reconfigurable computer systems based on FPGAs of various families. Five generations of reconfigurable computer systems with high placement density, designed on the base of various FPGA families, from Xilinx Virtex-E to modern Virtex UltraScale, are described. The last achievements in the domain of design of energetic effective reconfigurable computer systems with high real performance are presented. One of such achievements is the developed liquid cooling system for Virtex UltraScale FPGAs. It provides independent circulation of the cooling liquid in the 3U computational module with the 19'' height for cooling of 96-128 FPGA chips that in total generate 9.6-12.8 kWatt of heat. The distinctive features of the designed immersion liquid cooling system are high cooling efficiency with power reserve for the designed perspective FPGA families, resistance to leaks and their consequences, and compatibility with traditional water cooling systems based on industrial chillers.

BFT: a placement algorithm for non‐rectangle task model in reconfigurable computing system

Task scheduling and placement problem is one of the most significant and time-consuming parts in reconfigurable computing (RC) system. Many investigators have explored on the subject, and most of the traditional studies are concentrated on the rectangle task model, which is inconsistent with objective task shape placed in a field programmable gate array (FPGA) but simplifies the system complexity. Rectangle task model produces inner fragments which reduces utilisation of reconfigurable resources in an FPGA. In this study, a task model transformation strategy and an innovative best-fit transformation (BFT) placement algorithm are proposed for a non-rectangle task model to improve the performance of an RC system in rejection rate and total execution time. According to simulation experiments, BFT algorithm reduced the rejection rate by 15% and 7% compared with that of the first-fit algorithm and the best-fit algorithm, respectively. Multi-shape placement algorithm and 3D compaction algorithm are also cited to compare with the BFT algorithm. The result shows that the BFT algorithm has less total execution time in short laxity period and lower rejection rate in large laxity period. Compared with 3D compaction algorithm, the proposed algorithm reduced the total execution time up to 10.79%.

Self-Configurable FPGA-Based Computer Systems: Basics and Proof of Concept

Computer systems performance is today improved with two major approaches: general-purpose computer computing power increase (creation of multicore processors, multiprocessor computer systems, supercomputers), and adaptation of the computer hardware to the executed algorithm (class of algorithms). The last approach often provides application of hardware accelerators – ASIC-based and FPGA-based, also named reconfigurable, and is characterized by better performance / power consumption ratio and lower cost as compared to the general-purpose computers of equivalent performance. However, such systems have typical problems. The ASIC-based accelerators: 1) they are effective only for certain classes of algorithms; 2) for effective application there is a need to adapt algorithms and software. The FPGA-based accelerators and reconfigurable computer systems (that use FPGAs as a processing units): 1) the need in the process of writing a program to perform computing tasks balancing among the general-purpose computer and FPGA; 2) the need of designing applicationspecific processors soft-cores; and 3) they are effective only for certain classes of problems, for which applicationspecific processors soft-cores were previously developed. This paper covers the scope of questions regarding concept of design, architecture, and proof of concept of the Self-Configurable FPGA-Based Computer Systems – an emerging type of high-performance computer systems, which are deprived of specified challenges. The method of information processing in reconfigurable computer systems and its improvements that allow an information processing efficiency to increase are shown. These improvements are used as a base for creating a new type of high-performance computer systems with reconfigurable logic, which are named self-configurable ones, and a new method of information processing in these systems. The structure of self-configurable FPGA-based computer system, the rules of application of computer software and hardware means necessary for these systems implementation are described. Major processes on the stages of program loading and execution in the self-configurable computer system are studied, and their durational characteristics are determined. On the basis of these characteristics, the expressions for evaluating the program execution duration in the self-configurable computer system are obtained. The directions for further works are discussed.

Evolution Domestic of Multichip Reconfigurable Computer Systems: from Air to Liquid Cooling: FROM AIR TO LIQUID COOLING

In the paper we consider the evolution of design technologies of reconfigurable computer systems based on FPGAs of various families. Five FPGA-based generations of reconfigurable computer systems with high placement density, from Xilinx Virtex-E to modern Virtex UltraScale, are described. We show results of design of high real performance energy-efficient reconfigurable computer systems. The main contribution is a liquid cooling system designed for Virtex UltraScale FPGAs. It provides independent circulation of the cooling liquid in the 19” 3U computational module for cooling of 96-128 FPGA chips that generate 9.6-12.8 kWatt of heat in total. The distinctive features of the designed immersion liquid cooling system are high cooling efficiency with power reserve for the designed perspective FPGA families, resistance to leaks and their consequences, and compatibility with traditional water cooling systems based on industrial chillers.

Immersion liquid cooling FPGA-based reconfigurable computer system

Abstract: The paper deals with problems of design of promising reconfigurable computer systems with liquid cooling and Xilinx Virtex UltraScale FPGAs used as principal components. Architecture, placement and comparative technical characteristics of liquid immersion cooling are considered in the paper. Results of design, prototyping, and experimental testing of principal technical solutions of a designed next-generation computational module are given. The computational module is intended for placement into a standard 47U computer rack (with the power of 150 kWatt) of high-performance computer systems with liquid cooling and with the performance of 1 PFlops. Reconfigurable computer systems with liquid cooling have considerable advantage of such parameters as real and specific performance, energetic efficiency, mass and dimensions characteristics. Compatibility with traditional water cooling systems, based on industrial chillers, reduces data center infrastructure requirements.

Distributed Monitoring System for Reconfigurable Computer Systems

The paper covers the history of development of reconfigurable computer systems including currently being developed modern system with independent circulation of the cooling liquid. The authors introduced the distributed monitoring system for reconfigurable computer systems which provides continuous status diagnostics of the computational module components for reduction of the low-productive time periods of equipment and for minimization of burden when worst-case situations are detected. High cooling efficiency with power reserve for the designed perspective FPGA families, resistance to leaks and their consequences, and compatibility with traditional water cooling systems based on industrial chillers are the distinctive features of the designed immersion liquid cooling system.

Parallel Application Porting by Means of Soft-Architectures

Abstract: In the paper we consider a method of porting of parallel applications to various reconfigurable computer systems with different soft-architectures and configurations. Our method of porting of parallel applications by means of soft-architectures contains a procedure of analysis and comparison of objects of the initial and the target soft-architectures, a procedure of analysis and comparison of connections of the ported parallel application and the target soft-architecture, a procedure which generates recommendations for modification of the target soft-architecture for successful porting. Together these procedures provide porting of the application to the target soft-architecture without additional modification and debugging of the application, and if porting is impossible the developer gets recommendations for modification of the target soft-architecture. Owing to this, it is possible to port the application, to simplify modification of the target soft-architecture and to reduce considerably the porting time. Owing to our new porting method, the parallel application is ported to a new soft-architecture without any additional modification of its source code, and its information graph is automatically mapped on various soft-architectures.

Погружная система охлаждения реконфигурируемых вычислительных систем на основе ПЛИС

Погружная система охлаждения реконфигурируемых вычислительных систем на основе ПЛИС

Operating System Design Challenges for a Reconfigurable Computing Environment

Objective: The primary objective of this proposal is to explore the areas of applications for a Reconfigurable computing system and further to analyze the challenges in designing an Operating System suitable for such a computing environment. Method: In this paper we have discussed at length the issues in designing an operating system which will practically be suitable for a Reconfigurable computing environment. The different challenges faced by an Operatin System in handling the applications executed by a conventional CPU are analysed. The advantages of using the Field Programmable Gate Array (FPGA) in Reconfigurable Computing System (RCS) to handle complex applications and to increase the efficiency and throughput of the system are also discussed. Findings: A primary comparison was made with all existing strategies used in Reconfigurable Computing Systems. The inferences obtained from this analysis gave a clear picture that the objective can be achieved by designing a new OS or making some modifications in the kernel of the OS. By achieving this task, multitasking between the applications or processes can be done frequently yielding a far better performance and throughput. The challenges faced by an OS in dealing with the applications executed by the RCS can be eliminated to a greater extent. Improvements: By adopting these kind of designing strategies for the OS in a system with the programmable gate array, there is a considerable improvement and performance of the device also the life span of the device is increased which is considered as most important criteria for any users in computing environment. The new architecture and performance analysis is a research prone area in many of the leading Universities.

Performance Analysis of OS Scheduling for a Reconfigurable Computing Environment

The primary objective of this proposal is to minimize the battery drain and to maximize the compatibility of the device so that the complexity of the device is much more reduced to enhance the battery period considerably. In this paper we adopted a method for increasing the response time using a priority based algorithm along with Field Programmable Gate Array (FPGA) in Reconfigurable Computing System (RCS) to handle complex applications and to increase the efficiency and throughput of the system. A primary comparison was made with all existing algorithms namely First Come First Serve (FCFS), Round Robin, Shortest Job First (SJF) for a given set of processes by taking process delay as a core parameter. The result obtained from this analysis gave a clear picture that the objective can be achieved by decreasing the waiting time and by increasing the throughput. By achieving this task, multitasking between the applications or processes can be done frequently. By adopting these kind of scheduling algorithms with programmable gate array, there is a considerable improvement and performance of the device. Also, the life span of the device is increased which is considered as most important criteria for any users in computing environment.

Development of the reconfiguration acceleration method in the dynamically reconfigurable computing systems

The problem of performance improvement of reconfigurable computing systems, including solving the problem of reconfiguration overhead reduction was considered. A new reconfiguration acceleration method and hardware for its implementation, which allow to minimize the reconfiguration time overhead were proposed. Analytical expressions that formalize the reconfiguration acceleration method, justify the virtually complete removal of unproductive reconfiguration time by reducing the communication component of time that provides an intensive reconfiguration acceleration were obtained. The formalization shows that the volume of the removed unproductive time component is linearly dependent on the number of repetitive tasks. Thus, using the proposed method is the most efficient in the algorithms that contain a large number of similar tasks. The proposed hardware for schedule management of placement and support of configurations of functional units, based on the multi-level memory, provide effective support of the reconfiguration overhead reduction method and allow to reduce computational complexity of reconfiguration control algorithms and solve the problem of limited resources of internal memory of the FPGA. The designed emulator of the reconfigurable computing system and software model of the reconfiguration acceleration method enable the real-time control simulation of reconfigurable resources. The developed software is a handy tool to study the temporal characteristics of the reconfigurable computing system. Simulation of the reconfiguration acceleration method for computing algorithms with the multilevel structure, which is experimentally confirmed by theoretical research was performed.

Современные и перспективные высокопроизводительные вычислительные системы с реконфигурируемой архитектурой

The paper covers the architecture and comparative specifications of reconfigurable computer systems (RCS) based on FPGAs of Xilinx Virtex-7 family: the computational modules 24V7-750 and Taygeta, which can be placed into a computational rack, and the reconfigurable desktop computational block Celaeno. Besides, the paper covers the architecture and assembly of the next-generation RCS based on liquid cooling, the results of prototyping of principal engineering solutions. The technology of implementation of applied tasks using the application development suit is considered. The next-generation RCS based on liquid cooling provide the performance up to 1 PFlops in a standard 47U computational rack with power consumption of 150 kWatts. It has a significant advantage of such technical and economical parameters as real and specific performance, power efficiency, mass and dimension parameters, etc. in comparison with other similar systems.

Средства программирования реконфигурируемых вычислительных систем на основе ПЛИС VIRTEX-7 с использованием софт-архитектур

The paper covers the existing design tools of digital devices in FPGAs, programming languages of reconfigurable computer systems and ability of their use for programming of multichip reconfigurable computer systems. Besides it deals with the high-level programming language COLAMO and the multichip solution development suite for reconfigurable computer systems that are developed in SRI MCS SFU. A particular attention is paid to a new programming approach, which consists in development and use of adjustable special-purpose soft-architectures which help to reduce the number of translations of FPGA bitstream files during debugging of parallel programs on reconfigurable computer systems. Owing to special-purpose soft-architectures it is possible to change communication links between devices and create required computing structures for user applications only by means of program adjustment and without re-loading FPGA bitstream files of the computational field. It considerably reduces the debugging time of parallel applications.

A Novel Methodology for Task Distribution in Heterogeneous Reconfigurable Computing System

Modern embedded systems are being modeled as Heterogeneous Reconfigurable Computing Systems (HRCS) where Reconfigurable Hardware i.e. Field Programmable Gate Array (FPGA) and soft core processors acts as computing elements. So, an efficient task distribution methodology is essential for obtaining high performance in modern embedded systems. In this paper, we present a novel methodology for task distribution called Minimum Laxity First (MLF) algorithm that takes the advantage of runtime reconfiguration of FPGA in order to effectively utilize the available resources. The MLF algorithm is a list based dynamic scheduling algorithm that uses attributes of tasks as well computing resources as cost function to distribute the tasks of an application to HRCS. In this paper, an on chip HRCS computing platform is configured on Virtex 5 FPGA using Xilinx EDK. The real time applications JPEG, OFDM transmitters are represented as task graph and then the task are distributed, statically as well dynamically, to the platform HRCS in order to evaluate the performance of the designed task distribution model. Finally, the performance of MLF algorithm is compared with existing static scheduling algorithms. The comparison shows that the MLF algorithm outperforms in terms of efficient utilization of resources on chip and also speedup an application execution.

Dynamic Task Distribution Model for On-Chip Reconfigurable High Speed Computing System

Modern embedded systems are being modeled as Reconfigurable High Speed Computing System (RHSCS) where Reconfigurable Hardware, that is, Field Programmable Gate Array (FPGA), and softcore processors configured on FPGA act as computing elements. As system complexity increases, efficient task distribution methodologies are essential to obtain high performance. A dynamic task distribution methodology based on Minimum Laxity First (MLF) policy (DTD-MLF) distributes the tasks of an application dynamically onto RHSCS and utilizes available RHSCS resources effectively. The DTD-MLF methodology takes the advantage of runtime design parameters of an application represented as DAG and considers the attributes of tasks in DAG and computing resources to distribute the tasks of an application onto RHSCS. In this paper, we have described the DTD-MLF model and verified its effectiveness by distributing some of real life benchmark applications onto RHSCS configured on Virtex-5 FPGA device. Some benchmark applications are represented as DAG and are distributed to the resources of RHSCS based on DTD-MLF model. The performance of the MLF based dynamic task distribution methodology is compared with static task distribution methodology. The comparison shows that the dynamic task distribution model with MLF criteria outperforms the static task distribution techniques in terms of schedule length and effective utilization of available RHSCS resources.

A Case Study: Task Scheduling Methodologies for High Speed Computing Systems

High Speed computing meets ever increasing real-time computational demands through the leveraging of flexibility and parallelism. The flexibility is achieved when computing platform designed with heterogeneous resources to support multifarious tasks of an application where as task scheduling brings parallel processing. The efficient task scheduling is critical to obtain optimized performance in heterogeneous computing Systems (HCS). In this paper, we brought a review of various application scheduling models which provide parallelism for homogeneous and heterogeneous computing systems. In this paper, we made a review of various scheduling methodologies targeted to high speed computing systems and also prepared summary chart. The comparative study of scheduling methodologies for high speed computing systems has been carried out based on the attributes of platform & application as well. The attributes are execution time, nature of task, task handling capability, type of host & computing platform. Finally a summary chart has been prepared and it demonstrates that the need of developing scheduling methodologies for Heterogeneous Reconfigurable Computing Systems (HRCS) which is an emerging high speed computing platform for real time applications.

DNA‐Programmed Dynamic Assembly of Quantum Dots for Molecular Computation

AbstractDespite the widespread use of quantum dots (QDs) for biosensing and bioimaging, QD‐based bio‐interfaceable and reconfigurable molecular computing systems have not yet been realized. DNA‐programmed dynamic assembly of multi‐color QDs is presented for the construction of a new class of fluorescence resonance energy transfer (FRET)‐based QD computing systems. A complete set of seven elementary logic gates (OR, AND, NOR, NAND, INH, XOR, XNOR) are realized using a series of binary and ternary QD complexes operated by strand displacement reactions. The integration of different logic gates into a half‐adder circuit for molecular computation is also demonstrated. This strategy is quite versatile and straightforward for logical operations and would pave the way for QD‐biocomputing‐based intelligent molecular diagnostics.

DNA-programmed dynamic assembly of quantum dots for molecular computation.

Despite the widespread use of quantum dots (QDs) for biosensing and bioimaging, QD-based bio-interfaceable and reconfigurable molecular computing systems have not yet been realized. DNA-programmed dynamic assembly of multi-color QDs is presented for the construction of a new class of fluorescence resonance energy transfer (FRET)-based QD computing systems. A complete set of seven elementary logic gates (OR, AND, NOR, NAND, INH, XOR, XNOR) are realized using a series of binary and ternary QD complexes operated by strand displacement reactions. The integration of different logic gates into a half-adder circuit for molecular computation is also demonstrated. This strategy is quite versatile and straightforward for logical operations and would pave the way for QD-biocomputing-based intelligent molecular diagnostics.

RECONFIGURABLE CELL-ARRAY (RCA) BASED COMPUTER SYSTEM WITH CELL SPECIALIZATION

Reconfigurable system based on cell specialization of reconfigurable cell-array computer system is presented. Analysis of specialized reconfigurable cell-array hardware and methods of specialized cell inclusion are given.

Introduction to the TRETS Special Section on the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS'12)

Introduction to the TRETS Special Section on the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS'12)