Reconfigurable Chips Research Articles

Laser fabrication of modular superhydrophobic chips for reconfigurable assembly and self-propelled droplet manipulation

Natural creatures that enables controllable liquid transport provides the inspiration for developing novel microfluidic devices by engineering functional surfaces with superwettability. However, towards microfluidic applications, the strict requirements of sophisticated droplet manipulation make it challenging to reach this end. In this work, we report a conceptually new self-propelled droplet manipulation strategy based on reconfigurable superhydrophobic chips. The modular droplet chip (MDC) is developed by laser embossing a series of superhydrophobic structures on elastomer jigsaws that act as functional units. MDC is potable since only gravity is used as the driving force for dynamic manipulation of liquid droplets, including droplets transporting, splitting, merging and bouncing without mass loss. The MDC demonstrated reasonable anti-cross-contamination property due to the water repellence of the superhydrophobicity. Modular assembly of MDC enables different chip functions including solution dilution, SERS detection, cell labeling and chemical synthesis. As a miniature and portable experimental platform, the MDC is promising for next-generation lab-on-a-chip systems.

Reconfigurable TPM Implemented with Ultralow-Power Management in 28nm CMOS Process for IoT SoC Design

There have been amazing developments in the security applications of sensors for Internet of Things (IoT), which lead to the increasing demand for the System-on-a-Chip (SoC) based on Trusted Platform Module (TPM). Low-power design has become the key to enhancing the competitiveness of IoT’s product. The reconfigurable design can effectively reduce power consumption under the condition of ensuring the performance of the system. In this paper, a reconfigurable TPM with a power management module using 28nm CMOS process is proposed, which guarantees the energy saving and effectiveness of the chip. By integrating clock management, power management and multi-voltage management strategy, the designed TPM power management unit achieved a dynamic power reduction level of $$72.61\%$$ , a leakage power reduction level of $$82.05\%$$ and a total power reduction of $$72.68\%$$ with the combination of reconfigurable TPM chips without ultralow-power management.

Reconfigurable computing: toward software defined chips

With the rapid development of technology, software is rapidly evolving with emerging applications. Chips that fail to adapt to software (e.g., application-specific integrated circuits, ASICs) suffer from a short lifecycle and high nonrecurring engineering (NRE) costs. Meanwhile, as the projection of Moores law and Dennard scaling are decreasing, energy efficiency has shown a diminishing return with new technologies. The computing capacity of general-purpose processors is limited due to power budgets. Consequently, future chips must jointly optimize flexibility, power efficiency, and ease of programmability. Reconfigurable chips combine the high flexibility of a general-purpose processor and high energy efficiency of ASIC by providing on-demand customization of their architectures. This article thoroughly reviews the development and architecture of reconfigurable chips. Moreover, the future challenges of reconfigurable chips are analyzed. Based on these challenges, future directions are also discussed.

Levenberg-Marquardt based MLP for Detection and Classification of Power Quality Disturbances

In recent years, power quality (PQ) has become an important issue for utilities and users. In order to improve PQ, a method for detecting and classifying power quality disturbances (PQDs) is proposed. Hence in addition to identifying the disturbance signals, the proposed method is able to determine its type when occurring. This approach is based on Multilayer perceptron and Levenberg-Marquardt training rule. It is inspired by the desire to take advantage of the parallelism inherent to neural networks in view of hardware implementation using reconfigurable chips. The inputs of these networks are the samples obtained on the power grid in various conditions. The proposed method is tested for sags and swells. To classify the disturbances, the neural architectures have been generalized and configured according to the number and type of disturbances to be treated. To validate and test the proposal, a grid model was built with a three-phase fault generator under Matlab / Simulink R2017a. After comparing the results with those obtained by certain methods in the literature, the proposal proves to be an efficient and reliable tool for monitoring PQ. In fact it has the smallest mean square error and a highperformance with precision of 96%.

A design methodology for mobile and embedded applications on FPGA-based dynamic reconfigurable hardware

With the proliferation of mobile/embedded devices, multiple running applications are becoming a necessity on these devices. Thus, state-of-the-art techniques are needed to support complex applications running on mobile systems. We envision in the near future, many mobile devices will be implemented/delivered on FPGA-based reconfigurable chips. Previous analysis illustrated that FPGA-based dynamic-reconfigurable-hardware is currently the best option to deliver embedded applications that have stringent requirements. However, computation models and application characteristics play significant roles in determining whether this hardware is indeed a good match for specific embedded applications. Furthermore, selecting a specific dynamic reconfiguration method (out of many) and designing the corresponding hardware architectures for an application are important and challenging tasks. This paper proposes a design methodology for FPGA-based dynamic-reconfigurable-hardware that provides guidelines in mapping application's computation models and characteristics to the most suitable reconfiguration methods. Pipelined and functional-parallel models are used as case studies to illustrate the design methodology.

A design methodology for mobile and embedded applications on FPGA-based dynamic reconfigurable hardware

With the proliferation of mobile/embedded devices, multiple running applications are becoming a necessity on these devices. Thus, state-of-the-art techniques are needed to support complex applications running on mobile systems. We envision in the near future, many mobile devices will be implemented/delivered on FPGA-based reconfigurable chips. Previous analysis illustrated that FPGA-based dynamic-reconfigurable-hardware is currently the best option to deliver embedded applications that have stringent requirements. However, computation models and application characteristics play significant roles in determining whether this hardware is indeed a good match for specific embedded applications. Furthermore, selecting a specific dynamic reconfiguration method (out of many) and designing the corresponding hardware architectures for an application are important and challenging tasks. This paper proposes a design methodology for FPGA-based dynamic-reconfigurable-hardware that provides guidelines in mapping application's computation models and characteristics to the most suitable reconfiguration methods. Pipelined and functional-parallel models are used as case studies to illustrate the design methodology.

Asynchronous logiс one-level LUT design based on partial acknowledgement

In the paper, asynchronous logic design targeting LUT of custom size (number of inputs) implementation is proposed. It is based on conventional Sum-Of-Product terms (SOP) what differs from existing methods where Sum-Of-Minterms (SOM) and Disjoint SOP are supposed. It is shown, that LUT architectural features and delays ensure SOP hazard-free implementation. Nowadays reconfigurable chips contain multiple LUTs that can be combined using so called dedicated multiplexers. It implies producing LUT-based structure of various inputs number to match design needs. As a result, a function can be implemented using one-level LUT which increases the circuit performance. It is in contrast to the conventional approach where multi-level implementation is supposed. The model consists of functional and completion detection (CD) blocks. Both blocks are implemented using LUTs. LUTs total size is an optimization criterion. The method of LUTs total size minimization is proposed where inputs are removed from CD block and partially acknowledged via functional one. The problem is formulated as a covering task. Two sets of benchmarks are processed and comparison is done. Using our method, improvement w.r.t mention criterion is achieved.

Modeling and Simulation Speed-Up of Plasma Actuators Implementing Reconfigurable Hardware

The objective of the present study is to investigate the capability of field-programmable gate array hardware in numerical simulation of a model of a dielectric barrier discharge plasma actuator to accelerate the calculations. The reconfigurable hardware is designed such that it is possible to reprogram its architecture after manufacturing. This provides the capability to design and implement various architectures for several applications. Two reconfigurable chips are used in the present study, one of which consists of a programmable logic unit and a typical microprocessor. This hybrid architecture makes the high performance of the reconfigurable hardware in custom computing and the efficiency of the microprocessor in data flow control accessible. An automated design procedure is used for the design of the reconfigurable hardware. Further, a finite difference representation of a phenomenological model of a plasma actuator is derived and implemented on the field-programmable gate array hardware. The results are validated against other numerical data, and the computational time is compared to different conventional processors. Using the reconfigurable hardware results in up to 96% computational time reduction compared to a recent Core i7 processor.

Retraction Note: A new compaction strategy for enhancing the utilization of reconfigurable chips

Field programmable gate arrays (FPGAs) are designed to implement any logic circuit with the ability to host several independent tasks simultaneously. They inherit reconfigurability from their programmable architecture. However, designs are usually dynamic and the arrival times of tasks may be unknown in advance. Accordingly, FPGA should have the ability to: (1) place incoming tasks at run time, and (2) compact the chip whenever needed. Compaction is a proposed solution to alleviate external fragmentations. It tries to move running tasks closer to each others to free a sufficient area for hosting more tasks. Unfortunately, traditional compaction techniques suffer from internal and external fragmentations. This paper introduces a novel puzzle-based compaction (PBC) technique. PBC is a shape-aware technique that is the first to take the task shape into consideration. Hence, it succeeds not only to eliminate the internal fragmentations but also to minimize the external fragmentations. Moreover, the paper develops a novel formula, which is the first not to estimate, but to exactly calculate the amount of external fragmentations generated by hosting a set of tasks inside the reconfigurable chip. Experimental results have shown that PBC outperforms recent compaction techniques in which the chip utilization has reached 87 %.

Ultrafast physical generation of random numbers using hybrid Boolean networks

We describe a high-speed physical random number generator based on a hybrid Boolean network with autonomous and clocked logic gates, realized on a reconfigurable chip. The autonomous logic gates are arranged in a bidirectional ring topology and generate broadband chaos. The clocked logic gates receive input from the autonomous logic gates so that random numbers are generated physically that pass standard randomness tests without further postprocessing. The large number of logic gates on reconfigurable chips allows for parallel generation of random numbers, as demonstrated by our implementation of 128 physical random number generators that achieve a real-time bit rate of 12.8Gbits/s.

A Reconfigurable Logic Cell Based on a Simple Dynamical System

This paper introduces a new scheme to achieve a dynamic logic gate which can be adjusted flexibly to obtain different logic functions by adjusting specific parameters of a dynamical system. Based on graphical tools and the threshold mechanism, the distribution of different logic gates is studied, and a transformation method between different logics is given. Analyzing the performance of the dynamical system in the presence of noise, we discover that it is resistant to system noise. Moreover, we find some part of the system can be considered as a leaky integrator which has been already widely applied in engineering. Finally, we provide a proof-of-principle hardware implementation of the proposed scheme to illustrate its effectiveness. With the proposed scheme in hand, it is convenient to build the flexible, robust, and general purpose computing devices such as various network coding routers, communication encoders or decoders, and reconfigurable computer chips.

RETRACTED ARTICLE: A new compaction strategy for enhancing the utilization of reconfigurable chips

RETRACTED ARTICLE: A new compaction strategy for enhancing the utilization of reconfigurable chips

A Novel Puzzle Based Compaction (PBC) Strategy for Enhancing the Utilization of Reconfigurable Resources

Partially reconfigurable field programmable gate arrays (FPGAs) can accommodate several independent tasks simultaneously. FPGA, as all reconfigurable chips, relies on the “host-then-compact-when-needed” strategy. Accordingly, it should have the ability to both place incoming tasks at run time and compact the chip whenever needed. Compaction is a proposed solution to alleviate external fragmentations problem, trying to move running tasks closer to each other in order to free a sufficient area for new tasks. However, compaction conditions the suspension of the running tasks, which introduces a high penalty. In order to increase the chip area utilization as well as not affecting the response times of tasks, efficient compaction techniques become increasingly important. Unfortunately, traditional compaction techniques suffer from a variety of faults. This paper introduces a novel Puzzle Based Compaction (PBC) technique that is a shape aware technique, which takes the tasks shapes into consideration. In this regard, it succeeded not only to eliminate the internal fragmentations but also to minimize the external fragmentations. This paper develops a novel formula, which is the first not to estimate, but to exactly calculate the amount of external fragmentations generated by accommodating a set of tasks inside the reconfigurable chip.

True Front-to-Back Analogue IC Designers' Training

Analogue and mixed-signal sensor electronics comprise a small yet essential fraction of a large variety of embedded and integrated systems in industrial application systems. While the number of devices is considerably smaller than in massively parallel digital systems, the design of each device requires much more care, time and experience; moreover, learning the skills required for analogue and mixed-signal sensor electronics can be tedious, and these challenges are not taken up by a sufficient number of students to meet industry demands, in particular of the booming sensor and microelectromechanical systems industries. To attract more students to this topic, we offer design courses that combine theoretical and practical skills based on state-of-the-art tools and technologies. Students undertake (individually or in small groups) analogue/mixed signal design projects, but, due to the time constraints common in engineering courses, they are often unable to test to their designs. Drawing from research work and results on dynamically reconfigurable sensor electronics, we have tackled this problem by giving students an opportunity to download their dimensioning solution into certain reconfigurable devices and to carry out testing and measurement to characterise their designs. To this end, we introduced the true front-to-back (TFB) analogue IC designers training kit, used in the CAD laboratory at the Institute of Integrated Sensor Systems (ISE) in TU-Kaiserslautern for various engineering curricula. This paper gives the details of the teaching concepts and state of implementation, the reconfigurable hardware platform and typical results for student design and measurement activities. Finally, we give an outlook on upcoming reconfigurable chips.

From Newton to Einstein – N-body dynamics in galactic nuclei and SPH using new special hardware and astrogrid-D

The dynamics of galactic nuclei containing multiple supermassive black holes is modelled including relativistic dynamics. It is shown that for certain initial conditions there is no stalling problem for the relativistic coalescence of supermassive black hole binaries. This astrophysical application and another one using a smoothed particle hydrodynamics code are our first use cases on a new computer architecture using GRAPE and new MPRACE accelerator cards based on reconfigurable chips, developed in the GRACE project. We briefly discuss our science applications and first benchmarks obtained with the new hardware. Our present architecture still relies on the GRAPE special purpose hardware (not reconfigurable), but next generations will focus on new architectural approaches including custom network and computing architectures. The new hardware is embedded into national and international grid infrastructures.

News Briefs

Topics covered include a new approach to creating reconfigurable chips, the use of W-direct technology for improved wireless communications, and a technology that turns a cell phone into a motion-detection game controller.

Industry trends - Reconfiguring wireless phones with adaptive chips

Cellular phone manufacturers are on the horns of a dilemma. On one hand, the demand for their products continues to grow. On the other hand, cellular-phone technology is also changing rapidly. Vendors are dealing with this problem by using an adaptive (also called reconfigurable) chips in a new way. With this approach, software can redraw a chip's physical circuitry on the fly, letting a single processor perform multiple functions. In addition, adaptive computing could increase performance while reducing energy consumption.

Adaptive computing’s impact?

“We're coming upon a sea change in the world of semiconductors,” says Nick Tredennick, former designer of the Motorola 68000 microprocessor, which powered the Apple Mac in the 1980s and early 90s. “There are compelling advantages to reconfigurable chips in terms of performance and power consumption.” The momentum for adaptive computing is a result of advances in special high-speed memory chips called static ram, or S-RAM chips that make it possible to imitate the entire hardware circuits of a processor on a single chip. In adaptive computing, chip wiring would be reconfigured on the fly by software altering the circuitry’s information pathways. Reconfigurable chips may offer speed, cost and energy-saving advantages, and allow for quicker product design cycles. And the ability to combine the functions of many chips into one would be particularly desirable in making smaller, lighter and more energy-efficient portable computing and communications devices. Cellphones that could work worldwide; portable computers that use suitable radio frequency and wirelessly, automatically connect to the Internet, or consumer electronics gadgets able to adjust to each new technical standard in digital sights and sounds, offer enormous attractions with upgrades as easy as downloading the latest circuit design from the Internet. The fixed-circuit approach needs templates, or masks at $1m for each new circuit, making it difficult for product designers to quickly adapt to changing markets and technology formats. But for an adaptive circuit, that investment is not unreasonable. Reconfigurable chip design has several dozen start-ups (eg QuickSilver, and GateChange Technologies), as well interesting the giants. Intel, IBM, Infineon, Motorola and Texas, have all moved into both acquisition and spin-off. Infineon acquired Morphics Technology (reconfigurable circuits for wireless digital telephone networks). Royal Philips Electronics acquired Systemonic, (reconfigurable chips for wireless data applications). Motorola invested in Morpho Technologies (reconfigurable circuits for wireless, imaging and multimedia applications). HP research laboratories has spun off two adaptive companies, Synfora (Program-In Chip-Out PICO) and Elixent (Reconfigurable Algorithm Processing RAP). Reconfigurable looks as if its coming to stay. This is a short news story only. Visit www.three-fives.com for the latest advanced semiconductor industry news.

A PARALLEL ALGORITHM TO GENERATE N-ARY REFLECTED GRAY CODES IN A LINEAR ARRAY WITH RECONFIGURABLE BUS SYSTEM

A simple parallel algorithm for generating N-ary reflected Gray codes is presented. The algorithm is derived from the pattern of N-ary reflected Gray codes. The algorithm runs on a linear processor array with a reconfigurable bus system. A reconfigurable bus system is a bus system whose configuration can be dynamically changed. Recently processor arrays with reconfigurable bus systems were used to solve many problems in constant time. There already exists experimental reconfigurable chips.

Disjoint Covers in Replicated Heterogeneous Arrays

Reconfigurable chips are fabricated with redundant elements that can be used to replace the faulty elements. The fault cover problem consists of finding an assignment of redundant elements to the faulty elements such that all of the faults are repaired. In reconfigurable chips that consist of arrays of elements, redundant elements are configured as spare rows and spare columns.This paper considers the problem in which a chip contains several replicates of a heterogeneous array, one or more sets of spare rows, and one or more sets of spare columns. Each set of spare rows is identical to the set of rows in the array, and each set of spare columns is identical to the set of columns in the array. Specifically, an ith spare row can only be used to replace an ith row of an array, and similarly with spare columns. Repairing the chip reduces to finding a cover for the faults in each of the arrays. These covers must be disjoint; that is, a particular spare row or spare column can be used in the cover of at most on...