Reconfigurable Architecture Research Articles

Reconfigurable Architecture and Dataflow for Memory Traffic Minimization of CNNs Computation.

Computation of convolutional neural network (CNN) requires a significant amount of memory access, which leads to lots of energy consumption. As the increase of neural network scale, this phenomenon is further obvious, the energy consumption of memory access and data migration between on-chip buffer and off-chip DRAM is even much more than the computation energy on processing element array (PE array). In order to reduce the energy consumption of memory access, a better dataflow to maximize data reuse and minimize data migration between on-chip buffer and external DRAM is important. Especially, the dimension of input feature map (ifmap) and filter weight are much different for each layer of the neural network. Hardware resources may not be effectively utilized if the array architecture and dataflow cannot be reconfigured layer by layer according to their ifmap dimension and filter dimension, and result in a large quantity of data migration on certain layers. However, a thorough exploration of all possible configurations is time consuming and meaningless. In this paper, we propose a quick and efficient methodology to adapt the configuration of PE array architecture, buffer assignment, dataflow and reuse methodology layer by layer with the given CNN architecture and hardware resource. In addition, we make an exploration on the different combinations of configuration issues to investigate their effectiveness and can be used as a guide to speed up the thorough exploration process.

Ensuring the resilience of the national security of the Republic of Moldova in the context of increasing the geopolitical coordinate of covid-19 pandemic phenomenon

The research of the fundamental problem for ensuring the institutional resilience of the national security of the Republic of Moldova during the COVID-19 pandemic consists of the analysis of the geopolitical coordinate of the international events that determines the process of transforming the regional and international security environment. COVID-19 pandemic phenomenon can be considered a multi-dimensional global crisis in which the foreign policy actions of the great powers and regional powers have intensified in order to influence the reconfiguration of the geopolitical architecture of the international security system and the security complex structure in different regions of the world. The main idea of the subject proposed for scientific examination consists of investigating the impact of the geopolitical context of the regional security environment during the global pandemic generated by the new type of COVID-19 Coronavirus on the process of ensuring national security of the Republic of Moldova. Profifi ling fifi rst the examination of the political-military cooperation relations between the Republic Moldova and the North Atlantic Alliance, especially during the COVID-19 pandemic, contributed to the elucidation of the opportunities provided by the Alliance to increase the level of the institutional resilience of the national security and defense system of the Republic of Moldova, which needs further substantial support of the development partners, by ensuring the adjustment of the national security components to the Euro-Atlantic standards that will strengthen the capability and interoperability degree in the national security and defense field, thus discouraging possible menaces and counteracting current risks and threats.

Area-Delay-Power Efficient VLSI Architecture of FIR Filter for Processing Seismic Signal

Low-complexity, high-speed and re-configurability are the primary requirements of the finite impulse response (FIR) filters employed for the processing of acquired seismic signal in real-time seismic-alert-system. The common sub-expression elimination (CSE) technique is employed widely to reduce the hardware complexity by minimizing the logic operators (LOs) and logic depths (LDs) in digital FIR filter. In this brief, a novel matrix grouped CSE (MCSE) algorithm has been proposed which outperforms the existing CSE algorithms in terms of LOs and LDs minimization. Moreover, a new half-unit biased (HUB) based rounding technique is incorporated in the proposed design to reduce the truncation error while maintaining low-complexity and the cut-set retiming technique is employed to reduce the critical-path-delay (CPD). Two hardware efficient FIR filter architectures (I and II) involving the proposed canonical signed digit (CSD) based MCSE algorithm, HUB rounding and cut-set retiming approach have been presented. Further, the architecture II represents a hardware efficient realization of a reconfigurable FIR filter. The hardware implementation of the architectures is performed on both FPGA and ASIC platforms. The hardware implementation of the proposed architecture I yields more than 25%, 49%, 38%, 36% and, 31% reduction in LOs, CPD, effective latency, area-delay-product (ADP) and, power-delay-product (PDP), respectively, over the state-of-the-art CSE based architectures. Whereas the reconfigurable architecture II exhibits nearly 48%, 12% and, 13% reduction in CPD, ADP and, PDP over the counterpart.

A Reconfigurable Arbiter MPUF With High Resistance Against Machine Learning Attack

Physical unclonable function (PUF) is an emerging hardware security primitive which is increasingly used to authenticate and identify Internet of Things (IoT) devices. Spin-transfer torque magnetoresistive random access memory (STT-MRAM) provides new opportunities for novel PUFs due to inherent randomness sources, such as process variations, stochastic switching, and chaotic magnetization. In this article, we propose a hybrid STT-MRAM/complementary metal-oxide semiconductor (CMOS)-based reconfigurable arbiter PUF (MPUF) with enhanced performance metrics in terms of reliability, uniqueness, and uniformity. This design has a mean intra-hamming distance (HD) of 0.147%, a mean inter-HD of 50.21%, and passes the National Institute of Standards and Technology (NIST) statistical tests. The proposed arbiter MPUF features distinct advantages, such as reconfigurable architecture, challenge-dependent stage delays, and huge challenge-response pair (CRP) space. Moreover, the robustness of the proposed MPUF against machine learning (ML)-based modeling attacks is tested using three ML algorithms, namely support vector machine (SVM), linear regression (LR), and multilayer perceptron (MLP). Results show that the proposed reconfigurable arbiter MPUF is resistant to ML attacks and minimizes the ML attack prediction accuracy to less than 65.12% without XOR and less than 44.34% with XOR. Meanwhile, the correlation power analysis demonstrates that the proposed MPUF is also resilient to side-channel attacks.

A Flexible Digitally Controlled Oscillator Structure to Reconfigure the Frequency Band in Multi-band RF AD-PLL System

Reconfigurable architectures are more prominent in modern-day multi-band radio systems. This work has been conceptualized for a flexible 8-bit digitally controlled oscillator (DCO) design to suit reconfigurable RF all-digital phase-locked loop applications. To efficiently utilize the area, power consumption and attend to several operating frequencies, an optimal design of LC-tank based DCO topology with both L and C components contributing to the coarse and fine-tuning of the DCO’s frequency of oscillation has been proposed. The design has been carried out in the Cadence Spectre RF tool with UMC180 nm technology. The proposed 8-bit DCO exhibits wide bandwidth, generating 240 oscillating frequencies in the LTE frequency band and occupies less area of 70 × 18 µm. The frequency of oscillation varies from 491.5 MHz to 3.392 GHz designed for an 8-bit digital control word with a tuning range percentage of 149%. The maximum phase noise obtained is −103.57 dBc/Hz @ 10 MHz offset causing a figure of merit (FOM) of −144.167 dBc/Hz. The total power consumed by the DCO ranges from 1.05 to 9.5 mW approximately.

You Only Traverse Twice: A YOTT Placement, Routing, and Timing Approach for CGRAs

Coarse-grained reconfigurable architecture (CGRA) mapping involves three main steps: placement, routing, and timing. The mapping is an NP-complete problem, and a common strategy is to decouple this process into its independent steps. This work focuses on the placement step, and its aim is to propose a technique that is both reasonably fast and leads to high-performance solutions. Furthermore, a near-optimal placement simplifies the following routing and timing steps. Exact solutions cannot find placements in a reasonable execution time as input designs increase in size. Heuristic solutions include meta-heuristics, such as Simulated Annealing (SA) and fast and straightforward greedy heuristics based on graph traversal. However, as these approaches are probabilistic and have a large design space, it is not easy to provide both run-time efficiency and good solution quality. We propose a graph traversal heuristic that provides the best of both: high-quality placements similar to SA and the execution time of graph traversal approaches. Our placement introduces novel ideas based on “you only traverse twice” (YOTT) approach that performs a two-step graph traversal. The first traversal generates annotated data to guide the second step, which greedily performs the placement, node per node, aided by the annotated data and target architecture constraints. We introduce three new concepts to implement this technique: I/O and reconvergence annotation, degree matching, and look-ahead placement. Our analysis of this approach explores the placement execution time/quality trade-offs. We point out insights on how to analyze graph properties during dataflow mapping. Our results show that YOTT is 60.6 , 9.7 , and 2.3 faster than a high-quality SA, bounding box SA VPR, and multi-single traversal placements, respectively. Furthermore, YOTT reduces the average wire length and the maximal FIFO size (additional timing requirement on CGRAs) to avoid delay mismatches in fully pipelined architectures.

CGRA-EAM—Rapid Energy and Area Estimation for Coarse-grained Reconfigurable Architectures

Reconfigurable architectures are quickly gaining in popularity due to their flexibility and ability to provide high energy efficiency. However, reconfigurable systems allow for a huge design space. Iterative design space exploration (DSE) is often required to achieve good Pareto points with respect to some combination of performance, area, and/or energy. DSE tools depend on information about hardware characteristics in these aspects. These characteristics can be obtained from hardware synthesis and net-list simulation, but this is very time-consuming. Therefore, architecture models are common. This work introduces CGRA-EAM (Coarse-Grained Reconfigurable Architecture - Energy & Area Model), a model for energy and area estimation framework for coarse-grained reconfigurable architectures. The model is evaluated for the Blocks CGRA. The results demonstrate that the mean absolute percentage error is 15.5% and 2.1% for energy and area, respectively, while the model achieves a speedup of close to three orders of magnitude compared to synthesis.

RETRACTED ARTICLE: An energy-efficient reconfigurable accelerators in multi-core systems using PULP-NN

Emerging developments in embedded computer systems and applications demand low energy consumption and high performance. Owing to increased demand for low-voltage computing and lowered technology returns, academia and industry are interested primarily in energy-efficient accelerators. Hardware accelerators have the greatest disadvantage that they are not programmable. It can also be misused for a particular task. The number of accelerators in a device can cause scalability problems. Flexibility and scalability issues are present in programmable accelerators. Coarse-grained reconfigurable architecture (CGRA) design, implementation, computer systems integration and compilation for CGRA are the key contributions in this proposed design. First of all in parallel ultra-low-power processing system (PULP), the CGRA-based integrated programmable array (IPA) is implemented. Second, PULP-NN is a coding library that has been developed for the RISC-V cluster with parallel, high–low storage. The key development in PULP-NN is that the latest move towards aggressive quantization of deep neural network inferences which is a collection of kernels which use bytes and sub-byte information types up to INT-1. The library in the proposed procedure utilizes advanced sign handling expansions in the RISC-V PULP processors and in bunch matches, to accomplish ideal energy effectiveness of estimation execution.

Reconfigurable Fiber Wireless IFoF Fronthaul With 60 GHz Phased Array Antenna and Silicon Photonic ROADM for 5G mmWave C-RANs

We demonstrate experimentally a bandwidth-reconfigurable mmWave Fiber Wireless (FiWi) fronthaul bus topology for spectrally efficient and flexibly reconfigurable 5G Centralized-Radio Access Networks (C-RAN). The proposed fronthaul architecture includes four 1 Gb/s Intermediate Frequency over Fiber (IFoF) channels that can be flexibly allocated among two in-series Reconfigurable Optical Add/Drop Multiplexer (ROADM) integrated nodes, supporting in total 8 V-band 32-element Phased Array Antenna (PAA) terminals. The ROADM was fabricated as an integrated photonic device exploiting the ultra-low loss Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> TriPleX waveguide integration platform and an architectural layout based on cascaded MZI interleavers. The device has flat top response of 32.5 GHz with a Free Spectral Range (FSR) of 100 GHz and fiber-to-fiber losses of 5 dB, while the V-band PAA supports analog RF beamsteering capabilities within a 90°-sector and 1m wireless distance. Each of the FiWi links carries a 250 MBd QAM16 waveform enabling a total of 1 Gb/s rate per end user beam, complying with the 5G Key Performance Indicator (KPI) user-rate requirement. Bandwidth-reconfigurability is experimentally demonstrated by selectively dropping channels either at the first or at the second ROADM node, allowing in this way the bandwidth allocation to be flexibly defined between two different network segments. Both uplink and downlink performance are experimentally validated for different ratios of bandwidth allocation among the two nodes, revealing Error Vector Magnitude (EVM) values that meet the respective 3GPP signal quality specifications. The two-stage FiWi IFoF/mmWave fronthaul bus topology, based on a miniaturized, integrated, low loss Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> ROADM and supporting high-capacity wireless beamsteering capability can form a promising roadmap towards flexible and reconfigurable 5G C-RAN architectures.

Manufacturing Execution System Integration through the Standardization of a Common Service Model for Cyber-Physical Production Systems

Digital transformation and artificial intelligence are creating an opportunity for innovation across all levels of industry and are transforming the world of work by enabling factories to embrace cutting edge Information Technologies (ITs) into their manufacturing processes. Manufacturing Execution Systems (MESs) are abandoning their traditional role of legacy executing middle-ware for embracing the much wider vision of functional interoperability enablers among autonomous, distributed, and collaborative Cyber-Physical Production System (CPPS). In this paper, we propose a basic methodology for universally modeling, digitalizing, and integrating services offered by a variety of isolated workcells into a single, standardized, and augmented production system. The result is a reliable, reconfigurable, and interoperable manufacturing architecture, which privileges Open Platform Communications Unified Architecture (OPC UA) and its rich possibilities for information modeling at a higher level of the common service interoperability, along with Message Queuing Telemetry Transport (MQTT) lightweight protocols at lower levels of data exchange. The proposed MES architecture has been demonstrated and validated in several use-cases at a research manufacturing laboratory of excellence for industrial testbeds.

DiaNet: An elastic neural network for effectively re-configurable implementation

An elastic neural network is developed and evolved towards effectively re-configurable hardware in fully parallel on chip. The original prototype of DiaNet is organized as a symmetrical bisection neural network, which is feasible to be partitioned into arbitrary pieces of neural networks (NNs) without redundancy. To prevent the depth explosion in implementing complex tasks (complicated pattern recognition for instance), the evolution of DiaNets is investigated in this work. By using the I/O layer integration technology which enables all neurons in the hidden layer of DiaNet to receive inputs, the number of layers is reduced to 8.8% of DiaNet prototype. In this manner, the DiaNet topology is feasible to implement complex NNs without the risk of depth explosion. Moreover, the skip connection technology is proposed to avoid the gradient vanishing due to deep learning, which is significant to DiaNets especially. Compared with the LeNet5 model as state-of-the-art, the evolved DiaNet topology achieves the parameter reduction of 90.86% for MNIST recognition with the negligible loss of accuracy. To reduce hardware utilization, the sensitivity to the decline of computational precision and bit-width is investigated to suggest the guideline for efficient hardware implementations. Finally, the effectiveness of DiaNet is verified by the proposed re-configurable architecture on FPGA with the power reduction of 10.8% compared to state-of-the-art implementations.

A Dynamic Reconfigurable Architecture for Hybrid Spiking and Convolutional FPGA-Based Neural Network Designs

This work presents a dynamically reconfigurable architecture for Neural Network (NN) accelerators implemented in Field-Programmable Gate Array (FPGA) that can be applied in a variety of application scenarios. Although the concept of Dynamic Partial Reconfiguration (DPR) is increasingly used in NN accelerators, the throughput is usually lower than pure static designs. This work presents a dynamically reconfigurable energy-efficient accelerator architecture that does not sacrifice throughput performance. The proposed accelerator comprises reconfigurable processing engines and dynamically utilizes the device resources according to model parameters. Using the proposed architecture with DPR, different NN types and architectures can be realized on the same FPGA. Moreover, the proposed architecture maximizes throughput performance with design optimizations while considering the available resources on the hardware platform. We evaluate our design with different NN architectures for two different tasks. The first task is the image classification of two distinct datasets, and this requires switching between Convolutional Neural Network (CNN) architectures having different layer structures. The second task requires switching between NN architectures, namely a CNN architecture with high accuracy and throughput and a hybrid architecture that combines convolutional layers and an optimized Spiking Neural Network (SNN) architecture. We demonstrate throughput results from quickly reprogramming only a tiny part of the FPGA hardware using DPR. Experimental results show that the implemented designs achieve a 7× faster frame rate than current FPGA accelerators while being extremely flexible and using comparable resources.

Un Emprendimiento minero “al estilo inglés”

In the mid-19th century, several mining projects were developed in the west of Catamarca province (Argentina), mainly dedicated to the exploitation of copper. In that context, the Casa Lafone stood out –among other things– for presenting itself as an “English-style” company, differentiated from the rest by the technology used and by the way in which the tasks and different aspects related to the workers' lives were organized. In this paper we seek to characterize the operation of this mining establishment by focusing on the way in which people lived, worked and circulated as a result of spatial and architectural reconfigurations and, consequently, of times, rhythms, types and forms of work. We propose that these reconfigurations constituted subtle but no less powerful forms of workers control and discipline that, together with other actions, implied major changes and impacts on the landscape and resources and mainly on the life of the people who lived and worked there.

A scalable and reconfigurable hybrid AC/DC microgrid clustering architecture with decentralized control for coordinated operation

Microgrid clusters are effective to increase utilization of renewable energy resources (RESs), and improve reliability and stability of power systems. Facilitating flexible configurations, grid networking and coordinated operation among multiple microgrids are essential for the microgrid cluster. In view of this, this paper presents a scalable and reconfigurable hybrid microgrid clustering architecture and a corresponding decentralized control method. Initially, a new interlinking converter referred as energy networking unit (ENU) is proposed. The ENU is used to interface the AC and DC subgrid in single hybrid microgrid, and also facilitates the connection with the external power grid. Then the ENU-based hybrid microgrid clustering architecture is established, which is characterized by scalability, reconfigurability and modularity. Thanks to the reconfigurable topology of ENUs, the architecture could realize flexible AC/DC interconnection between microgrids by the same converter modules with less power conversion units. Finally, a proposed decentralized control strategy for this architecture could realize autonomous power exchange between subgrids in single microgrid with considering energy storage restrictions and smooth mode switch. And an adaptive and autonomous power interaction among neighboring microgrids is also achieved with full utilization of the compensation capacity of clusters, thus improving the system reliability, as well as the utilization and local consumption of RESs. The effectiveness of the proposed clustering architecture and decentralized control strategy is verified by comprehensive cases.

Are There Biomimetic Lessons from Genetic Regulatory Networks for Developing a Lunar Industrial Ecology?

We examine the prospect for employing a bio-inspired architecture for a lunar industrial ecology based on genetic regulatory networks. The lunar industrial ecology resembles a metabolic system in that it comprises multiple chemical processes interlinked through waste recycling. Initially, we examine lessons from factory organisation which have evolved into a bio-inspired concept, the reconfigurable holonic architecture. We then examine genetic regulatory networks and their application in the biological cell cycle. There are numerous subtleties that would be challenging to implement in a lunar industrial ecology but much of the essence of biological circuitry (as implemented in synthetic biology, for example) is captured by traditional electrical engineering design with emphasis on feedforward and feedback loops to implement robustness.

Efficient reconfigurable architecture for moving object detection with motion compensation

The detection and tracking of object in large data surveillance requires a proper motion estimation and compensation techniques which are generally used to detect accurate movement from video stream. In this paper, a novel hardware level architecture involving motion detection, estimation, and compensation is proposed for real-time implementation. The motion vectors are obtained using 16×16 sub-blocks with a novel parallel D flip flop architecture in this work to arrive at an optimised architecture. The sum of absolute difference (SAD) is then calculated by optimized absolute difference and adder blocks designed using kogge-stone adder which helps in improving the speed of the architecture. The controller block is designed by finite state machine model used for synchronization of all the operations. Further, the comparator and compensation blocks are optimized by using basic logical elements and the Kogge-stone adder. Finally, the proposed architecture is implemented on Zynq Z7-10 field-programmable gate array (FPGA) and simulated using System Generator tool for real time traffic signal. The hardware and software parameters are compared with the existing techniques which shows that the proposed architecture is efficient than existing methods of design.

Antipsychotics Effects on Network-Level Reconfiguration of Cortical Morphometry in First-Episode Schizophrenia.

Cortical thickness reductions are evident in schizophrenia (SZ). Associations between antipsychotic medications (APMs) and cortical morphometry have been explored in SZ patients. This raises the question of whether the reconfiguration of morphological architecture by APM plays potential compensatory roles for abnormalities in the cerebral cortex. Structural magnetic resonance imaging was obtained from 127 medication-naive first-episode SZ patients and 133 matched healthy controls. Patients received 12 weeks of APM and were categorized as responders (n = 75) or nonresponders (NRs, n = 52) at follow-up. Using surface-based morphometry and structural covariance (SC) analysis, this study investigated the short-term effects of antipsychotics on cortical thickness and cortico-cortical covariance. Global efficiency was computed to characterize network integration of the large-scale structural connectome. The relationship between covariance and cortical thinning was examined by SC analysis among the top-n regions with thickness reduction. Widespread cortical thickness reductions were observed in pre-APM patients. Post-APM patients showed more reductions in cortical thickness, even in the frontotemporal regions without baseline reductions. Covariance analysis revealed strong cortico-cortical covariance and higher network integration in responders than in NRs. For the NRs, some of the prefrontal and temporal nodes were not covariant between the top-n regions with cortical thickness reduction. Antipsychotic effects are not restricted to a single brain region but rather exhibit a network-level covariance pattern. Neuroimaging connectomics highlights the positive effects of antipsychotics on the reconfiguration of brain architecture, suggesting that abnormalities in regional morphology may be compensated by increasing interregional covariance when symptoms are controlled by antipsychotics.

Reconfigurable Slip Vectoring Control in Four In-Wheel Drive Electric Vehicles

Controllability, maneuverability, fault-tolerance/isolation and safety are significantly enhanced in electric vehicles (EV) equipped with the redundant actuator configuration of four-in-wheel electric motors (4IWM). A highly reconfigurable architecture is proposed and illustrated for the adaptive, nonmodel-based control of 4IWM-EVs. Given the longitudinal force, yaw-moment requests and the reconfiguration matrix, each IWM is given a slip reference according to a Slip Vectoring (SV) allocation strategy, which minimizes the overall slip vector norm. The distributed electric propulsion and the slip vector reference allow for a decentralized online estimation of the four-wheel torque-loads, which are uncertain depending on loading and road conditions. This allows for the allocation of four different torques depending on individual wheel conditions and to determine in which region (linear/nonsaturated or nonlinear/saturated) of the torque/slip characteristics each wheel is operating. Consequently, the 4IWMs can be equalized or reconfigured, including actuator fault-isolation as a special case, so that they are enforced to operate within the linear tire region. The initial driving-mode selection can be automatically adjusted and restored among eighteen configurations to meet the safety requirements of linear torque/slip behavior. Three CarSim realistic simulations illustrate the equalization algorithm, the quick fault-isolation capabilities and the importance of a continuous differential action in a critical double-lane-change maneuver.

Blockchain-based digital twin sharing platform for reconfigurable socialized manufacturing resource integration

The emergence of social manufacturing has facilitated the evolution of resource organization in the manufacturing industry, with a trend towards a flat management structure. The mass absorption of socialized idle resources that lack a digitalized and intelligent basis has influenced the efficiency of collaborative production. The digital twin has been widely applied to promote cyber collaboration through the multidimensional digitalization of physical resources. As a knowledge-intensive software entity, it is impractical for resource owners, especially individuals and small and micro businesses, to implement digital twins. To make sufficient use of the sharing convenience in the social manufacturing community (SMC), this paper proposes a blockchain-based digital twin sharing platform to enable software copyright protection and simplify heterogeneous manufacturing resource integration in decentralized and distributed environments. Domain-driven design is adopted as the major methodology to recognize the problem domain and partition the business subdomains. Blockchain technology is introduced to construct a novel sharing schema to preserve and retrieve the copyrights of digital twins under a distributed and decentralized SMC network. Furthermore, to enhance the reusability of digital twins, a reconfigurable digital twin architecture is proposed to enable UPnP implementation of shared digital twins under heterogeneous deployment environments. Finally, a demonstrative case study motivated by a real-life 3D printing scenario is conducted to verify and evaluate the proposed platform.

MLUTNet: A Neural Network for Memory Based Reconfigurable Logic Device Architecture

Neural networks have been widely used and implemented on various hardware platforms, but high computational costs and low similarity of network structures relative to hardware structures are often obstacles to research. In this paper, we propose a novel neural network in combination with the structural features of a recently proposed memory-based programmable logic device, compare it with the standard structure, and test it on common datasets with full and binary precision, respectively. The experimental results reveal that the new structured network can provide almost consistent full-precision performance and binary-precision performance ranging from 61.0% to 78.8% after using sparser connections and about 50% reduction in the size of the weight matrix.