Recessed Channel MOSFET Research Articles

Assessment of high-k gate stacked In2O5Sn gate recessed channel MOSFET for x-ray radiation reliability

This work reports the effect of x-ray radiation on In2O5Sn based Transparent Gate Recessed Channel (TGRC) MOSFET with the high-k dielectric at the sub-20 nm regime. Reliability of TGRC-MOSFET with a high-k dielectric in harsh radiation environment (x-ray radiation in the 1k to 10k rad dose range after irradiation) is the main aim of this analysis using TCAD simulation. Results reveal that HfO2 as a gate stack on SiO2 improves the device reliability and enhances the drain current, hole trap density, threshold voltage shift, and radiation sensitivity as compared to Al2O3 and ZrO2 gate stack with 1k rad to 10 k rad radiation doses. Trap/de-trap model has been used for interface charging as well as insulator along with the electron-hole pair generation and recombination. Further, the thermal effect on threshold voltage and sensitivity has also been evaluated. Results suggest that the proposed device with a high-k dielectric is more reliable in the x-ray radiation environment at the sub 20 nm scale. This device finds enormous applications in the clinical and space environment along with signal amplification and a processing circuit.

Analysis of structural parameters on sensitivity of black phosphorus junctionless recessed channel MOSFET for biosensing application

This paper presents a technology computer-aided design analysis of an ultrasensitive black phosphorus junctionless recessed channel MOSFET as a biosensor. A nano cavity gap is embedded in the gate insulator region (for molecules immobilization) due to which gate capacitance changes owing to the accumulation of different molecules which reflects the deviation in threshold voltage. Higher sensitivity (1.7) is achieved for protein at low Vds (0.2 V) in comparison to streptavidin (1.17) and Biotin (1.24). Further, the effect of cavity gap length and oxide thickness variation is also examined. All the results pave the way for early detection techniques of protein-related diseases such as Alzheimer’s diseases, ovarian cancer and coronary artery disease with the existing complementary metal–oxide–semiconductor technology.

In2O5Sn based transparent gate recessed channel MOSFET: RF small-signal model for microwave applications

This paper discusses the small signal RF model of Transparent Gate Recessed Channel (TGRC) MOSFET using a 3D TCAD device simulator. Small signal model is studied in terms of microwave parameters such as S (scattering) parameters, Z (impedance) parameters, Y (admittance) parameters, and h (hybrid) parameters with an aim to analyze the behavior of TGRC MOSFET at microwave frequency. All the results of TGRC-MOSFET have been compared with Conventional Recessed Channel (CRC) MOSFET having aluminum as gate metal electrode. Modeled results have also been compared with simulation results and found good agreement with the 3D-simulation results. Moreover, it is perceived from the results that 99.4% enhancement in the input impedance of TGRC-MOSFET and input admittance is improved by 32.9% in the proposed device (TGRC-MOSFET) in comparison to CRC-MOSFET. It has also been observed that the transit (cut-off) frequency (fT) and maximum oscillator frequency (fMAX) enhances significantly by 42.85% and 123% respectively in TGRC MOSFET owing to the remarkable reduction in intrinsic capacitances. Results reveal that the proposed device design improves the small signal behavior thus, may provide detailed insight to RF engineers for microwave applications and testing of RF ports.

Comprehensive analysis of sub-20 nm black phosphorus based junctionless-recessed channel MOSFET for analog/RF applications

In this work, a comprehensive analog and RF performance of a novel Black Phosphorus-Junctionless-Recessed Channel (BP-JL-RC) MOSFET has been explored at 45 nm technology node (Gate length = 20 nm). The integration of black phosphorus with junctionless recessed channel MOSFET, leads to higher drain current of about 0.3 mA and excellent switching ratio (of the order of 1011) due to reduced off-current which leads to improvement in sub-threshold slope (SS) (67mV/dec). Further, RF performance metrics have also been studied with an aim to analyze high-frequency performance. The following FOMs have been evaluated: cut-off frequency (fT), maximum oscillator frequency (fMAX), stern stability factor, various power gains and parasitic capacitances at THz frequency range. Thus, in addition to the high packing density offered by RC MOSFET, the proposed design finds numerous application at THz frequency making it a promising candidate at wafer scale integration level.

An extensive investigation of work function modulated trapezoidal recessed channel MOSFET

The concept of silicon on insulator (SOI) and grooved gate help to lessen the short channel effects (SCEs). Again the work function modulation along the metal gate gives a better drain current due to the uniform electric field along the channel. So all these concepts are combined and used in the proposed MOSFET structure for more improved performance. In this work, trapezoidal recessed channel silicon on insulator (TRC-SOI) MOSFET and work function modulated trapezoidal recessed channel silicon on insulator (WFM-TRC-SOI) MOSFET are compared with DC and RF parameters and later linearity of both the devices is tested. An analytical model is formulated by using a 2-D Poisson’s equation and develops a compact equation for threshold voltage using minimum surface potential. In this work we analyze the effect of negative junction depth and the corner angle on various device parameters such as minimum surface potential, sub-threshold slope (SS), drain induced barrier lowering (DIBL) and threshold voltage. The analysis interprets that the switching performance of WFM-TRC-SOI MOSFET surpasses TRC-SOI MOSFET in terms of high Ion/Ioff ratio and also the proposed structure can minimize the short channel effects (SCEs) in RF application. The validity of proposed model has been verified with simulation result performed on Sentaurus TCAD device simulator.

Investigation of parasitic capacitances of In2O5Sn gate electrode recessed channel MOSFET for ULSI switching applications

This work discusses the capacitance–voltage (C–V) analysis and frequency dependent capacitance of In2O5Sn (Tin Oxide) gate electrode Recessed Channel (TGRC) MOSFET with an aim to examine the effectiveness of In2O5Sn (Transparent) as a gate material on parasitic capacitance which prominently influences the current driving capability and thus, the switching performance. Moreover, capacitance dependent parameters such as Transconductance Frequency Product (TFP), Energy Delay Product (EDP) and Gain Bandwidth Product (GBP) are also assessed and found that, TFP increases to 6.33 times in comparison to metal gate RC MOSFET owing to a noticeable reduction in parasitic capacitance (Cgg = Cgs + Cgd), due to which EDP and GBP also improve considerably and thus reflects its effectiveness in RF amplifiers and receivers. In addition, the effect of parameter variation such as gate length (Lg) and negative junction depth (NJD) of TGRC is also observed, and results reveal that with Lg = 20 nm and NJD = 5 nm, TGRC unveils outstanding switching performance which is desirable for low power ULSI applications.

TCAD RF performance investigation of Transparent Gate Recessed Channel MOSFET

In this paper, analog/RF performance and small signal behavior of Transparent Gate Recessed Channel (TGRC) MOSFET has been investigated in terms of transconductance, DIBL, channel resistance parasitic capacitances, cut-off frequency and maximum oscillator frequency. Results so obtained are compared with Conventional Recessed Channel (CRC) MOSFET at THz frequency range, using ATLAS-3D device simulator. Furthermore, the impact of technology parameter variations in terms of gate length (Lg) has also been evaluated. Result shows that there is 42% enhancement in cut-off frequency, 132% increment in maximum oscillator frequency and significant improvement in parasitic capacitances for TGRC-MOSFET due to reduced short channel effects (SCEs) and enhanced on-current driving capabilities thus, reflecting its significance in high-frequency THz range applications.

Analysis of novel transparent gate recessed channel (TGRC) MOSFET for improved analog behaviour

In this paper, a novel device structure called transparent gate recessed channel MOSFET (TGRC-MOSFET) is proposed to alleviate the hot carrier effects for the advanced nanometer process. TGRC-MOSFET involving a recessed channel and incorporates indium tin oxide as a transparent gate. TCAD analysis shows that the performance of TGRC-MOSFET surpasses conventional recessed channel (CRC)-MOSFET in terms of high ION/IOFF ratio and better carrier transport efficiency in comparison to CRC-MOSFET. This simulation divulges the reduction in hot-carrier-effects metrics like electron velocity, electron temperature, potential, and electron mobility. Furthermore, the effect of gate length is observed on the analog behavior of TGRC-MOSFET. All the simulations have been done using DEVEDIT-3D and ATLAS device simulator. The work proposes the novel design for reduced hot carrier and low power switching applications.

Frequency Dependence of Noise Performance Metrices forGate Electrode Work Function Engineered RecessedChannel MOSFET

Frequency Dependence of Noise Performance Metrices forGate Electrode Work Function Engineered RecessedChannel MOSFET

Leakage current mechanisms in sub-50 nm recess-channel-type DRAM cell transistors with three-terminal gate-controlled diodes

We investigated the leakage mechanism in the recently developed DRAM cell transistors having deeply recessed channels for sub-50nm technology using a gate-controlled diode method. The identification and modeling of the various leakage components in DRAM cell transistors with three-dimensional structures is of great importance for the estimation of their data retention characteristics. Our study reveals that there is a significant difference in the leakage mechanisms of planar and recessed channel MOSFETs, due to their different geometrical aspects. The leakage current at the extended gate–drain overlapping region in recessed channel MOSFETs is of particular importance from the viewpoint of their refresh modeling. The information on the leakage characteristics of three-dimensional DRAM cell transistors obtained herein will be very useful for refresh modeling and future DRAM device designs.

Analytic Threshold Voltage Model of Recessed Channel MOSFETs

Threshold voltage is one of the most important factors in a device modeling. In this paper, analytical method to calculate threshold voltage for recessed channel (RC) MOSFETs is studied. If we know the fundamental parameter of device, such as radius, oxide thickness and doping concentration, threshold voltage can be obtained easily by using this model. The model predicts the threshold voltage which is the result of 2D numerical device simulation.

Gate material engineered‐trapizoidal recessed channel MOSFET for high‐performance analog and RF applications

AbstractIn this article, device characteristics of gate material engineered‐trapezoidal recessed channel (GME‐TRC) MOSFET are investigated using device simulators, ATLAS and DEVEDIT. Further, proposed device is examined for cutoff frequency (FT) and parasitic capacitances, and result offers the opportunity for realizing the reliability of GME‐TRC MOSFET for high‐speed logic and RF applications. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 694–698, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25012

Modeling of Polysilicon Depletion Effect in Recessed-Channel MOSFETs

The polysilicon depletion effect is one of the key factors that degrade MOSFETs' performance. In this letter, a polysilicon depletion model for recessed-channel (RC) MOSFETs is presented. The model shows good agreement with numerical device simulation results. We also compare the polysilicon depletion effect of RC MOSFETs to that of planar MOSFETs.

A comparative study of the DRAM leakage mechanism for planar and recessed channel MOSFETs

We have experimentally analyzed the leakage mechanism by comparing the planar DRAM cell and the recently developed DRAM cell transistors that have deeply recessed channels. We have identified important differences in the leakage mechanisms between planar MOSFETs and recessed channel MOSFETs, so we can suggest guidelines with respect to the optimal device structures for the recessed channel DRAM cell.

On the structure of the recessed-channel MOSFET for sub-100 nm Si CMOS

A theoretical study is presented to understand misalignment tolerance and process window for channel depth in the recessed-channel MOSFET for sub-100 nm Si CMOS. Simulations of the device at 100 nm demonstrate that the device is misalignment tolerant if it possesses two features: (1) symmetric source/drain (S/D) doping profiles and (2) a T-shaped gate. In addition, a relatively positive S/D junction depth with respect to the recessed channel provides a process window for channel depth. Therefore, a new device structure is proposed for the recessed-channel MOSFET, T-gate recessed-channel MOSFET, which can be fabricated with standard Si CMOS processes.

A novel 0.1 μm MOSFET structure with inverted sidewall and recessed channel

To solve the problems of trade-off between the short channel effect and the performance enhancement of sub-quartermicrometer MOSFETs, we have developed a recessed channel MOSFET structure called ISRC (Inverted-Sidewall Recessed-Channel). The oxide thickness is 4 nm and the effective channel length is 0.1 μm, which is the smallest Si-MOSFET ever reported in the recessed channel structures. The maximum saturation transconductance at V/sub D/=2 V is 446 mS/mm for the 0.1 μm n-channel device. The threshold voltage roll-off is kept within 64 mV when the gate length varies from 1.4 μm to 0.1 μm and good subthreshold characteristics are achieved for 0.1 μm channel device.

Short-channel effect immunity and current capability of sub-0.1-micron MOSFET's using a recessed channel

Sub-0.1-/spl mu/m planar and gate recessed MOSFET's are investigated using both drift-diffusion and Monte Carlo simulations. In nonplanar devices, the influence of the gate corner explains that the threshold voltage roll-off can be almost suppressed. A steeper subthreshold slope (low swing) is also obtained for a channel length shorter than 50 nm when the recessed channel MOSFET is compared to its planar counterpart. The influence of the corner effect on high-current performances is also considered in relation with the electric field profile along the Si/SiO/sub 2/ interface.

A new 0.25- mu m recessed-channel MOSFET with selectively halo-doped channel and deep graded source/drain

To improve the performance and reliability of deep submicron MOS devices, a gate-recessed MOSFET (GR-MOSFET), which has a selectively halo-doped recessed channel and a deep graded source/drain formed without counterdoping, is proposed. The GR-MOS structure, which adopts a new doping concept, eliminates the tradeoff between drain-induced barrier lowering (DIBL) and hot-carrier effect, which are important to deep submicron device design. It also reduces the V/sub T/ lowering effect and the lateral electric field at the drain. A 0.25- mu m GR-MOSFET with a 10-nm gate oxide has exhibited 15% higher transconductance and 10% increased saturation current at V/sub D/=V/sub G/=3.3 V, 1 V higher BV/sub DSS/, and six times less substrate current compared with an LDD-MOSFET of the same device dimensions. >