Recess Etching Research Articles

Normally-off AlGaN/GaN-based MOS-HEMT with self-terminating TMAH wet recess etching

Normally-off AlGaN/GaN-based MOS-HEMT has been fabricated by utilizing damage-free self-terminating tetramethyl ammonium hydroxide (TMAH) recess etching. The device exhibited a threshold voltage of +2.0 V with good uniformity, extremely small hysteresis of ∼20 mV, and maximum drain current of 210 mA/mm. The device also exhibited excellent off-state performances, such as breakdown voltage of ∼800 V with off-state leakage current as low as ∼10−12 A and high on/off current ratio (Ion/Ioff) of 1010. These excellent device performances are believed to be due to the high quality recessed surface, provided by the simple self-terminating TMAH etching.

Exponential dependence of capture cross section on activation energy for interface traps in Al2O3/AlN/AlGaN/GaN metal-insulator-semiconductor heterostructures

This paper presents a systematic study on the interface traps in AlGaN/GaN metal-insulator-semiconductor (MIS) heterostructures with an atomic layer deposited Al2O3/AlN gate stack. The interface trap density in MIS heterostructures with and without recess gate is estimated to be 2.76 × 1013 eV−1 cm−2 and 2.38 × 1013 eV−1 cm−2, respectively, by using the conductance method. The capture cross section, extracted from Arrhenius fitting, shows an exponential increase from 1.73 × 10−18 cm2 to 1.07 × 10−16 cm2 with an increase in trap activation energy from 0.21 eV to 0.47 eV for MIS heterostructures with recess gate, while the exponentially related capture cross section and activation energy for the case without recess gate are 1.19 × 10−18–2.36 × 10−12 cm2 and 0.15–0.82 eV, respectively. The voltage-dependent measurement enables different interface traps detectable which are continuously distributed within the bandgap, and the exponential dependence of the capture cross section on activation energy is attributed to the entropy change accompanying electron emission from interface traps to the conduction band. The comparison between devices with and without recess gate shows that recess etching leads to a decrease in the linear dependence factor of activation energy on gate voltage from 0.61 to 0.52 and also slightly reduces the influence of atomic vibration on electron emission.

Ultra-low rate dry etching conditions for fabricating normally-off field effect transistors on AlGaN/GaN heterostructures

Enhancement-mode transistors with uniform turn-on threshold voltage (Vth) can be achieved using low damage and low rate gate recess etching techniques. In this work, dry etching conditions for a AlGaN/GaN heterostructure with an ultra-low etching rate of 1.5 nm/min were demonstrated and we succeeded the possibility to achieve a low etch rate of an AlGaN/GaN heterostructure in a Cl2/BCl3 plasma using inductively coupled plasma (ICP). The etching development was successfully implemented in the achievement of a normally-off GaN/AlGaN based transistor. The optimal recess depth was determined after fabrication of various devices with different recess depth values and with various dry etching conditions and after examining the performances of fabricated devices various conditions, and determining the dependence of recess time. The optimized etching condition resulted in low damage and smooth morphology of the etched AlGaN/GaN surfaces. Fine control of the depth of the gate region recess was achieved for the AlGaN/GaN heterostructure without any etch-stop layer, and validated for the fabrication of field effect transistors (FETs) using conventional processes. The fabricated normally-off Al2O3/AlGaN/GaN MOSFETs delivered a high positive Vth of +5.64 V with a low off-state leakage current of ∼10−7 A/mm and lower current collapse.

Normally-off fully recess-gated GaN metal–insulator–semiconductor field-effect transistor using Al2O3/Si3N4 bilayer as gate dielectrics

By a self-terminating gate recess etching technique, a normally-off fully recess-gated GaN metal–insulator–semiconductor field-effect transistor (MISFET) was fabricated using Al2O3/Si3N4 bilayer as gate dielectrics. Owing to the high breakdown electric field (∼10 MV/cm) of the gate dielectrics, the device exhibits a large gate swing of 18 V, a high threshold voltage of 1.7 V (at ID = 100 µA/mm), a large maximum drain current of 534 mA/mm, a gate leakage current lower than 20 nA/mm in the whole gate swing, and a high OFF-state breakdown voltage of 1282 V. Furthermore, owing to the high gate overdrive (VGS − VTH), the on-resistance of the device only increases by 5.4% under a constant stress of VGS/VDS = 18 V/1 V.

Neutral beam process in AlGaN/GaN HEMTs: Impact on current collapse

In this paper, we report a promising approach for the gate recess process with a suppressed current collapse in GaN-based high electron mobility transistors (HEMTs) by means of neutral beam (NB). A recessed gate structure has been widely studied as a way to realize normally-off operation in GaN, InP, and GaAs-based HEMTs. Since GaN-based materials are usually etched by dry process, plasma-induced damage is a serious concern. NB is free from electrical charges and UV photons, resulting in an accurate control of etching depth and less plasma-induced damages. In this work, we introduce NB irradiation to the gate interface and measured DC and gate-pulsed output characteristics. The results suggest that NB is applicable for the gate recess etching with suppressing the current collapse.

Precise thickness control in recess etching of AlGaN/GaN hetero-structure using photocarrier-regulated electrochemical process

The photocarrier-regulated electrochemical (PREC) process was developed for fabricating recessed-gate AlGaN/GaN high-electron-mobility transistors (HEMTs) for normally off operation. The PREC process is based on photo-assisted electrochemical etching using low-energy chemical reactions. The fundamental photo-electrochemical measurements on AlGaN/GaN heterostructures revealed that the photo-carriers generated in the top AlGaN layer caused homogeneous etching of AlGaN with a smooth surface, but those generated in the GaN layer underneath caused inhomogeneous etching that roughens the surface. The concept of the PREC process is to supply the photo-carriers generated only in the AlGaN layer by selecting proper conditions on light wavelength and voltage. The phenomenon of self-termination etching has been observed during the PREC process, where the etching depth was controlled by light intensity. The recessed-gate AlGaN/GaN HEMT fabricated with the PREC process showed positive threshold voltage and improvement in transconductance compared to planar-gate AlGaN/GaN HEMTs.

Normally-Off AlGaN/GaN Mos-Hemts Using ZrO2 Gate Dielectric with Tuneable Charge

GaN-based high electron mobility transistors (HEMTs) are of significant interest for next-generation RF power amplifiers and monolithic microwave integrated circuits (MMICs). The integration of a gate dielectric in a MOS-HEMT device has been shown to offer significantly reduced gate leakage, resulting in improved reliability and reduced off-state power consumption. ZrO2 has attracted increasing attention as a candidate gate insulator for GaN-based HEMTs, due to a high dielectric constant (25), large bandgap (5.9 eV), and high breakdown voltage (15-20 MV/cm). We have previously reported high positive threshold voltage in unpassivated HEMT structures with recessed barrier layers and ZrO2 gate dielectrics deposited using zirconium (IV) tert-butoxide (ZTB) as the Zr precursor [1]. In this work, we compare these devices to structures incorporating the more common tetrakis(dimethylamino)zirconium (TDMA-Zr) precursor, which is expected to exhibit less fixed oxide charge. Combined with the optional barrier recess step, we demonstrate threshold voltage control over a range of 7V for a given HEMT layer structure. We also report the integration of SiNX passivation layers and an evaluation of the dynamic switching performance of the devices. AlGaN/GaN HEMT devices structures were grown on Si substrates by MOCVD, and devices were fabricated following standard GaN device process steps described elsewhere [1]. ZrO2 layers were deposited by atomic layer deposition using both ZTB and TDMA-Zr precursors and deionized water. Ellipsometry and X-ray photoelectron spectroscopy (XPS) were used to verify thickness and identify film stoichiometry. Capacitance-voltage measurements were initially used to characterize the oxide. A dielectric constant of 25 was extracted, and interface trap density was on the order of ~1x1012, dependent upon the nature of the oxide and the surface upon which it was deposited (HEMT structure vs GaN MOS capacitor). Gated Hall measurements were used to characterize the 2DEG mobility and sheet carrier density, both in the HEMT structure and in the recessed region under the gate. The non-recessed devices exhibit comparable current density, transconductance, and ON-resistance. The threshold voltage is shifted positive for device structures incorporating the ZTB-derived ZrO2 film, approaching enhancement mode even without the barrier recess and demonstrating an exceptionally high +4V with a barrier recess. The mechanism for this is proposed to be the presence of negative charge in the oxide film, potentially due to excess oxygen in the film. The presence of such charge was verified on GaN capacitor structures. In contrast, the TDMA-Zr-derived ZrO2 films exhibit a negative VT shift due to the thicker effective barrier, just reaching enhancement mode operation even with a full barrier recess. The breakdown voltage was comparable among all device structures both with and without recess. As expected, the gate leakage was suppressed over 5 orders of magnitude compared to the reference Schottky gated HEMT. Pulsed I-V measurements indicate a degraded current collapse behavior in the ZTB-based devices, which is expected as the negative charge from the oxide would be expected to enhance the charge trapping effect. In contrast, the TDMA-Zr-based device structures exhibit comparable current collapse to the reference device, and possibly even represent an improvement due to reduced trapping under the gate in the MOS structure. Similar behavior in the recessed gate structure indicates minimal permanent damage from the plasma recess etch. In conclusion, we have demonstrated enhancement mode AlGaN/GaN MOS-HEMTs with a thin ALD-ZrO2 gate oxide and barrier recess. The integration of this particular high-k dielectric in the device structure results in a positive threshold voltage shift due to negative charge in the oxide film and at the interface, which when integrated with a barrier recess enables a VT ~+4V while suppressing gate leakage by 4 orders of magnitude compared to a reference Schottky-gated HEMT. 1. T.J. Anderson, et. al. Appl. Phys. Express 9, 071003 (2016)

Impact of Recess Etching on the Temperature-Dependent Characteristics of GaN-Based MIS-HEMTs With Al2O3/AlN Gate-Stack

This paper studied the recess-etching effects on the temperature-dependent characteristics of AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) with Al2O3/AlN gate-stack. The 12.6 nm recess-etching resulted in voltage shift of capacitance-voltage curves by 2.4 V, improved peak field-effect mobility ( $\mu _{\text {FE}})$ from 1906 to 2036 cm2/ $\text{V}\cdot \text{s}$ , and increased peak transconductance ( ${g}_{\text {max}})$ from 272 to 353 mS/mm. The temperature-dependent measu-rement from 298 to 473 K showed decrease in maximum drain current, ${g}_{\text {max}}$ , and $\mu _{\text {FE}}$ for both devices with and without recess etching, attributed to thermal electron emission and carrier depletion effects. Recess etching did not degrade the thermal stability of carrier distribution and the transport properties. Temperature-dependent $\mu _{\text {FE}}$ analysis revealed that optical phonon scattering dominated the transport mechanism of Al2O3/AlN/ AlGaN/GaN MIS-HEMTs. Optical phonon energy of 74 and 77 meV were obtained for the devices with and without recess etching, respectively.

High Electron and Hole Mobility by Localized Tensile & Compressive Strain Formation Using Ion Implantation and Advanced Annealing of Group IV Materials (Si+C, Si+Ge & Ge+Sn)

Since the 90nm node the industry has been using S/D-stressor for strain-channel formation and increased hole & electron mobility. The S/D-stressor strain-Si method required optimizing the deep S/D junction with the shallow SDE implant junction. PMOS used recess etch eSiGe for p+ S/D tensile strain with precise lateral gate overlap distance control to induce channel compressive strain for increased hole mobility in Si while NMOS n+ S/D compressive strain is formed by deep amorphous implant with carbon and stacking fault dislocation defects that induces channel tensile strain for increased electron mobility in Si. With the switch in transistor design from 2-D planar to 3-D FinFET by the industry at the 22nm and 14/16nm nodes, increasing eSiGe Ge content above 55% has reached it’s limit in strain-Si S/D-stressor of -3GPa for hole mobility improvement therefore requiring higher mobility channel material at 10nm and beyond by using: 1) relaxed >70% SiGe to 100% Ge or 2) compressive strain >50% SiGe to 100% Ge for higher hole mobility. Higher electron mobility requires: 1) relaxed >95% SiGe to 100% Ge, 2) tensile strain-Si on >25% relaxed-SiGe or 3) tensile strain >50% SiGe to 100% Ge. Using CVD epitaxial growth of SiGe and Ge requires thick SRB (strain relaxed buffer) epilayers by blanket or selective epitaxial growth but this results in threading dislocation in the 106 to 109 /cm2 level results in high n+ and p+ junction leakage. The reported targets for NMOS is 2% tensile channel strain of >1.5GPa while for PMOS, 2% compressive channel strain of >-1.5GPa at 7nm node [1]. This paper will review strain-Si and strain-Ge formation by ion implantation and advanced annealing to form tensile and compressive strain channel for improved electron and hole mobility in Group IV materials. Carbon and Si implants was used to form surface tensile strained-channel SiC, GeC and GeSi material while Ge and Sn implants was used to form surface compressive strained-channel SiGe, SiGeSn and GeSn material. Improved hole mobility (µh) by >4x and electron mobility (ue) by >2x have been reported by use of implantstrain formation [2,3]. References 1] R. Kim et al., IEDM-2015, paper 34.1. 2] J. Borland et al., IWJT-2013, paper S4-4, p.49. 3] J. Borland et al., IWJT-2015, paper S2-1, p.12.

Fabrication of normally-off AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors by photo-electrochemical gate recess etching in ionic liquid

We characterized an ionic liquid (1-butyl-3-methylimidazolium nitrate, C8H15N3O3) as a photo-electrochemical etchant for fabricating normally-off AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs). Using the ionic liquid, we achieved an etching rate of ∼2.9 nm/min, which is sufficiently low to facilitate good etching control. The normally-off AlGaN/GaN MIS-HEMT was fabricated with an etching time of 6 min, with the 20 nm low-pressure chemical vapor deposition (LPCVD) silicon nitride (Si3N4) gate dielectric exhibiting a threshold voltage shift from −10 to 1.2 V, a maximum drain current of more than 426 mA/mm, and a breakdown voltage of 582 V.

Impact of recess etching and surface treatments on ohmic contacts regrown by molecular-beam epitaxy for AlGaN/GaN high electron mobility transistors

Ohmic contacts fabricated by regrowth of n+ GaN are favorable alternatives to metal-stack-based alloyed contacts in GaN-based high electron mobility transistors. In this paper, the influence of reactive ion dry etching prior to regrowth on the contact resistance in AlGaN/GaN devices is discussed. We demonstrate that the dry etch conditions modify the surface band bending, dangling bond density, and the sidewall depletion width, which influences the contact resistance of regrown contacts. The impact of chemical surface treatments performed prior to regrowth is also investigated. The sensitivity of the contact resistance to the surface treatments is found to depend upon the dangling bond density of the sidewall facets exposed after dry etching. A theoretical model has been developed in order to explain the observed trends.

Mechanism of Ti/Al/Ti/W Au-free ohmic contacts to AlGaN/GaN heterostructures via pre-ohmic recess etching and low temperature annealing

The physical mechanism of low-thermal-budget Au-free ohmic contacts to AlGaN/GaN heterostructures is systematically investigated with current-voltage, high-resolution transmission electron microscopy, and temperature-dependent contact resistivity characterizations. With a low annealing temperature of 600 °C, pre-ohmic recess etching of the AlGaN barrier down to several nanometers is demonstrated to be an effective method to reduce the contact resistance between Ti/Al/Ti/W ohmic metals and AlGaN/GaN heterostructures. However, further over recess of the AlGaN barrier leads to only sidewall contact to 2D electron gas channel and thus degraded contact performance. It is verified by temperature-dependent contact resistivity measurements that field emission (tunneling) dominates the current transport mechanism in Au-free ohmic contacts with AlGaN barrier partially and over recessed, while both field emission and thermionic emission contribute to traditional Ti/Al/Ni/Au ohmic contacts to AlGaN/GaN heterostructures that annealed at high temperature (850 °C).

Monolithic Integration of an Active InSb-Based Mid-Infrared Photopixel With a GaAs MESFET

Medium wavelength infrared (MWIR) detectors are of increasing importance in defense, security, commercial, and environmental applications. Enhanced integration will lead to greater resolution and lower cost focal plane arrays (FPAs). We present the monolithic fabrication of an active photopixel made in InSb on a GaAs substrate that is suitable for large-scale integration into an FPA. Pixel addressing is provided by the cointegration of a GaAs MESFET with an InSb photodiode (PD). Pixel fabrication was achieved by developing novel materials and process steps, including isolation etches, a gate recess etch, and low temperature processes, to make Ohmic contacts to both the GaAs and InSb devices. Detailed electrical and optical measurements in an FTIR demonstrated that the PD was sensitive to radiation in the range of 3– $5~\mu \text{m}$ at room temperature, and that the device could be isolated from its contacts using the integrated MESFET. This heterogeneous technology creates great potential to realize a new type of monolithic FPA of addressable pixels for imaging in the MWIR range.

Trap states induced by reactive ion etching in AlGaN/GaN high-electron-mobility transistors**Project supported by the National Natural Science Foundation of China (Grant Nos. 61334002 and 61106106).

Frequency-dependent conductance measurements were carried out to investigate the trap states induced by reactive ion etching in AlGaN/GaN high-electron-mobility transistors (HEMTs) quantitatively. For the non-recessed HEMT, the trap state density decreases from 2.48 × 1013 cm−2·eV−1 at an energy of 0.29 eV to 2.79 × 1012 cm−2·eV−1 at ET = 0.33 eV. In contrast, the trap state density of 2.38 × 1013–1.10 × 1014 cm−2·eV−1 is located at ET in a range of 0.30–0.33 eV for the recessed HEMT. Thus, lots of trap states with shallow energy levels are induced by the gate recess etching. The induced shallow trap states can be changed into deep trap states by 350 °C annealing process. As a result, there are two different types of trap sates, fast and slow, in the annealed HEMT. The parameters of the annealed HEMT are ET = 0.29–0.31 eV and DT = 8.16 × 1012–5.58 × 1013 cm−2·eV−1 for the fast trap states, and ET = 0.37–0.45 eV and DT = 1.84 × 1013 − 8.50 × 1013 cm−2·eV−1 for the slow trap states. The gate leakage currents are changed by the etching and following annealing process, and this change can be explained by the analysis of the trap states.

Low resistive Au-free, Ta-based, recessed ohmic contacts to InAlN/AlN/GaN heterostructures

The formation of recess etched Au-free ohmic contacts to an InAlN/AlN/GaN heterostructure is investigated. A Ta/Al/Ta metal stack is used to produce contacts with contact resistance (Rc) as low as 0.14 Ω mm. It is found that Rc decreases with increasing recess depth until the InAlN barrier is completely removed. For even deeper recesses Rc remains low but requires annealing at higher temperatures for contact formation. The lowest Rc is found for contacts where the recess etch has stopped just above the 2D electron gas channel. At this depth the contacts are also found to be less sensitive to other process parameters, such as anneal duration and temperature. An optimum bottom Ta layer thickness of 5–10 nm is found. Two reliability experiments preliminary confirm the stability of the recessed contacts.

(Invited) Reliability and Pulsed I-V Analysis of Vertically-Scaled GaN MIS-Hemts

GaN solid-state power amplifiers are becoming more frequently utilized in RF applications due to their significant power density advantages over conventional III-V semiconductor materials. Development of the core transistor technology, GaN high-electron-mobility transistors (HEMTs), has been the research focus of numerous groups around the globe. One of the most recent thrusts in the community has been to extend the frequency performance of GaN HEMTs to the millimeter wavelength (MMW) range of 30 – 300 GHz. To obtain power gain at these frequencies, device and heterostructure dimensions must be scaled down to minimize electron transit delay. However, this scaling raises the peak electric fields in the device to extremely high levels and often limits the operational voltage range due to excessive leakage current related breakdown. Historical solutions for managing peak electric fields, such as the use of source-connected field plates in microwave HEMTs, are generally avoided due to the excessive parasitic capacitance introduced. Without field-plate management of peak fields, a critical question that remains to be answered is how to achieve reliable high power operation in a MMW GaN device. In our laboratory we have been exploring methods to simultaneously achieve high power gain at MMW frequencies along with high breakdown voltage [1, 2]. This talk will discuss an initial study that has investigated the effect of SiN gate insulator thickness on MMW GaN HEMT reliability. As illustrated in Fig. 1, the heterostructure used in this work consists of an ultra-thin 2.3 nm In0.17Al0.83N / 1 nm AlN barrier, GaN channel and buffer layers grown on SiC by metalorganic chemical vapor deposition. After heterostructure growth, molecular beam epitaxy was used to deposit 1, 3, 5, or 6 nm of SiN gate insulator at 575 °C. Metal-insulator-semiconductor (MIS) HEMTs with 120 nm gate length were then fabricated using standard processing procedures described previously [2]. For the 5 nm SiN sample, an SF6 plasma recess etch was performed prior to gate metallization, creating a Schottky gate variant as a reference device. After initial dc, pulsed, and RF electrical testing, devices from each sample were biased in class AB at VDS = 20 V on a Maury on-wafer load-pull system that had been tuned to achieve maximum output power. To perform RF operation life testing (RFOL), large signal input power at 40 GHz was set to achieve peak power-added-efficiency while output power (Pout) and drain current were monitored as a function of time. Fig. 2 shows the change in Pout over time for pairs of samples with different gate insulator thickness. Interestingly, samples with thicker SiN showed less degradation in Pout relative to initial values. The dc characteristics of the 6 nm SiN sample before and after stress are shown in Fig. 3. This talk will discuss the measured results and implications for future MMW GaN HEMT design. Acknowledgements: The authors thank N. Green for his assistance with device fabrication. This work was supported by the Office of Naval Research (P. Maki).

Normally-off AlGaN/GaN high-electron-mobility transistor using digital etching technique

A normally-off AlGaN/GaN high-electron-mobility transistor (HEMT) with a recessed-gate structure fabricated by novel digital etching is reported. Digital etching consists of multiple cycles of oxidation and wet etching of the oxide, and has the merits of easy control of the recess depth and reduction of surface damage in comparison with conventional dry etching. However, in conventional digital etching, the oxidation process involves the possibility of undercutting. In the digital etching, a reactive ion etcher was used and recess etching without any undercut was confirmed. Normally-off operation and the improvement of transconductance were confirmed in an AlGaN/GaN HEMT fabricated by this technique.

Record-low contact resistance for InAlN/AlN/GaN high electron mobility transistors on Si with non-gold metal

We have demonstrated 0.17-µm gate-length In0.17Al0.83N/GaN high-electron-mobility transistors (HEMTs) on Si(111) substrates using a non-gold metal stack (Ta/Si/Ti/Al/Ni/Ta) with a record-low ohmic contact resistance (Rc) of 0.36 Ω mm. This contact resistance is comparable to the conventional gold-based (Ti/Al/Ni/Au) ohmic contact resistance (Rc = 0.33 Ω mm). A non-gold ohmic contact exhibited a smooth surface morphology with a root mean square surface roughness of ∼2.1 nm (scan area of 5 × 5 µm2). The HEMTs exhibited a maximum drain current density of 1110 mA/mm, a maximum extrinsic transconductance of 353 mS/mm, a unity current gain cutoff frequency of 48 GHz, and a maximum oscillation frequency of 66 GHz. These devices exhibited a very small (<8%) drain current collapse for the quiescent biases (Vgs0 = −5 V, Vds0 = 10 V) with a pulse width/period of 200 ns/1 ms. These results demonstrate the feasibility of using a non-gold metal stack as a low Rc ohmic contact for the realization of high-frequency operating InAlN/AlN/GaN HEMTs on Si substrates without using recess etching and regrowth processes.

1/&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$f$ &lt;/tex-math&gt;&lt;/inline-formula&gt; Noise Characteristics of Surface-Treated Normally-Off Al&lt;sub&gt;2&lt;/sub&gt;O&lt;sub&gt;3&lt;/sub&gt;/GaN MOSFETs

Normally off Al 2 O 3 /GaN MOSFETs are fabricated with a tetramethylammonium hydroxide (TMAH) treatment as a postgate recess etch. The effects of the surface treatment on the etched GaN surface are investigated using low-frequency (1/f ) noise and capacitance-voltage (C-V) measurements. For a quantitative comparison with conventional devices, the oxide trap density (N ot ) is extracted using the unified 1/f noise model, whereas the interface trap density (D it ) is extracted using the high-low-frequency C-V method. After the TMAH treatment, N ot is found to have decreased from 5.40 × 10 19 to 2.50 × 10 19 eV -1 cm -3 , whereas D it is decreased from 2.8 × 10 12 to 1.1 × 10 11 eV -1 cm -2 , as compared with conventional devices. The surface treatment is thus shown to lower trap density in the Al 2 O 3 /GaN MOSFETs by smoothing the surface and suppressing plasma damage in the recessed GaN surfaces.

Boron trichloride plasma treatment effect on ohmic contact resistance formed on GaN-based epitaxial structure

A BCl3 plasma treatment effect on GaN surface and reduction of ohmic contact resistance in GaN/AlGaN epitaxial structure with a GaN cap layer has been studied. The BCl3 plasma treatment was carried out by an inductively coupled plasma reactive ion etching (ICP RIE) system under conditions of low discharge power with zero external bias controlling power to prevent any recess etching of the GaN cap layer. The measured average contact resistances with and without plasma treatment were 1.8×10−5 and 1.05×10−5 Ω·cm2 respectively. To study the BCl3 plasma treatment effect on GaN surface and explain the increasing of contact resistance, the elemental composition of GaN surface was measured using x-ray photoelectron spectroscopy. It was found that a Bx-Cly layer covered the GaN surface after the BCl3 plasma treatment. This can indicate that ion bombardment from plasma is inefficient to prevent deposition of BClx radicals on the GaN cap layer surface and subsequent formation of the Bx-Cly layer which is responsible for increase of ohmic contact resistance after the BCl3 plasma treatment.