Reasonable Speedup Research Articles

An Optimized and Efficiently Parallelized Dynamic Programming for RNA Secondary Structure Prediction

RNA secondary structure prediction based on free energy rules remains a major computational method in computational biology. Its basic dynamic programming algorithm needs O(n) time to calculate the minimum free energy for RNA secondary structure, where n is the length of RNA sequence. There are two variants for handling this problem: either the internal loops are bounded by a maximal size k, giving a time complexity of O(n×k), or one uses the trick of Lyngso, which makes use of the rules of loop energies, to reduce time complexity to O(n) for suboptimal free energy without restriction. Only with additional O(n) space, a new algorithm is proposed to eliminate the redundant calculation in the energy of internal loops and reduce the time complexity to O(n) with unrestricted loop sizes for optimal free energy. While the optimized algorithm is time consuming, an efficient parallel algorithm with good load balancing in cluster systems is also proposed. The experimental results show that the parallel program achieves reasonable speedups.

A fast, parallel spanning tree algorithm for symmetric multiprocessors (SMPs)

The ability to provide uniform shared-memory access to a significant number of processors in a single SMP node brings us much closer to the ideal PRAM parallel computer. Many PRAM algorithms can be adapted to SMPs with few modifications. Yet there are few studies that deal with the implementation and performance issues of running PRAM-style algorithms on SMPs. Our study in this paper focuses on implementing parallel spanning tree algorithms on SMPs. Spanning tree is an important problem in the sense that it is the building block for many other parallel graph algorithms and also because it is representative of a large class of irregular combinatorial problems that have simple and efficient sequential implementations and fast PRAM algorithms, but these irregular problems often have no known efficient parallel implementations. Experimental studies have been conducted on related problems (minimum spanning tree and connected components) using parallel computers, but only achieved reasonable speedup on regular graph topologies that can be implicitly partitioned with good locality features or on very dense graphs with limited numbers of vertices. In this paper we present a new randomized algorithm and implementation with superior performance that for the first time achieves parallel speedup on arbitrary graphs (both regular and irregular topologies) when compared with the best sequential implementation for finding a spanning tree. This new algorithm uses several techniques to give an expected running time that scales linearly with the number p of processors for suitably large inputs ( n > p 2 ). As the spanning tree problem is notoriously hard for any parallel implementation to achieve reasonable speedup, our study may shed new light on implementing PRAM algorithms for shared-memory parallel computers. The main results of this paper are 1. A new and practical spanning tree algorithm for symmetric multiprocessors that exhibits parallel speedups on graphs with regular and irregular topologies; and 2. an experimental study of parallel spanning tree algorithms that reveals the superior performance of our new approach compared with the previous algorithms. The source code for these algorithms is freely-available from our web site.

Fast fragments: the development of a parallel effective fragment potential method.

The Effective Fragment Potential (EFP) method for solvation decreases the cost of a fully quantum mechanical calculation by dividing a chemical system into an ab initio region that contains the solute plus some number of solvent molecules, if desired, and an "effective fragment" region that contains the remaining solvent molecules. Interactions introduced with this fragment region (for example, Coulomb and polarization interactions) are added as one-electron terms to the total system Hamiltonian. As larger systems and dynamics are just starting to be studied with the EFP method, more needs to be done to decrease the calculation time of the method. This article considers parallelization of both the EFP fragment-fragment and mixed quantum mechanics (QM)-EFP interaction energy and gradient computation within the GAMESS suite of programs. The iteratively self-consistent polarization term is treated with a new algorithm that makes use of nonblocking communication to obtain better scalability. Results show that reasonable speedup is achieved with a variety of sizes of water clusters and number of processors.

A Divide-and-Conquer Parallel Computing Scheme for the Optimization Analysis of Tribological Systems

The trend of using commercial products and open source packages to construct a scalable computer cluster for distributed computing to minimize the execution time of numerical optimization has long been expected. However, in the tribology field progress has been slow due to the complexity of parallel coding and the lack of easy-to-implement parallel algorithms. This study presents an optimization analysis of constrained problems by using a divide-and-conquer scheme suitable for parallel computation. A porous air bearing model of moderate computational load is used to illustrate the optimization procedure. In the optimization process, the design space is subdivided and each of the subdivisions is dealt with by Taguchi's Design of Experiments to achieve the local optimum. The global optimum is then determined when all the local optima are obtained. Two task-assignment strategies in the cluster computing are implemented and discussed. Reasonable speedup and parallel efficiency were obtained for the highly uneven task-load calculations. The approach does not require the knowledge of parallel programming techniques associated with message passing libraries. The presented scheme has high portability, low cost of evaluation process, and algorithm-machine scalability, which should be an easy-to-implement and efficient tool for many tribological studies.

Generating Cutting Planes for Mixed Integer Programming Problems in a Parallel Computing Environment

A parallel implementation of a disjunctive cutting-plane algorithm in a distributed memory environment is described. Guided by a selection of difficult instances from MIPLIB and real instances obtained from brain-tumor research, various strategies of cut synchronization are considered, and their influence on speedup, communication overhead, load balance, and effectiveness in closing the integrality gap are studied. The parallel cutting-plane algorithm is coupled with an LP-based heuristic to assist in returning a good quality integer feasible solution upon termination of the parallel process. The parallel implementation is sufficiently coarse-grained to yield an average of less than 6% of the total time performing tasks associated with communication overhead, and it provides reasonable speedup when executing in parallel. Noticeable differences in load-balance scores are observed, depending on the number of processors used, the synchronization scheme used, and the structure of the MIP problem instance. Nevertheless, the synergism of the combined collection of cuts generated locally on each processor is effective in closing the integrality gap in all cases, and there is minimal variability in the amount of the gap closed as the number of processors varies. In particular, the degree of decentralization, as governed by the synchronization schemes, has little effect on the overall quality of the cuts generated.

STAR-CUBE: A Special Purpose Interconnection Network for Signal Processing

Both Hypercube and star graph networks possess desirable properties like regularity, vertex and edge symmetric, maximally fault-tolerant etc, though, some of the attractive features of one are not found in the other. In this paper, we propose and study a composite architecture, which is a combination of these two architectures and call it Star-Cube. The most important characteristic of the proposed star-cube network is that, it can be incremented in smaller steps. This is an advantage for FFT implementation as an architecture with reasonable number of nodes can be made out of this star-cube graph that will give more processor utilization than either star-graph or Hypercube architecture individually. It provides some of the desirable properties of both the networks such as reduced diameter and degree. The degree and diameter of the proposed network falls in-between its individual constituents that make it suitable for Fast Fourier Transform (FFT) type of processing. The proposed Star-Cube network has simple routing algorithms amenable to networks with faults. Other parameters such as average distance, number of links, fault-tolerance, etc, are computed. To show its performance, a Fast Fourier Transform algorithm is considered for implementation in this hybrid network where a hierarchical ranking scheme is adopted for assigning node addresses. We estimate the speedup and efficiency for the Star-cube graph. It is observed that our proposed star-cube interconnection network gives reasonable speedup as compared to hypercube and star graph as FFT processor.

Blue Matter, an application framework for molecular simulation on Blue Gene

In this paper we describe the context, architecture, and challenges of Blue Matter, the application framework being developed in conjunction with the science effort within IBM's Blue Gene project. The study of the mechanisms behind protein folding and related topics can require long time simulations on systems with a wide range of sizes and the application supporting these studies must map efficiently onto a large range of parallel partition sizes to optimize scientific throughput for a particular study. The design goals for the Blue Matter architecture include separating the complexities of the parallel implementation on a particular machine from those of the scientific simulation as well as minimizing system environmental dependencies so that running an application within a low overhead kernel with minimal services is possible. We describe some of the parallel decompositions currently being explored that target the first member of the Blue Gene family, BG/L, and present simple performance models for these decompositions that we are using to prioritize our development work. Preliminary results indicate that the high-performance networks on BG/L will allow us to use FFT-based techniques for periodic electrostatics with reasonable speedups on 512–1024 node count partitions even for systems with as few as 5000 atoms.

A parallel CFD rotor code using OpenMP

The extended full-potential (FPX) helicopter rotor computational fluid dynamics (CFD) code of Fortran in its reduced two-dimensional version is successfully converted into a parallel version for multiprocessing. The FPX code with an internal grid generator solves the compressible full-potential equation using an approximately factored finite-difference scheme with added numerous physical modeling enhancements, including viscous boundary layers, shock-induced entropy corrections and wake-vortex embedding. The parallel version of the code uses open multi-processing (OpenMP) directives as parallel programming tool in shared-memory (SM) environment. The OpenMP code is portable and scalable, which can run on various computer platforms including UNIX platforms and Windows NT platforms. The performance study of the parallel code on SGI Origin 2000 UNIX platform is made. The results show that reasonable speedups through parallelization are obtained and that OpenMP is easy to use and an efficient parallel programming tool for the present problem.

A parallel linear system solver for circuit simulation problems

This paper presents a parallel mixed direct/iterative method for solving linear systems Ax = b arising from circuit simulation. The systems are solved by a block LU factorization with an iterative method for the Schur complement. The Schur complement is a small and rather dense matrix. Direct LU decomposition of the Schur complement takes too much time in order to achieve reasonable speedup results. Our iterative method for the Schur complement is often much faster than the direct LU approach. Moreover, the iterative method is better parallelizable. This results in a fast sequential and well parallelizable method. Copyright © 2000 John Wiley & Sons, Ltd.

Concurrency Preserving Partitioning Algorithm forParallel Logic Simulation

A partitioning algorithm for parallel discrete event gate‐level logic simulations is proposed in this paper. Unlike most other partitioning algorithms, the proposed algorithm preserves computation concurrency by assigning to processors circuit gates that can be evaluated at about the same time. As a result, the improved concurrency preserving partitioning (iCPP) algorithm can provide better load balancing throughout the period of a parallel simulation. This is especially important when the algorithm is used together with a Time Warp simulation where a high degree of concurrency can lead to fewer rollbacks and better performance. The algorithm consists of three phases and three conflicting goals can be separately considered so to reduce computational complexity.To evaluate the quality of partitioning algorithms in terms of preserving concurrency, a concurrency metric that requires neither sequential nor parallel simulation is proposed. A levelization technique is used in computing the metric so to determine gates which can be evaluated at about the same time. A parallel gate‐level logic simulator is implemented on an INTEL Paragon and an IBM SP2 to evaluate the performance of the iCPP algorithm. The results are compared with several other partitioning algorithms to show that the iCPP algorithm does preserve concurrency pretty well and reasonable speedup may be achieved with the algorithm.

Prototyping of Tightly Coupled Hardware/Software-Systems

Verification and test issues raise the need for rapid prototyping of complex systems and especially hardware/software-systems. We tackle this problem by integration of hardware/software-codesign and prototyping. First we define the concept of the entire system architecture. This concept directs the hardware/software-partitioning process. Our prototyping environment reflects the architecture concept as well. In this overview the architecture concept and all important design tasks (hardware/software-partitioning, speed-up estimation before HW-synthesis, and prototyping of the entire hardware/software-system) are presented and compared to several approaches from literature. Thus a substantial overview over the prototyping problem is given. The latter part of this presentation illustrates our approach by a case study and presents the results. Our automated design process generates a tightly coupled hardware/software-system with very good performance characteristics. The case study focus on the prototyping of a ciphering algorithm. The reported approach leads to a reasonable overall system speed-up of 10 percent. Similar results have been found for further examples as well.

A Coarse-Grained Parallel Variable-Complexity Multidisciplinary Optimization Paradigm

Modem aerospace vehicle design requires the interac tion of multiple disciplines, traditionally processed in a sequential order. Multidisciplinary optimization (MDO), a formal methodology for the integration of these disci plines, is evolving toward methods capable of replacing the traditional sequential methodology of aerospace vehi cle design by concurrent algorithms, with both an overall gain in product performance and a decrease in design time. A parallel MDO paradigm using variable-complexity modeling and multipoint response surface approxima tions is presented here for the particular instance of the design of a high-speed civil transport (HSCT). This para digm interleaves the disciplines at one level of complexity and processes them hierarchically at another level of complexity, achieving parallelism within disciplines rather than across disciplines. A master-slave paradigm manages a coarse-grained parallelism of the analysis and optimization codes required by the disciplines showing reasonable speedups and efficiencies on an Intel Paragon.

Parallelizing the QR Algorithm for the Unsymmetric Algebraic Eigenvalue Problem: Myths and Reality

Over the last few years, it has been suggested that the popular QR algorithm for the unsymmetric Schur decomposition does not parallelize. In this paper, we present both positive and negative results on this subject. In theory, asymptotically perfect speedup can be obtained. In practice, reasonable speedup can be obtained on an MIMD distributed memory computer for a relatively small number of processors. However, we also show theoretically that it is impossible for the standard QR algorithm to be scalable. Performance of a parallel implementation of the LAPACK DLAHQR routine on the Intel ${\text{Paragon}}^{{\text{TM}}} $ system is reported.

Concurrency preserving partitioning (CPP) for parallel logic simulation

Based on a linear ordering of vertices in a directed graph, a linear-time partitioning algorithm for parallel logic simulation is presented. Unlike most other partitioning algorithms, the proposed algorithm preserves circuit concurrency by assigning to processors circuit gates that can be evaluated at about the same time. As a result, the concurrency preserving partitioning (CPP) algorithm can provide better load balancing throughout the period of a parallel simulation. This is especially important when the algorithm is used together with a Time Warp simulation where a high degree of concurrency can lead to fewer rollbacks and better performance. The algorithm consists of three phases, and three conflicting goals can be separately considered in each phase so to reduce computational complexity. A parallel gate-level circuit simulator is implemented on an Intel Paragon machine to evaluate the performance of the CPP algorithm. The results are compared with two other partitioning algorithms to show that reasonable speedup may be achieved with the algorithm.

Performance modelling of three parallel sorting algorithms on a pipelined transputer network

The implementation of three parallel sorting algorithms, namely binary sort, odd-even transposition sort and bitonic sort, on a network of transputers is analysed in the paper. The variation in the performance of these algorithms as the number of processors and sort size are changed is investigated. Experimental results show that when up to eight transputers are used, connected as a linear pipeline configuration, all three algorithms can achieve reasonable speedup ratios. The bitonic sort, binary sort odd-even transposition sort achieve speedup ratios of 5, 4.4 and 4, respectively, when eight processors are used to sort 100,000 integers. Analytical models are derived which can be used to predict the performance of the three algorithms when a linear pipeline configuration is used. The predicted performance of the algorithms is compared with the experimental performance in order to validate the model. When the models are used to predict the performance using 16 transputers, it is found that the speedup does not significantly improve compared to the performance achieved with eight transputers. This shows that interprocessor communication has a significant effect on the algorithmic performance when a larger number of processors are used. The conclusions reinforce the fact that the binary and bitonic sorting algorithms are not well-suited to a linear pipeline configuration and that they may perform better if a different topology were used, for example a mesh or a cube connection scheme. Further, the analytical technique used for performance modelling as elaborated in the paper can be employed profitably for other multiprocessor systems as well.

Parallel Implementation of a Sparse Simplex Algorithm on MIMD Distributed Memory Computers

Parallelizing sparse Simplex algorithms is one of the most challenging problems in computational science. We implemented the revised Simplex algorithm with LU decomposition on the Touchstone Delta and the iPSC/2. Because of very sparse matrices and very heavy communication, the ratio of computation to communication is extremely low. It becomes necessary to carefully select parallel algorithms, partitioning patterns, and communication optimization to achieve a reasonable speedup. Satisfactory performance has been obtained for a class of LP problems with high n/ m ratios.

A parallel image-rendering algorithm and architecture based on ray tracing and radiosity shading

In this paper, we explore ways to improving the performance of a ray-casting based approach for visualizing artificial scenes with photo realism on the screen of a workstation. We aim at developing a parallel image-rendering algorithm and architecture based on the so-called two-pass approach [1–4]. This approach is normally demanding orders-of-magnitude more processing power for a single processor if we wish to make a state-of-art image in real-time or even interactive time. Several attempts have been made to boost processing power by using parallel architectures, but they still suffer from high overheads due to latency and synchronization. In this paper, we argue that large speedups and low overheads can only be attained through combined algorithm and architecture design. By attempting this combined effort, we come up with a good algorithm-architecture pair, namely, the shelling technique[5–7] and a pipelined parallel architecture[8], in which a parameterized space partitioning on the one hand finds its counterpart in a scalable network of clusters on the other hand. The target system which is made of a host computer and a scalable network of clusters has been completely modelled by using a mixed-level simulator called the Block Oriented Network Simulator (BONeS ®), and we have evaluated its performance for a set of practical scenes. Promising results have been observed, including the following: 1. 1. The performance of the shelling technique is a weak function of the scene complexity. The computational complexity of the shelling technique is k × R ( k is about 2–5) as compared to N × R ( N is the total number of patches) of the naive algorithm, where R is the total number of intersection-computation rays. 2. 2. A reasonable speedup has been observed up to 8 clusters. The limiting factors in speedup are workload imbalancing, the long latencies for global memory requests and the limited bandwidth provided by the system and local buses. To achieve a higher scalability of the system, further improvement in the front-end system together with the use of a dynamic workload balancing scheme would be necessary. 3. 3. The performance of software intersection computation on HP720 is about 0.2 M/sec. The radiosity engine provides two-orders-of-magnitude more processing power than this software approach per cluster.

Status and issues of HPF compilers

AbstractHigh Performance Fortran (HPF) is an emerging, de facto standard language for machine‐independent, data‐parallel programs that run on various parallel machines. The ease with which parallel programs can be created by means of simple data placement annotations to Fortran 90 programs is particularly attractive to end‐users. The success of the HPF approach, however, depends on the innovation in compiler technology. In order to achieve a reasonable speedup on the target parallel machine, the HPF compiler must be able to parallelize loops, optimize communications, localize arrays, and generate efficient, scalable single‐program multiple‐data (SPMD) code. We have implemented HPF on the basis of the IBM XL Fortran 90 compiler. This task will present an overview of our compilation strategy and preliminary results obtained on an IBM Scalable POWERparallel System.

An efficient parallel critical path algorithm

The problem of identifying one of the longest sensitizable paths in a circuit is called a critical path problem. Several critical path algorithms have been proposed in the last few years. However, due to the long computation time required to produce accurate results, these algorithms may not be able to generate any result for large designs with many long false paths unless the accuracy of the results is compromised. Parallel processing seems to be an appropriate way to speed up the required computation. In this paper, we study the parallel algorithms for critical path problem. We first present a sensitization criterion. Based on this sensitization criterion an algorithm called DT-algorithm, which is a variation of the D-algorithm with stable time range of signals also taken into consideration, is developed. The DT-algorithm is especially suitable and can be used to determine the sensitizability of a given path in a parallel processing environment. We also present an implementation of parallel DT-algorithm that can be executed on a shared memory multiprocessor. The experimental results show that a reasonable speed-up can be obtained.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Performance benefits and limitations of large NUMA multiprocessors

In scalable multiprocessor architectures, the times required for a processor to access various portions of memory are different. In this paper, we consider how this characteristic affects performance by comparing it to the ideal but unrealizable case in which the access times to all memory modules can be kept constant, even as the number of processors is increased. We examine several application kernels to investigate how well they would execute on various instances of NUMA systems with a hierarchical memory structure. The results of our analytic model show that access locality is much more important in NUMA architectures than it is in UMA architectures. The extent of the performance penalty of non-local memory accesses depends on the variability in access times to various parts of shared memory, as well as on the amount of congestion in the interconnection network that provides access to remote memory modules. In the applications we examined, we found that it is possible to partition and locate both the data and the computation in such a way that reasonable speedups can be achieved on NUMA systems.