Real-time Signal Processing Applications Research Articles

Performance Analysis of Vedic Multiplier in Hardware Implementation of Biomedical Applications

As technology advances at a rapid pace, there is an increasing need for real-time digital signal processing (DSP) applications that are efficient and swift. DSPs, or digital signal processors, are crucial components of several engineering disciplines. For processes like convolution and Fourier transforms in DSPs, rapid multiplication is essential. Multiplication is one of the basic mathematical operations used by all applications. Many different multiplier designs have been developed to boost their speed. When compared to array and booth multipliers—the products of decades of hard research—vedic multipliers are among the fastest and lowest power multipliers. The sixteen sutras, or algorithms, that the Vedic Multiplier uses are primarily logical procedures. They are the fastest and most effective because several of them have been proposed using the Urdhava Tiryakbhyam sutra. The purpose of this study is to provide an overview of the numerous biomedical applications of Vedic Multiplier in the wide field of digital signal processing, including denoising of Electrocardiogram (ECG) and Electroencephalogram ( EEG) signal. Particular attention is paid to how current Vedic Multiplier designs have been altered to increase speed and performance metrics.

Performance Analysis of Vedic Multiplier in Signal Processing Applications

The demand for quick and effective real-time digital signal processing (DSP) applications has increased due to the rapidly advancing technology. Digital signal processors, or DSPs, are essential to several engi- neering specialties. In DSPs, quick multiplication is crucial for operations like Fourier transformations and convolution. One of the fundamental arithmetic processes required by all applications is multiplication. To increase their speed, numerous multiplier designs have been created. Vedic multipliers are among the quick- est and lowest power multipliers compared to array and booth multipliers which are the result of decades of intensive research. The Vedic Multiplier works with sixteen sutras, or algorithms, most of which are for logical processes. Since several of them have been proposed utilizing the Urdhava Tiryakbhyam sutra, they are the fastest and most efficient. This paper's goal is to summarise the many uses of Vedic Multiplier in the broad field of digital signal processing such as image processing, with a focus on the various ways that Vedic Multiplier designs that are now in use have been modified to improve speed and performance metrics.

General Tensor Least-Mean-Squares Filter for Multi-Channel Multi-Relational Signals

Least-mean-squares (LMS) algorithms constitute a prevalent approach to implement the linear adaptive filters whose coefficients can be updated sample by sample so as to track time-varying dynamics. As the memory and computational complexities required for the realization of LMS filters are very low, they have been widely adopted in many real-time signal processing applications. The input of any conventional LMS filter has to be a sequence of scalar samples (one-dimensional time series), whereas such assumption is too restrictive nowadays for multi-channel (high-dimensional) signals and multi-relational data in the rise of a big-data era. It is crucial to deal with high-dimensional data-arrays, a.k.a. tensors, to manifest the variety and complex interrelations of data. Owing to lack of a sufficient mathematical framework to govern relevant tensor operations, the general tensor LMS filter, whose input is allowed to be an arbitrary tensor, has never been established for realization to the best of our knowledge. In this work, we will dedicate a new mathematical framework for tensors to establish the general tensor least-mean-squares (TLMS) filter theory and propose two novel TLMS algorithms with update rules based on stochastic gradient-descent and Newton's methods, respectively. Furthermore, as we establish the tensor calculus theory, the performance evaluation on convergence-rate and misadjustment for our proposed TLMS filters can be conducted. Finally, the memory and computational complexities of the new TLMS algorithms are also studied in this paper.

Analog signal processing through space-time digital metasurfaces

Abstract In the quest to realize analog signal processing using subwavelength metasurfaces, in this paper, we present the first demonstration of programmable time-modulated metasurface processors based on the key properties of spatial Fourier transformation. Exploiting space-time coding strategy enables local, independent, and real-time engineering of not only amplitude but also phase profile of the contributing reflective digital meta-atoms at both central and harmonic frequencies. Several illustrative examples are demonstrated to show that the proposed multifunctional calculus metasurface is capable of implementing a large class of useful mathematical operators, including 1st- and 2nd-order spatial differentiation, 1st-order spatial integration, and integro-differential equation solving accompanied by frequency conversions. Unlike the recent proposals based on the Green’s function (GF) method, the designed time-modulated signal processor effectively operates for input signals containing wide spatial frequency bandwidths with an acceptable gain level. Proof-of-principle simulations are also reported to demonstrate the successful realization of image processing functions like edge detection. This time-varying wave-based computing system can set the direction for future developments of programmable metasurfaces with highly promising applications in ultrafast equation solving, real-time and continuous signal processing, and imaging.

Efficient recursive least squares solver for rank-deficient matrices

Updating a linear least-squares solution can be critical for near real-time signal-processing applications. The Greville algorithm proposes a simple formula for updating the pseudoinverse of a matrix A∈Rn×m with rank r. In this paper, we explicitly derive a similar formula by maintaining a general rank factorization, which we call rank-Greville. Based on this formula, we implemented a recursive least-squares algorithm exploiting the rank-deficiency of A, achieving the update of the minimum-norm least-squares solution in O(mr) operations and, therefore, solving the linear least-squares problem from scratch in O(nmr) operations. We empirically confirmed that this algorithm displays a better asymptotic time complexity than LAPACK solvers for rank-deficient matrices. The numerical stability of rank-Greville was found to be comparable to Cholesky-based solvers. Nonetheless, our implementation supports exact numerical representations of rationals, due to its remarkable algebraic simplicity.

A Comparative Survey of Convex Combination of Adaptive Filters

Over the last twenty years, combination of adaptive filters has emerged to provide a potential solution in the development of advanced applications, such as channel equalization, active noise control, acoustic echo cancelation, adaptive beamforming, among others. Several authors have demonstrated that the combination of two filters with complementary capabilities improves the overall filter performance in comparison when a single filter is used. Commonly, these combinations employ a fast filter and slow filter to guarantee fast convergence speed and low steady-state mean square error (MSE), respectively, at the cost of increasing their computational complexity. However, those combinations have not been well analysed and compared. Currently, this aspect is crucial since most of the current convex combination of adaptive filters could be implemented in advanced embedded digital devices to be used in real-time signal processing applications. In this work, we evaluate the convex combination of adaptive filters, mainly including those based on least mean square (LMS) algorithm, the affine projection (AP) algorithm and the recursive least mean square (RLS) algorithm. We carry out an extensive performance evaluation to demonstrate the advantages and disadvantages of each approach. Specifically, we simulate them in fixed point, which makes feasible the rapid development of advanced prototypes. This aspect could be potentially valuable to the signal processing engineering communities.

New Efficient Algorithm for the Discrete Hartley Transform

In real-time signal processing applications, the discrete version of the transform introduced by Hartley (DHT) has been proved to be an efficient substitute to the discrete Fourier transform (DFT). A new algorithm for fast calculations of the DHT (FHT) based on radix -2/4/8 method is introduced in this paper. In comparison with the split radix FHT algorithm, the proposed algorithm has a comparable arithmetic complexity, but preserves the regularity and the simple butterfly structure of the radix-2 algorithm. The development of the algorithm is motivated by firstly deriving a new radix-2/8 FHT algorithm and then cascading it with the radix-4 and radix-2 FHT algorithms. The arithmetic complexity of the developed algorithm has been implemented and analyzed by calculating the number of real additions and multiplications for different transform lengths. Comparisons with the existing FHT algorithms have shown that this algorithm can be considered as a good compromise between structural and arithmetic complexity.

Implementation of Parallel and Pipeline Scheme in the Standard Floating Point Adder to Improve the Speed

In real time Signal Processing applications, the analogue signal is over sampled as per the Nyquist criterion in order to avoid the aliasing effect. Floating Point (FP) adder is used in the floating point Multiplier Accumulator Content (MAC) for real time Digital Signal Processing(DSP) applications. The heart of any real time DSP processor is floating point MAC. Floating Point MAC is constructed by Finite Impulse Response (FIR) or Infinite Impulse Response (IIR) filters. FIR filters are stable than IIR filters because the impulse response is finite in FIR. Hence, for stable applications FIR filters are preferred. These FIR filters are intern constituted by FP adder, FP multiplier and shifter. In conventional floating point adder the two floating point numbers are added in series. Series means one after the other so the computation speed is less. In series fashion adding the floating point numbers means definitely it furnishes more delay[1] because in the addition of floating point numbers, along with the addition of mantissas; computation is required for both signs and exponents also. Hence, the processing speed is slow for computing the floating point numbers compared with fixed point numbers. Therefore, in order to increase the speed of operation for floating point addition in real time application i.e., to add 16- samples at a time which are in floating notation; a parallel and pipe line technique is going to be incorporated to the two bit floating point architecture. Before developing such novel architecture, a novel algorithm is developed and after, the novel architecture is developed. The total work is simulated by Modelsim 10.3c tool and synthesized by Xilinx 13.6 tool.

Frequency response masking based FIR filter using approximate multiplier for bio-medical applications

The advancements in medical healthcare networks and bio-medical sensor technologies enabled the use of wearable and body implantable intelligent devices for healthcare monitoring. These battery-operated devices must be capable of very low power operation for ensuring long battery life and also to prevent intense radiations. The major power consuming part of these devices are the multipliers built into the digital filters for performing signal processing operations. This paper proposes a low power signed approximate multiplier architecture for bio-medical signal processing applications. The circuit characteristics and error metrics of the proposed multiplier are estimated to verify its performance advantage over other approximate multipliers. In order to validate the efficacy of the approximate multiplier in real time signal processing applications, a band pass finite impulse response filter (FIR) filter is designed using frequency response masking technique and used in the Pan Tompkins method for the extraction of QRS complex from raw ECG data. The sensitivity, positive predictivity, and detection error rate of the QRS detection method are estimated and the results show that the approximate filtering method implemented gives a comparable performance as that of exact methods.

Best-Choice Topology: An Optimized Array-based Maximum Finder

Extracting maximum from an unsorted set of binary elements is important in many signal processing applications. Since quite few maximum-finder implementations are found in the recent literature, in this paper we provide an update on the current topic. Generally, maximum-finders are considered array-based, with parallel bit-by-bit comparison of the elements, or more efficient tree-based structures, with the hierarchical maximum extraction. In this paper, we concentrate on array-based topologies only, since our goal is to propose a new maximum-finder design called Best-Choice Topology (BCT), which is an optimized version of the standard Array Topology (AT). The usual bit-by-bit parallel comparison is applied for extracting the maximum and its one-of-N address. Boolean expressions are derived for BCT logical design and the minimum-finder equivalent. Functionality of the proposed architecture and the reference designs is verified with Xilinx ISE Design Suite 14.5. Synthesis is done on Application Specific Integrated Circuit (ASIC) TSMC 65nm technology. The conclusion of the paper is two-fold. First, we confirm the timing efficiency of BCT compared to AT. Next, we show that BCT is more efficient than the recent maximum-finder design called Maximum Magnitude Generator (MaxMG) and it has a great potential to be used for real-time signal processing applications.

Implementation of High Speed Vedic Multiplier Using Vertical and Crosswise Algorithm

Multiplication is an important fundamental function in arithmetic operations. Multiplication-based operations such as Multiply and Accumulate (MAC) and inner product are some of the frequently used operations in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform(FFT), filtering and in microprocessors in its arithmetic and logic unit. Since multiplication dominates the execution time of most DSP algorithms, so there is a need of high speed multiplier. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications. In this project, the comparative study of Vedic multiplier and Sequential multiplier is done for low power requirement and high speed. The proposed architecture is based on the Vertical and Crosswise algorithm of ancient Indian Vedic Mathematics, which increases the speed of multiplier by reducing the number of clock cycles thus achieving the greater speed of the processor or system.

Stereo I/O framework for audio signal processing on android platforms

Smartphones and tablets are attractive cost-effective solutions for implementing multi-channel audio signal processing algorithms. Modern smartphones and tablets have at least two microphones and requisite processing capabilities to perform real-time audio signal processing. However, it is still challenging to integrate the dual-microphone audio capture and the audio processing pipeline in real-time for efficient operation. In this paper, we propose an efficient stereo input/output framework for real-time audio signal processing on Android smartphones/tablets. This framework enables us to perform a large variety of real-time signal-processing applications on Android platform such as Direction of Arrival (DOA) estimation, Audio Compression, and Multi-Channel Speech Enhancement. The implementations and demos of Direction of Arrival (DOA), Audio Compression, and Multi-Channel Speech Enhancement algorithms are also presented to show the effectiveness of proposed framework.

Proposal for nanoscale cascaded plasmonic majority gates for non-Boolean computation

Surface-plasmon-polariton waves propagating at the interface between a metal and a dielectric, hold the key to future high-bandwidth, dense on-chip integrated logic circuits overcoming the diffraction limitation of photonics. While recent advances in plasmonic logic have witnessed the demonstration of basic and universal logic gates, these CMOS oriented digital logic gates cannot fully utilize the expressive power of this novel technology. Here, we aim at unraveling the true potential of plasmonics by exploiting an enhanced native functionality - the majority voter. Contrary to the state-of-the-art plasmonic logic devices, we use the phase of the wave instead of the intensity as the state or computational variable. We propose and demonstrate, via numerical simulations, a comprehensive scheme for building a nanoscale cascadable plasmonic majority logic gate along with a novel referencing scheme that can directly translate the information encoded in the amplitude and phase of the wave into electric field intensity at the output. Our MIM-based 3-input majority gate displays a highly improved overall area of only 0.636 μm2 for a single-stage compared with previous works on plasmonic logic. The proposed device demonstrates non-Boolean computational capability and can find direct utility in highly parallel real-time signal processing applications like pattern recognition.

FPGA implementation of hardware efficient adaptive filter robust to impulsive noise

Adaptive filters are prevalent in many real-time signal processing applications. Many adaptive algorithms already exist, but most of them assume white Gaussian noise as disturbance. However, for many applications such as electrocardiogram, foetus heart rate measurement, low frequency atmospheric noise, underwater acoustic noise and signal measurement in instrumentation, the impulsive noise is more common. This study presents a modified robust mixed norm (MRMN) adaptive filter algorithm robust to impulsive noise with higher convergence rate and lower steady state error (SSE). MRMN adaptive filter algorithm has been simulated using Matlab and Xilinx system generator high level synthesis tool and a significant improvement in SSE and convergence speed is obtained compared with the existing adaptive filter algorithms for similar specifications. The proposed algorithm is also described using VHDL and synthesised using Xilinx synthesiser tool in order to implement on field-programmable gate array (FPGA). The FPGA post route and place implementation results show nearly 90% reduction in resource utilisation and nearly 2.6 times improvement in clock frequency as compared with the existing FPGA based implementation for similar specifications.

Unified and Modular Modeling and Functional Verification Framework of Real-Time Image Signal Processors

In VLSI industry, image signal processing algorithms are developed and evaluated using software models before implementation of RTL and firmware. After the finalization of the algorithm, software models are used as a golden reference model for the image signal processor (ISP) RTL and firmware development. In this paper, we are describing the unified and modular modeling framework of image signal processing algorithms used for different applications such as ISP algorithms development, reference for hardware (HW) implementation, reference for firmware (FW) implementation, and bit-true certification. The universal verification methodology- (UVM-) based functional verification framework of image signal processors using software reference models is described. Further, IP-XACT based tools for automatic generation of functional verification environment files and model map files are described. The proposed framework is developed both with host interface and with core using virtual register interface (VRI) approach. This modeling and functional verification framework is used in real-time image signal processing applications including cellphone, smart cameras, and image compression. The main motivation behind this work is to propose the best efficient, reusable, and automated framework for modeling and verification of image signal processor (ISP) designs. The proposed framework shows better results and significant improvement is observed in product verification time, verification cost, and quality of the designs.

FPGA-VHDL implementation of Pipelined Square root Circuit for VLSI Signal Processing Applications

An efficient mathematical operation plays an imperative role in achieving the preferred presentation in most of the real time Signal processing applications. In all types of mathematical operations, Square root is an important operation which can be used in VLSI signal processing applications. This paper presents a proficient policy to implement non restoring algorithm based on FPGA in gate level build of VHDL, which uses abundant pipelined architecture. An original basic building block called as controlledsubtract-multiplex (CSM) is introduced here. The pipelined square root circuit is designed using an ever known algorithm called non-restoring algorithm that does not require any floating-point hardware .The designed circuit is simulated and debugged using XILINX ISE 14.1. The architecture is implemented onto SPARTAN 3E family and debugged on Spartan 3 XC3S100E. The main principle of the proposed method is similar with conventional non-restoring algorithm, but it only uses subtract operation and append 01, while add operation and append 11 is not used. The proposed strategy has conducted to implement FPGA successfully. General Terms VLSI, Algorithms, Signal Processing

Bit-width-aware constant-delay run-time Accuracy Programmable Adder for error-resilient applications

Error-resilient applications such as image, audio and video processing adopt the concept of approximate computing to decorate delay, power and area metrics at the cost of accuracy. Approximate computing relaxes the exact equivalence between the design specifications and the design implementation to achieve Speed-Power-Accuracy-Area (SPAA) trade-off. In this paper, we propose a bit-width-aware constant-delay run-time Accuracy Programmable Adder (APA) in which the probability of input combinations exhibiting accurate results is programmable and adaptively controlled by the Number of Iterations (NoIs). Simulation results based on the PTM 32nm CMOS technology suggest that the proposed approach attains tremendous improvements in delay, power and area metrics with a trivial degradation in the output quality. The proposed APA shows 3.4 × improvement in performance and 41.5% reduction in area over the best known accuracy configurable adder. Even with 100% accuracy, a 32-bit APA improves delay, power and area by 33.92%, 23.04% and 17.44%, respectively, over Ripple Carry Adder (RCA). We also demonstrate an APA embedded error-resilient JPEG encoder architecture in order to inspect the efficacy of the proposed approach in real-time Digital Signal Processing (DSP) applications.

Configurable Folded IIR Filter Design

This brief proposes an efficient very-large-scale integration architecture for folded configurable infinite-impulse response (IIR) filter design, which is used in modern real-time digital signal processing applications such as loudspeaker equalization. The proposed configurable sixth-order IIR filter is designed with three cascaded second-order IIR filters, and the same is used to perform one sixth-order or three second-order or one fourth-order and one second-order IIR filter operations in parallel, where floating-point multiply–accumulate circuit (MAC) is used to design each second-order IIR filter. The proposed sixth-order IIR filter achieves a 58.4% reduction in energy per operation compared with conventional MAC-based architecture using 45-nm technology.

FPGA Implementation of Ultrasonic S-Scan Coordinate Conversion Based on Radix-4 CORDIC Algorithm

To solve the existing problems on traditional method of calling function at ultrasonic S-scan coordinate conversion, this paper introduced the FPGA implementation of ultrasonic S-scan coordinate conversion based on Radix-4 CORDIC algorithm. On the analysis of the Radix-4 Rotation CORDIC algorithm, we selected 7-level pipeline structure on FPGA, used the preprocessing technique to solve the non-constant problem of scale factor. The simulation results show that the maximum error of Radix-4 Rotation CORDIC algorithm is 1.5×10 -3 and the computing latency is only 7T at 16 bit data-width under 100MHz FPGA. The scan conversion rate speed up at least 10 times, and the output effect of the image is basically the same as the traditional method. The algorithm has the characteristics of low latency, high speed and high precision, suitable for real-time signal processing applications.

Reconfigurable Ultrasonic Testing System Development Using Programmable Analog Front-End and Reconfigurable System-on-Chip Hardware

Ultrasonic testing systems have been extensively used in medical imaging and non-destructive testing applications. Generally, these systems aim at a particular application or target material. To make these systems portable and more adaptable to the test environments, this study presents a reconfigurable ultrasonic testing system (RUTS), which possesses dynamic reconfiguration capabilities. RUTS consists a fully programmable Analog Front-End (AFE), which facilitates beamforming and signal conditioning for variety of applications. RUTS AFE supports up to 8 transducers for phased-array implementation. Xilinx Zynq System-on-Chip (SoC) based Zedboard provides the back-end processing of RUTS. The powerful ARM embedded processor available within Zynq SoC manages the ultrasonic data acquisition/processing and overall system control, which makes RUTS a unique platform for the ultrasonic researchers to experiment and evaluate a wide range of real-time ultrasonic signal processing applications. This Linux-based system is utilized for ultra-sonic data compression implementation providing a versatile environment for further development of ultrasonic imaging and testing system. Furthermore, this study demonstrates the capabilities of RUTS by performing ultrasonic data acquisition and data compression in real-time. Thus, this reconfigurable system enables ultrasonic designers and researchers to efficiently prototype different experiments and to incorporate and analyze high performance ultrasonic signal and image processing algorithms.