Abstract
Surface-plasmon-polariton waves propagating at the interface between a metal and a dielectric, hold the key to future high-bandwidth, dense on-chip integrated logic circuits overcoming the diffraction limitation of photonics. While recent advances in plasmonic logic have witnessed the demonstration of basic and universal logic gates, these CMOS oriented digital logic gates cannot fully utilize the expressive power of this novel technology. Here, we aim at unraveling the true potential of plasmonics by exploiting an enhanced native functionality - the majority voter. Contrary to the state-of-the-art plasmonic logic devices, we use the phase of the wave instead of the intensity as the state or computational variable. We propose and demonstrate, via numerical simulations, a comprehensive scheme for building a nanoscale cascadable plasmonic majority logic gate along with a novel referencing scheme that can directly translate the information encoded in the amplitude and phase of the wave into electric field intensity at the output. Our MIM-based 3-input majority gate displays a highly improved overall area of only 0.636 μm2 for a single-stage compared with previous works on plasmonic logic. The proposed device demonstrates non-Boolean computational capability and can find direct utility in highly parallel real-time signal processing applications like pattern recognition.
Highlights
For more than four decades, Moore’s law has been the driving force for the semiconductor industry
Using finite-difference-time domain (FDTD) simulations performed in commercially available software Lumerical Solutions[24], we provide a comprehensive scheme for building a nanoscale cascadable plasmonic majority logic gate
Note that since the emphasis of this work is on building a nanoscale cascadable plasmonic majority logic, we do not focus on the mechanism or circuits for excitation and final detection of Surface plasmon polaritons (SPP) which are the focus of separate works in the literature[25,26,27,28,29,30,31,32,33,34,35,36,37]
Summary
For more than four decades, Moore’s law has been the driving force for the semiconductor industry. A complete set of fundamental logic gates (basic and universal) have been realized by exploiting phase-dependent interference of SPP waves[18,19,20]. These CMOS based digital logic gate designs cannot exploit an important feature of plasmonic logic and wave computing, namely, the ability to execute majority voting efficiently. Using finite-difference-time domain (FDTD) simulations performed in commercially available software Lumerical Solutions[24], we provide a comprehensive scheme for building a nanoscale cascadable plasmonic majority logic gate. We investigate the cascadability of these gates by studying up to 3 stages of cascaded logic This is sufficient to support interesting arithmetic primitives like adders and multipliers with limited bit-width. Note that since the emphasis of this work is on building a nanoscale cascadable plasmonic majority logic, we do not focus on the mechanism or circuits for excitation and final detection of SPP which are the focus of separate works in the literature[25,26,27,28,29,30,31,32,33,34,35,36,37]
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