Real-time Logic Research Articles

Decidability of mean value calculus

Mean Value Calculus (MVC)[1] is a real-time logic which can be used to specify and verify real-time systems[2]. As a conservative extension of Duration Calculus (DC)[3], MVC increases the expressive power but keeps the properties of DC. In this paper we present decidability results of MVC. An interesting result is that propositional MVC with chop star operator is still decidable, which develops the results of [4] and [5].

Incremental modeling and verification of flexible manufacturing systems

An FMS is a typical real-time concurrent system composed of a number of computer-controlled machine tools, automated material handling and storage systems that operate as an integrated system under the control of host computer(s). The growing demand for higher performance and flexibility in these systems and the interlocking factors of concurrency, deadline-driven activities, and real-time decision making pose a significant challenge to FMS design, especially in terms of control and scheduling. A formal engineering approach that helps handle the complexity and dynamics of FMS modeling, design and analysis is needed. A real-time architectural specification (RAS) model and its application in the modeling of flexible manufacturing system (FMS) are presented. RAS combines mature operational and descriptive formal methods, in particular time Petri nets (TPN) and real-time computational tree logic (RTCTL), to form an integrated system model for architectural specification and analysis of real-time concurrent systems such as FMS. The contribution of RAS is twofold: First, it provides a formal system to systematically maintain a strong correlation between (real-time) requirements and design and to verify the conformance of the design to the requirements, which helps enhance traceability and thus to help us to achieve high assurance in design. Second, it offers better scalability in modeling and analysis, which provides an effective way to deal with complexity in the application of formal methods. These two features together make RAS a suitable model for the design of FMS.

Use of causal knowledge in a real-time fuzzy logic controller

The establishment of expert control techniques and their actual industrial impact have been inhibited by the lack of a comprehensive design methodology. This paper summarizes principal drawbacks limiting the development of a definitive methodology. It also addresses the key problem of acquisition of plant knowledge, clarifying first the types of knowledge. For a case study, a real-time fuzzy-rule-based controller using causal knowledge is designed for control of liquid level in a pilot plant and tested for closed-loop operation under different conditions of set-point change, noise disturbance and parametric change. The results show that it yields superior performance over a qualitative and a conventional proportional integral derivative controller implemented on the same plant and subjected to similar disturbances.

Current-Mode Fuzzy Linguistic Hedge Circuits

In this paper, a current-mode design methodology to implement a set of fuzzy linguistic hedge circuits is proposed. The so-called fuzzy linguistic hedge is a fuzzy operation applied to adjust the membership function of a fuzzy set. The fuzzy membership function of control variable and the control rules are very important in a fuzzy logic controller because they dominate the control strategies. If the control results fail to meet the system requirements, the control objective can still be achieved by adjusting the membership function of the fuzzy set or the control rules. Moreover, the adjustment effect of the control strategies through the modifications of the fuzzy membership function is the same as that of the system control rules. In this paper, we propose a set of fuzzy linguistic hedge circuits, including absolutely, very, much more, more, plus minus, more or less, slightly, and contrast intensification, which has been fabricated in 0.8 μm CMOS process. Experimental results show that the average error of the circuits is within 1% of the full scale current. Under the power supply voltage of 3.3 V, the operating dynamic range is 50 μA. Furthermore, these circuits still work well even when the power supply voltage is down to 2.5 V. In addition, in real world application, we can incorporate a membership function generator, a fuzzification unit, a multi-input maximum/minimum circuit, and a defuzzification unit with the linguistic hedge used to modify the membership function in order to develop a real-time adaptive fuzzy logic controller.

Industrial integration of graphical and formal specifications

This paper discusses an approach to formal methods technology exploitation which introduces formal notations into critical systems development processes. The provision of “Ω functions” that map graphical specifications into axiomatic formal specifications, which can then be subjected to proof, is explored as a means of achieving this goal. Such functions must treat a useful subset of the graphical language and be compatible with industrialized tools. Experiences in developing this approach for industrial application are discussed by means of an example mapping function known as Ω1. This function maps a subset of statecharts into Real Time Logic.

Continuous Estimation of CO2 Production during Exercise

A new method was developed for continuous isotopic estimation of human whole body CO2 rate of appearance (Ra) during non-steady state exercise. The technique consisted of a breath-by-breath measurement of 13CO2 enrichment (E) and a real-time fuzzy logic feedback system which controlled NaH13CO3 infusion rate to achieve an isotopic steady state. Ra was estimated from the isotope infusion rate and body 13CO2 enrichment which was equal to E at the isotopic steady state. During a non-steady state incremental cycle exercise (5 w/min or 10 w/min), NaH13CO3 infusion rate was successfully increased by the action of feedback controller so as to keep E constant.

A specification architecture for multimedia systems in Open Distributed Processing

The field of distributed systems is now entering a stage of maturity with work focusing on standards for Open Distributed Processing (ODP). However, it is still important that standardisation remains responsive to new technological demands such as the emergence of distributed multimedia computing. This paper focuses on the likely impact of multimedia computing on formal description within ODP. In particular, a specification architecture is proposed for the formal specification and verification of quality of service and more general real-time concerns in distributed multimedia systems. This specification architecture exhibits a separation of concerns between the specification of behaviour and requirements and also between the specification of abstract behaviour and real-time concerns. The architecture also supports refinement to the computational language defined by the ODP standard. It is important to stress that the architecture does not prescribe the use of specific formal notations or languages; particular specification disciplines can however be developed by populating the architecture with appropriate languages. The usefulness of this architecture is demonstrated by the development of such an approach based on LOTOS together with a real-time temporal logic, QTL. This is applied to a simple multimedia example.

Implementing Intelligence in Silicon Integrated Circuits Using Neuron-Like High-Functionality Transistors

The primary objective of this article is not to present integrated circuit implementation of neural networks in the sense that neurophysiological models are constructed in electronic circuits, but to describe new-architecture intelligent electronic circuits built using a neuron-like high-functionality transistor as a basic circuit element. This has greatly reduced the VLSI hardware/software burden in carrying out intelligent data processing and would find promising applications in robotics. The transistor is a multiple-input-gate thresholding device called a neuron MOSFET (neuMOS or νMOS) due to its functional similarity to a simple neuron model. vMOS circuits are characterized by a high degree of parallelism in hardware computation, large flexibility in the hardware configuration, and a dramatic reduction in circuit complexity compared to conventional integrated circuits. As a result, a number of new-concept circuits has been developed. Examples include a real-time reconfigurable logic circuit called flexware and associative memory conducting a fully parallel search for the most similar targets. A simple hardware model for self-learning systems is also presented. The enhancement in functionality at a very elemental transistor level is critical to building human-like intelligent systems on silicon.

Interval logics and their decision procedures Part II: A real-time interval logic

Abstract In a companion paper, we presented an interval logic, and showed that it is elementarily decidable. In this paper we extend the logic to allow reasoning about real-time properties of concurrent systems; we call this logic real-time future interval logic (RTFIL). We model time by the real numbers, and allow our syntax to state the bounds on the duration of an interval. RTFIL possesses the “real-time interpolation property,” which appears to be the natural quantitative counterpart of invariance under finite stuttering. As the main result of this paper, we show that RTFIL is decidable; the decision algorithm is slightly more expensive than for the untimed logic. Our decidability proof is based on the reduction of the satisfiability problem for the logic to the emptiness problem for timed Buchi automata. The latter problem was shown decidable by Alur and Dill in a landmark paper, in which this real-time extension of ω-automata was introduced. Finally, we consider an extension of the logic that allows intervals to be constructed by means of “real-time offsets”, and show that even this simple extension renders the logic highly undecidable.

A real-time interval logic and its decision procedure

Real-Time Future Interval Logic is a temporal logic in which formulæ have a natural graphical representation, resembling timing diagrams. It is a dense real-time logic that is based on two simple temporal primitives:interval modalities for the purely qualitative part andduration predicates for the quantitative part. This paper describes the logic and gives a decision procedure for satisfiability by reduction to the emptiness problem for Timed Büchi Automata. This decision procedure forms the core of an automated proof-checker for the logic. The logic does not admit instantaneous states, and is invariant under real-time stuttering, properties that facilitate proof methods based on abstraction and refinement. The logic appears to be as strong as one can hope for without sacrificing elementary decidability. Two natural extensions of the logic, along lines suggested in the literature, lead to either non-elementariness or undecidability.

Specification and verification of reactive system behaviour: The Railroad Crossing example

In this paper we present an approach to the specification and verification of reactive systems. The approach uses Timed Statecharts and Real Time Logic for the specification of temporal behaviour, and theorem proving techniques for the verification of safety and utility properties. Formal verification is achieved through the automation of semi-formal (rigorous) proofs using a theorem prover (Proofpower HOL). To illustrate the approach, we use the Railroad Crossing Problem, which has been proposed, along with a set of criteria for assessment, as a benchmark for the comparison of real-time formalisms. We conclude with our assessment of the approach against the proposed criteria.

Checking timing constraints in distributed object-oriented programs

In real-time systems design-assumptions can be divided into functional and temporal assumptions. While checks for functional correctness are already addressed by some modern programming languages (e.g. Eiffel's pre- and postconditions), checks for temporal correctness are usually out of the scope of the existing programming or runtime systems. Our work in the DIRECT [GKS94] project tries to fill this gap. A methodology for specifying and checking timing constraints in an object-oriented environment is presented. The approach extends previous work on RTL[JM86] (Real-Time Logic) based monitors towards an object-oriented responsive system. The paper focuses on how object-orientation can be utilized to simplify the specification and the checking of timing constraints and how this can be integrated into an existing programming language like C++.

Automated deduction in a graphical temporal logic

ABSTRACT Real-time graphical interval logic is a modal logic for reasoning about time in which the basic modality is the interval. The logic differs from other logics in that it has a natural intuitive graphical representation that resembles the timing diagrams drawn by system designers. We have developed an automted deduction system for the logic, which includes a theorem prover and a user interface. The theorem prover checks the validity of proofs in the logic and produces counterexamples to invalid proofs. The user interface includes a graphical editor that enables the user to create graphical formulas on a workstation display, and a database and proof manager that tracks proof dependencies and allows graphical formulas to be stored and retrieved. In this paper we describe the logic, the automated deduction system, and an application to robotics.

A Fuzzy Logic Beam-and-Ball Controller Prototype

In this study, we describe the design and hardware implementation of a real-time fuzzy logic controller for a nontrivial nonlinear system control application, balancing a beam-and-ball system in re...

Formal specification and verification of multimedia systems in open distributed processing

The field of distributed systems is now entering a stage of maturity with work focusing on standards for Open Distributed Processing (ODP). However, it is still important that standardization remains responsive to new technological demands such as the emergence of distributed multimedia computing. This paper focuses on the likely impact of multimedia computing on formal description within ODP. In particular, a framework is proposed for the formal specification and verification of quality of service and more general real-time concerns in distributed multimedia systems. This framework exhibits a separation of concerns between the specification of behaviour and requirements and also between the specification of abstract behaviour and real-time concerns. The usefulness of this framework is demonstrated by the development of an approach based on LOTOS together with a real-time temporal logic, QTL.

Real-Time Software Development with Formal Models

Improvements in microprocessor technology have prompted a willingness to embed computer hardware in structural and mechanical systems. Active structural control is one such application in which computer-based sensors and actuators work to limit vibrations and reduce the possibility of failure in seismic events. Although there have been numerous studies on control strategies for these real-time systems, our goal is to develop approaches that can ensure the overall reliability of the software before deployment. In this paper, we outline a three-step approach based on formal methods for designing reliable real-time systems. This approach includes an analysis of the required timing properties, a modeling technique based on real-time logic and Modechart, and a verification procedure using simulation and model checking. As demonstrated with an application to structural control, this process ensures that the necessary timing properties are satisfied by a given hardware and software architecture.

Comparing RTL and FNLOG- timing properties in real-time systems

The specification and verification of real-time systems is an important component in the reliable development of such systems. Formal techniques of specification and verification have the advantage of formal analysis and design, as well as the possibility of automating some of the processes. FNLOG is a logic-based specification language for real-time systems, which is based on first order predicate logic with arithmetic extended by quantified temporal operators. FNLOG semantics is based on an underlying statechart, and a sound and relatively complete proof system for FNLOG exists. This paper presents extensions to FNLOG, inspired by Real Time Logic (RTL), to facilitate the specification of periodic and sporadic properties of real-time systems.

Performance enhancement using forward error correction on power line communication channels

The use of forward error correction (FEC) coding is investigated, to enhance communication throughput and reliability on noisy power line networks. Rate one-half self-orthogonal convolutional codes are considered. These codes are known to be effective in other environments, and can be decoded inexpensively in real-time using majority logic decoders. Extensive bit and packet error rate tests were conducted on actual, noisy in-building power line links. Coding gains of 15 dB were observed at 10/sup -3/ decoded bit error rates. A self-orthogonal (2, 1, 6) convolutional code with interleaving to degree 7 was particularly effective, and was implemented as a VLSI microelectronic chip. Its use improved data throughput and packet error rates substantially, at data transmission rates of 9,600 bits/s. >

Modechart: a specification language for real-time systems

Present a specification language for real-time systems called Modechart. The semantics of Modechart is given in terms of real-time logic (RTL), which is especially amenable to reasoning about the absolute (real-time clock) timing of events. The semantics of Modechart has an important property that the translation of a Modechart specification into RTL formulas results in a hierarchical organization of the resulting RTL assertions. This gives us significant leverage in reasoning about properties of a system by allowing us to filter out assertions that concern lower levels of abstraction. Some results about desirable properties of Modechart specifications are given. A graphical implementation of Modechart has been completed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Real-Time Logics: Complexity and Expressiveness

The theory of the natural numbers with linear order and monadic predicates underlies propositional linear temporal logic. To study temporal logics that are suitable for reasoning about real-time systems, we combine this classical theory of infinite state sequences with a theory of discrete time, via a monotonic function that maps every state to its time. The resulting theory of timed state sequences is shown to be decidable, albeit nonelementary, and its expressive power is characterized by ω-regular sets. Several more expressive variants are proved to be highly undecidable. This framework allows us to classify a wide variety of real-time logics according to their complexity and expressiveness. Indeed, it follows that most formalisms proposed in the literature cannot be decided. We are, however, able to identify two elementary real-time temporal logics as expressively complete fragments of the theory of timed state sequences, and we present tableau-based decision procedures for checking validity. Consequently, these two formalisms are well-suited for the specification and verification of real-time systems.