Real-time Image Processing Requirement Research Articles

End-to-end dehazing of traffic sign images using reformulated atmospheric scattering model

As an advanced machine vision task, traffic sign recognition is of great significance to the safe driving of autonomous vehicles. Haze has seriously affected the performance of traffic sign recognition. This paper proposes a dehazing network, including multi-scale residual blocks, which significantly affects the recognition of traffic signs in hazy weather. First, we introduce the idea of residual learning, design the end-to-end multi-scale feature information fusion method. Secondly, the study used subjective visual effects and objective evaluation metrics such as Visibility Index (VI) and Realness Index (RI) based on the characteristics of the real-world environment to compare various traditional dehazing and deep learning dehazing method with good performance. Finally, this paper combines image dehazing and traffic sign recognition, using the algorithm of this paper to dehaze the traffic sign images under real-world hazy weather. The experiments show that the algorithm in this paper can improve the performance of traffic sign recognition in hazy weather and fulfil the requirements of real-time image processing. It also proves the effectiveness of the reformulated atmospheric scattering model for the dehazing of traffic sign images.

Design and Implementation of Brightness Configurable Bi-Histogram Equalization Based on FPGA

In order to improve the contrast of images in different brightness environments, based on brightness preserving Bi-Histogram Equalization(BBHE), a Brightness configurable Bi-Histogram Equalization(BCBHE) system is proposed and implemented by FPGA in this paper. The system implements the BBHE algorithm, and adds the brightness configurable logic unit to realize the brightness configurable image contrast enhancement. The test results of the video processing platform of Genesys 2 development board show that: the design obtains BBHE images with different brightness configurations, and achieves the best contrast enhancement visual effect by setting image brightness threshold in different field environment. At the same time, based on the parallel operation characteristics of the FPGA, it meets the requirements of real-time image processing.

Video stabilization algorithm for tunnel robots based on improved Kalman filter

The application of tunnel robots in power tunnels is becoming more and more extensive. Due to various reasons, video jitter will inevitably occur during the inspection process, which will affect the real-time processing of subsequent images. In order to reduce the impact of video jitter and meet the requirements of real-time image processing, it is necessary to study fast video image stabilization methods. The traditional Kalman filtering algorithm has less computational cost, but it will cause a large estimation error when the system motion state changes. In this regard, the paper proposes an improved Kalman filtering algorithm, which changes the corresponding filter parameters by real-time estimation of a system in motion to reduce the estimation error. And this algorithm performs Harris corner extraction in the set feature dense area, and combines the PyrLK optical flow algorithm with the homography matrix to calculate the motion trajectory, which improves the calculation speed and accuracy of the algorithm. Experimental results show that this algorithm has better video stabilization effect and faster calculation speed compared with the traditional Kalman filtering algorithm, and can better meet the real-time image processing requirements in the inspection process.

Real-time image carrier generation based on generative adversarial network and fast object detection

Image steganography aims to conceal the secret information inside another carrier image. And by embedding the information into the carrier image, the carrier image may suffer certain image distortion. Thus, not only the hiding algorithm should be carefully designed, but also the carrier image should be meticulously selected during the hiding process. This paper follows the idea of creating suitable cover images instead of selecting the ones by presenting a unified architecture which combines real-time object detection based on convolutional neural network, local style transfer using generative adversarial network and steganography together to realize real-time carrier image generation. The object in the carrier image is first detected using a fast object detector and then the detected area is reconstructed through a local generative network. The secret message is embedded into the intermediate generated images during the training process in order to generate an image which is suitable as an image carrier. The experimental results show that the reconstructed stego images are nearly indistinguishable to both human eyes and steganalysis tools. Furthermore, the whole carrier image generation process with GPU implementation can achieve around 5 times faster than the regular CPU implementation which meets the requirement of real-time image processing.

Resource-Efficient Image Buffer Architecture for Neighborhood Processors

Neighborhood image processing operations on Field Programmable Gate Array (FPGA) are considered as memory intensive operations. A large memory bandwidth is required to transfer the required pixel data from external memory to the processing unit. On-chip image buffers are employed to reduce this data transfer rate. Conventional image buffers, implemented either by using FPGA logic resources or embedded memories are resource inefficient. They exhaust the limited FPGA resources quickly. Consequently, hardware implementation of neighborhood operations becomes expensive, and integrating them in resource constrained devices becomes unfeasible. This paper presents a resource efficient FPGA based on-chip buffer architecture. The proposed architecture utilizes full capacity of a single Xilinx Block-RAM (BRAM36 primitive) for storing multiple rows of input image. To get multiple pixels/clock in a user defined scan order, an efficient duty-cycle based memory accessing technique is coupled with a customized addressing circuitry. This accessing technique exploits switching capabilities of BRAM to read 4 pixels in a single clock cycle without degrading system frequency. The addressing circuitry provides multiple pixels/clock in any user defined scan order to implement a wide range of neighborhood operations. With the saving of 83% BRAM resources, the buffer architecture operates at 278 MHz on Xilinx Artix-7 FPGA with an efficiency of 1.3 clock/pixel. It is thus capable to fulfill real time image processing requirements for HD image resolution ( $1080\times 1920$ ) @103 fps.

Development of Distributed Control System for Vision-Based Myoelectric Prosthetic Hand

Vision-based myoelectric prosthetic hand uses a camera integrated into its body for object detection and environment understanding, where the results provide necessary information for grasp planning. It is expected that the semi-automatic prosthesis control can be realized with this method. However, such a control method usually suffers from heavy computation due to the requirement of real-time image processing to keep up with the arm movements of the user. This paper presents a distributed control system that assigns heavy processing tasks to one or multiple processing nodes through the network, which greatly reduces the computation burdens of the processor embedded in the prosthetic hand. In this control scheme, the embedded system in the prosthetic hand is only used for gathering necessary data for grasp planning, while the processing nodes in the network are responsible for processing and managing the collected data. A test platform is built to verify the proposed control scheme. The test platform streams user electromyography (EMG) signals and images simultaneously to the GPU server. The GPU sever analyzes the received data and generates the corresponding motor commands in real time. A case study that uses a 3-DoF gripper to continuously grasp several objects is performed using this test platform.

Image De-noising on Strip Steel Surface Defect Using Improved Compressive Sensing Algorithm

De-noising for the strip steel surface defect image is conductive to the accurate detection of the strip steel surface defects. In order to filter the Gaussian noise and salt and pepper noise of strip steel surface defect images, an improved compressive sensing algorithm was applied to defect image de-noising in this paper. First, the improved Regularized Orthogonal Matching Pursuit algorithm was described. Then, three typical surface defects (scratch, scar, surface upwarping) images were selected as the experimental samples. Last, detailed experimental tests were carried out to the strip steel surface defect image de-noising. Through comparison and analysis of the test results, the Peak Signal to Noise Ratio value of the proposed algorithm is higher compared with other traditional de-noising algorithm, and the running time of the proposed algorithm is only26.6\% of that of traditional Orthogonal Matching Pursuit algorithms. Therefore, it has better de-noising effect and can meet the requirements of real-time image processing.

Experiment Design Regularization-Based Hardware/Software Codesign for Real-Time Enhanced Imaging in Uncertain Remote Sensing Environment

A new aggregated Hardware/Software (HW/SW) codesign approach to optimization of the digital signal processing techniques for enhanced imaging with real-world uncertain remote sensing (RS) data based on the concept of descriptive experiment design regularization (DEDR) is addressed. We consider the applications of the developed approach to typical single-look synthetic aperture radar (SAR) imaging systems operating in the real-world uncertain RS scenarios. The software design is aimed at the algorithmic-level decrease of the computational load of the large-scale SAR image enhancement tasks. The innovative algorithmic idea is to incorporate into the DEDR-optimized fixed-point iterative reconstruction/enhancement procedure the convex convergence enforcement regularization via constructing the proper multilevel projections onto convex sets (POCS) in the solution domain. The hardware design is performed via systolic array computing based on a Xilinx Field Programmable Gate Array (FPGA) XC4VSX35-10ff668 and is aimed at implementing the unified DEDR-POCS image enhancement/reconstruction procedures in a computationally efficient multi-level parallel fashion that meets the (near) real-time image processing requirements. Finally, we comment on the simulation results indicative of the significantly increased performance efficiency both in resolution enhancement and in computational complexity reduction metrics gained with the proposed aggregated HW/SW co-design approach.

A Multiplierless 2-D Convolver Chip for Real-Time Image Processing

This paper proposes a new real-time 2-D convolver chip with no multiplier. Several commercial 2-D convolver chips have many multipliers and existing multiplierless architectures have many shift-and-accumulators to meet the real-time image processing requirement, i.e., the standard of CCIR601. Even though the proposed architecture uses only one shift-and-accumulator, it can meet the real-time requirement. Furthermore, because it controls the input data sequence, the proposed chip does not require row buffers to store two adjacent rows as do commercial chips, and it can further reduce the gate count. The proposed architecture can reduce the gate count by more than 70 and 90% compared to HSP48901 and HSP48908, respectively, and the gate count of the computation block itself by more than 70% compared to existing multiplierless architectures. We have implemented the chip using the Samsung™ 0.8 μm SOG cell library (KG60K). The implemented filter chip consists of only 3,893 gates, operates at 125 MHz and can meet the real-time image processing requirement. The proposed architecture is especially suitable for larger size convolutions because of its small gate count.

A morphological filter chip using a modified decoding function

This paper proposes a new very large scale integration architecture for cost-effective morphological filters and presents its design and chip implementation. The proposed architecture can reduce the hardware cost by using a feedback loop path and a decoder/encoder pair comparator. The feedback loop path can reuse partial results to reduce the number of add/subtract units. The decoder/encoder pair comparator using a modified decoding function can reduce the gate count and propagation delay especially when the size of morphological operations increases. We used the 0.8-/spl mu/m SOG cell library (KG60 K) and the total number of gates is only 2667. The proposed morphological filter chip has actually been fabricated and is running at 30 MHz that meets the real-time image processing requirement of the ITU-R BT.601 standard.