Real-time Debugging Research Articles

Adaptive Synchronization and Pacing Control for Visual Interactive Simulation

Parallel and distributed computing enable the execution of large and complex simulations. Yet, the usual separation of (headless) simulation execution and (subsequent, offline) output analysis often renders the simulation endeavor long and inefficient. Recently, Visual Interactive Simulation (VIS) tools and methods that address this end-to-end efficiency are gaining relevance, offering in-situ visualization, real-time debugging, and computational steering. Here, the typically distributed computing nature of the simulation execution poses synchronization challenges between the headless simulation engine and the user-facing frontend required for Visual Interactive Simulation. To the best of our knowledge, state-of-the-art synchronization approaches fall short due to their rigidity and inability to adapt to real-time user-centric changes. This paper introduces a novel adaptive algorithm to dynamically adjust the simulation’s pacing through a buffer-based framework, informed by predictive workload analysis. Our extensive experimental evaluation across diverse synthetic scenarios illustrates our method’s effectiveness in enhancing runtime efficiency and synchronicity, significantly reducing end-to-end time while minimizing user interaction delays, thereby addressing key limitations of existing synchronization strategies.

A Study on the Real-Time Visual Debugging of Hierarchically Designed Logic Circuits

A Study on the Real-Time Visual Debugging of Hierarchically Designed Logic Circuits

Using CoreSight PTM to Integrate CRA Monitoring IPs in an ARM-Based SoC

The ARM CoreSight Program Trace Macrocell (PTM) has been widely deployed in recent ARM processors for real-time debugging and tracing of software. Using PTM, the external debugger can extract execution behaviors of applications running on an ARM processor. Recently, some researchers have been using this feature for other purposes, such as fault-tolerant computation and security monitoring. This motivated us to develop an external security monitor that can detect control hijacking attacks, of which the goal is to maliciously manipulate the control flow of victim applications at an attacker’s disposal. This article focuses on detecting a special type of attack called code reuse attacks (CRA), which use a recently introduced technique that allows attackers to perform arbitrary computation without injecting their code by reusing only existing code fragments. Our external monitor is attached to the outside of the host system via the system bus and ARM CoreSight PTM, and is fed with execution traces of a victim application running on the host. As a majority of CRAs violates the normal execution behaviors of a program, our monitor constantly watches and analyzes the execution traces of the victim application and detects a symptom of attacks when the execution behaviors violate certain rules that normal applications are known to adhere. We present two different implementations for this purpose: a hardware-based solution in which all CRA detection components are implemented in hardware, and a hardware/software mixed solution that can be employed in a more resource-constrained environment where the deployment of full hardware-level CRA detection is burdensome.

Statistical assertion: A more powerful method for debugging scientific applications

Traditional debuggers are of limited value for modern scientific codes that manipulate large complex data structures. Current parallel machines make this even more complicated, because the data structure may be distributed across processors, making it difficult to view/interpret and validate its contents. Therefore, many applications’ developers resort to placing validation code directly in the source program. This paper discusses a novel debug-time assertion, called a “Statistical Assertion”, that allows using extracted statistics instead of raw data to reason about large data structures, therefore help locating coding defects. In this paper, we present the design and implementation of an ‘extendable’ statistical-framework which executes the assertion in parallel by exploiting the underlying parallel system. We illustrate the debugging technique with a molecular dynamics simulation. The performance is evaluated on a 20,000 processor Cray XE6 to show that it is useful for real-time debugging.

Real-Time Debugging and Testing a Control System Using Matlab

In this paper two methods for real-time debugging and testing of a control system are proposed. The basic instruments used are personal computers, a Visual C++ compiler and MATLAB including the GUI Design Environment, Simulink, real-time workshop, xPC target, and some relevant hardware. For the first method, MATLAB functions are used to build a control system debugging and testing environment. This method is flexible and only one RS-232 serial cable is used. Limited programming is used for the second method and ready-made blocks in MATLAB/Simulink are used to build the simulation environment and communication channel. In both methods, the parameters of the emulation system can be modified online, important graphs can be drawn in real time and relevant data can be easily saved for the later analysis. As can be seen from the presented examples, both techniques are easily realized.

Development of A Wearable and WBAN-Based Vital Signs Monitoring System for Low-cost Personal Healthcare in Qatar

Population aging is a worldwide phenomenon, but its impact on Qatar is unique. The proposed system aims at comprehensive and integrated vital signs (ECG, Saturation of Arterial Oxygen (SpO2), BP and Heart rate (HR)) monitoring using a wearable sensor platform without professional involvements or interfering the elderly's everyday activities. A novel wireless physiological sensor node with single highly-integrated board has been specifically designed and fabricated ( Fig.1(a) ). The new board comprises of a MCU, ECG analog front-end, LED driver and brightness adjustment circuit for photoplethysmograph (PPG) measurement, a CC2420 chip for wireless communication and a FTDI FT232RL chip for MCU programming and real-time debugging. A miniaturized wireless gateway was also designed ( Fig.1(b) ) to wirelessly receive the data from sensor node and further relay to the PC for ongoing research on ECG denoising and arrhythmia classification. A novel MEMS-based electrode has been designed and fabricated for ECG measurement as shown in Fig.2 . Compared with conventional ECG electrodes, micromachined electrode is more comfortable; no direct contact of gel with the human skin and imposes no side effects to human for continuous and long term measurement. A unique characteristic feature of the proposed electrode is that the microneedle array is made of heavily doped silicon, which is electrically conductive and eliminates the requirement to dope Ag/AgCl or metal layer on the microneedles for electric contact. The microneedles can directly pierce through the outer skin surface, lowering the electrode-skin-electrode impedance (ESEI) and eliminating the need for skin preparation which, is prerequisite for wet electrode. For long-term monitoring, mechanical failure of micro-needles may accidentally happen due to the axial loading during insertion process or transverse loading during the measurement. As a result, the broken silicon needles will become debris in the skin, which attracts healthy concern for the user. Therefore, critical buckling loads for fabricated micro-needle were investigated using both theoretical estimation and ANSYS simulation. The results show that the critical buckling load is much larger than theoretical insertion force thereby the buckling problem will not occur during the insertion process. This work is supported by Qatar National Research Funding (QNRF) under the grant NPRP 09-292-2-113.

Formal timing analysis for distributed real-time programs

A static analysis method for verifying timing properties of real-time distributed programs is presented. The goal is to calculate the worst-case response time of concurrent tasks which run mainly independently but share, and may have to wait for, logical or physical devices. For such tasks, the determination of the worst-case waiting time is a crucial problem because of the unpredictable order of synchronization events. We investigate the class of distributed Client-Server programs in which independent, time-critical tasks (clients) are synchronized only through additional server tasks, playing the role of monitors or resource managers. This model follows well-known real-time design guidelines for distributed ADA programs proposed to enhance schedulability and synchronization analysis. Our formal analysis approach is flow graph oriented. It leads to generating reduced program paths each of which represents a sequence of ordered local and global operations, thus transforming and reducing the original problem of computing the worst-case waiting time of a concurrent task into a graph-theoretic problem of calculating the maximal blocking time for one of its corresponding program paths. While local operations are completely independent global operations require mutually exclusive access to shared resources. We prove that computing the worst-case blocking time for a program path is NP-complete. Even for a reduced problem solution—which would yield a good upper bound for the worst-case blocking time—there was a conjecture maintained over many years that this problem was NP-complete. A major result of this paper is to show that this is wrong. Instead, we construct a polynomial solution algorithm, and we prove its correctness. The effectiveness and complexity of our method are discussed, with particular emphasis on distributed real-time debugging.

Realtime high level debugging in host/target environments

Programs for embedded systems with 16- or 32-bit microprocessors, often realtime systems, are usually written in a high level programming language and are based on a realtime multitasking kernel. But, available microprocessor development systems do not sufficiently support realtime debugging of such software at a high level. Only tools for realtime debugging at a level which lies between assembler and high level languages, are available. This paper presents new concepts for realtime high level debugging tools in host/target environments. In addition a prototype of a realtime high level debugging system is introduced, which allows debugging of programs written in a high level language (C or Pascal) and based on an object oriented realtime multitasking kernel in the target microcomputer.

Synchronous debugging of real-time microprocessor-based control systems

Real-time debugging of large microprocessor control software applications can be a formidable task. Programmers must be concerned with more than software requirements. The develop ment tools, the electrical control hardware and debugging techniques all affect an individual's productivity. This paper contrasts software debugging environments and their capabilities. A xerographic copier is used as an example of a real- time application. Two debugging environments are discussed. One is a real-time-only configuration where copier application software is debugged using the actual copier. The other, sug gested as an improved method, substitutes a real-time simulator in place of the copier. In each case the actual electrical control system of the copier is used. A copier is a mechanical device that cannot be stopped quickly. This characteristic is not a good match for software debugging methods that use breakpoints and stepping techniques. Com mercial microprocessor development equipment aids the de bugging effort by adding hardware support to store trace infor mation while debugging in real time. Although this is an effective method for debugging software, there are several shortcomings that should be evaluated. These are: • Only a portion of software debugging techniques can be used in this real-time-only environment. • The copier's operation is difficult to monitor and change. The copier is inflexible in comparison to the capabilities of the software debugging tools. Simulating the copier, on the other hand, offers significant debugging capabilities to the control applications engineer. • It is a separate computer system. The computer characteristics of the simulator match the character of the software de bugging tools. • It can be manipulated, as desired, on-line. • It is capable of displaying the copier in two-dimensional form. The complete development environment including the simu lator, a microprocessor support and in-circuit emulator system, a logic analyzer and copier controls can be stopped by adding a hardware signal called "freeze." This signal is asserted by any development equipment to synchronously stop the entire en vironment. Considerations for designing the freeze function into the electrical controls system are discussed. Synchronizing the development environment during debugging, enables use of powerful non-real-time debugging techniques. This configuration offers the controls application programmer an efficient alternative to "run to crash" techniques commonly used in real-time-only efforts.

Summary of evaluation and comments

On the last day of the Symposium an evaluation form was distributed to all participants. About half responded; their comments are summarized here. Three-quarters of those responding felt the Symposium met their expectations well or very well. Important topics reported as being not discussed or not sufficiently discussed included real-time debugging, practical debugging strategies, implementation issues for production debuggers, human factors, and architectural support for debugging.

Summary of evaluation and comments

On the last day of the Symposium an evaluation form was distributed to all participants. About half responded; their comments are summarized here. Three-quarters of those responding felt the Symposium met their expectations well or very well. Important topics reported as being not discussed or not sufficiently discussed included real-time debugging, practical debugging strategies, implementation issues for production debuggers, human factors, and architectural support for debugging.

Real-Time Speech Coder Implementation on an Array Processor

The feasibility of a speech coding algorithm is most effectively indicated by its successful real-time implementation. The implementation effort presents issues distinct from those related to the development of the algorithm. Problems of real-time software design and debugging, system reliability, and implementation correctness must be addressed. In addition, the power of a general purpose array processing computer may be required to accomplish the real-time aspect of the implementation. The unique, often highly parallel, architecture of available array processors can present the additional issues of multiprocessor intercommunication and control. This paper considers successful approaches to these issues in the context of two real-time speech coder algorithms implemented on an array processor, a linear predictive baseband coder operating at 9.6 kbits/s, and an adaptive predictive coder operating at 16 kbits/s.

Automatic Intercept System: Development Support Systems

A series of hardware-software packages has been developed to aid the Automatic Intercept System (AIS) development. These packages involve a PDP-9 support computer connected to the AIS control unit through specially designed hardware. Described in this paper are a real-time debugging system, a series of three support computer programs which aid in the administration of AIS program development, and two utility programs used in connection with the AIS file subsystem.