Circuit Realization Research Articles

Single Miller Compensation Based Four Stage CMOS Amplifier

Like reversed nested Miller compensation, four nested Miller loops are exploited as a compensation network for a four-stage amplifier. However, isolating the feed-forward path via two differential stages allows the use of a single Miller compensation capacitor while the output node remains intact regarding capacitive loading from compensation. The exploited configuration for the compensation network provides the capability of reducing the number and size of needed capacitors due to positioning at the outputs of differential stages. This scenario is linearly modeled by a transfer function, then a circuit realization is suggested and simulated using 0.18 µm CMOS technology. According to the simulation results, the proposed amplifier can obtain 158 dB DC gain, 11.2 MHz GBW, and 84° PM while consuming 298 µW. Ample sensitivity analysis verifies the robustness of the proposed amplifier against probable mismatches and errors.

Multimodal shunt damping of monolithic bladed drums using multiple digital vibration absorbers

Abstract Based on a digital realization of piezoelectric shunt circuits, this works presents a proof-of-concept damping approach tailored to address the complex dynamics of monolithic bladed drums (BluMs) and attenuate their vibrations. This approach comprises the simultaneous use of multiple digital vibration absorbers (DVAs) together with a mean shunt strategy, taking advantage of the fact that multiple absorbers act simultaneously on the structure and that the blade modes of BluMs appear closely-spaced. In order to target multiple groups of modes, this strategy is incorporated in a multi-staged shunt circuit. The damping concept is numerically and experimentally demonstrated on a BluM with multiple piezoelectric patches, proving its ability to achieve excellent damping performance on multiple groups of modes. This performance is shown to be relatively insensitive to the spatial distribution of the shunted patches. Based on a robustness study, it was also found that the shunts are robust to changes in the host structure which could, e.g., be due to mistuning. Owing their digital nature, DVAs are easily adjustable making them highly attractive in practical applications.

Single-Molecule Conductance of Neutral Closed-Shell and Open-Shell Diradical Indenofluorenes.

Organic diradicals are highly promising candidates as future components in molecular electronic and spintronic devices because of their low spin-orbit coupling. To advance toward final circuit realizations, a thorough knowledge of the behavior of diradicals within a single-molecule junction framework is imperative. In this work, we have measured for the first time the single-molecule conductance of a neutral open-shell diradical compound, a [2,1-b] isomer of indenofluorene (IF). Our results reveal that the conductance of the [2,1-b] isomer is about 1 order of magnitude higher than that of the corresponding closed-shell regioisomer [1,2-b] IF. This is significant, as it fundamentally demonstrates the possibility of forming stable single-molecule junctions using neutral diradical compounds which are also highly conducting. This opens up a new approach to the development of externally addressable spintronic devices operable at room temperature.

Realization of 4-Bit Parity Checker Circuit Using XPM Technique-Based Phase-Shifted Fiber Bragg Grating Scheme

Realization of 4-Bit Parity Checker Circuit Using XPM Technique-Based Phase-Shifted Fiber Bragg Grating Scheme

Microscopic deconstruction of cortical circuit stimulation by transcranial ultrasound.

Transcranial Ultrasound Stimulation (TUS) can noninvasively and reversibly perturb neuronal activity, but the mechanisms by which ultrasound engages brain circuits to induce functional effects remain unclear. To elucidate these interactions, we applied TUS to the cortex of awake mice and concurrently monitored local neural activity at the acoustic focus with two-photon calcium imaging. We show that TUS evokes highly focal responses in three canonical neuronal populations, with cell-type-specific dose dependencies. Through independent parametric variations, we demonstrate that evoked responses collectively scale with the time-average intensity of the stimulus. Finally, using computational unmixing we propose a physiologically realistic cortical circuit model that predicts TUS-evoked responses as a result of both direct effects and local network interactions. Our results provide a first direct evidence of TUS's focal effects on cortical activity and shed light on the complex circuit mechanisms underlying these effects, paving the way for TUS's deployment in clinical settings.

Microwave artificial neurons based on magnetic tunnel junction nano-oscillators for image recognition and denoising

We report a microwave artificial neuron based on magnetic tunnel junction spin torque nano-oscillator (STNO). Based on STNO neurons, the three-layer full connected artificial neural network (ANN) are constructed to recognize handwritten digit with a produced accuracy of up to 90.95%. To address noise inherent in real circuits leads to poor recognition accuracy, we harness the frequency mutation characteristics of the STNO output near the critical threshold current for denoising handwritten digits corrupted by noise. Before and after denoising using the aforementioned ANN, the recognition accuracy is improved from 55.98% to 88.76%.

The impact of take-home laboratories on student perceptions of conceptual and professional learning in electronic engineering across four European universities

ABSTRACT Research exploring the advantages and limitations of different laboratory modes on student learning is critical so that engineering instructors can design hybrid/blended laboratories to maximise student learning. However, limited research explores the impact of take-home laboratories on student learning. This article documents the impact that the "HELP" take-home laboratory had on student perceptions of conceptual and professional learning across four European universities within the discipline of electronic engineering. Impact was evaluated through a student questionnaire that included Likert-scale and open-ended questions and was completed by 74 participants. The research extends what is known by revealing how take-home laboratories supported student understanding. Participants report that having flexible access and more time to build and test real circuits enhanced their understanding. Participants also reported that take-home laboratories supported the development of specific professional skills. Based on the student perspective, an implication of this research is that take-home laboratories can legitimately complement other laboratory modalities.

A Computer Model of a Marx Generator Charging a Coaxial Switched Wave Oscillator

The paper describes an axisymmetric Finite-Difference Time-Domain computer model of a coaxial Switched Wave Oscillator integrated with a dipole antenna. The model analyzes the operation of a realistic circuit model of a multistage Marx generator that charges the oscillator to a high voltage. The initial field distribution is calculated with an electrostatic finite-difference method solver to speed up the time-domain analysis. The work presents the results of our circuit model of a Marx generator’s simulations of the charging phase, followed by the results from the discharge phase, using our axisymmetric Finite-Difference Time-Domain model. Our work describes new and fast numerical solvers that can observe the operation of Switched Wave Oscillator systems (also considering the connected antenna). The codes could be used in the process of designing such a system. Advanced boundary conditions modeling the spark gap and oscillator’s excitation set our work apart from the other attempts in the literature.

SAT-based Formal Verification of Fault Injection Countermeasures for Cryptographic Circuits

Fault injection attacks represent a type of active, physical attack against cryptographic circuits. Various countermeasures have been proposed to thwart such attacks, however, the design and implementation of which are intricate, error-prone, and laborious. The current formal fault-resistance verification approaches are limited in efficiency and scalability. In this paper, we formalize the fault-resistance verification problem and show that it is coNP-complete. We then devise a novel approach for encoding the fault-resistance verification problem as the Boolean satisfiability (SAT) problem so that modern off-the-shelf SAT solvers can be utilized. The approach is implemented in an open-source tool FIRMER which is evaluated extensively on realistic cryptographic circuit benchmarks. The experimental results show that FIRMER is able to verify fault-resistance of almost all (72/76) benchmarks in 3 minutes (the other three are verified in 35 minutes and the hardest one is verified in 4 hours). In contrast, the prior approach fails on 31 fault-resistance verification tasks even after 24 hours (per task).

A new hyperchaotic system: circuit realization, nonlinear analysis and synchronization control

This paper presents a novel seven-dimensional nonlinear hyperchaotic system characterized by a minimal number of nonlinear terms and variables, yet exhibiting high complexity. Standard nonlinear analysis is conducted to unveil the system’s intricacies, emphasizing its notable feature of possessing four to five Lyapunov exponents in certain intervals, signifying its volatility and complexity. Hyperchaotic synchronization is explored using a novel nonsingular terminal sliding control design, effectively achieving synchronization between two hyperchaotic master systems and a hyperchaotic slave system within finite time while mitigating the chattering phenomenon. Practical evaluations through orbital analysis, numerical simulations, and practical implementations further substantiate the efficacy and performance of the proposed system. This study contributes to the advancement of chaotic and hyperchaotic systems, particularly those with dimensions exceeding 5D, offering insights into synchronization techniques and practical applications in engineering and other scientific disciplines.

A review of physical heat dissipation methods for 3D integrated technology

Three-dimensional integrated circuits have higher integration than two-dimensional integrated circuits, and can obtain higher performance and lower power consumption in a certain space. In order to fulfill higher efficiency, thermal management becomes particularly important in 3D integration technology. However, the traditional heat dissipation method cannot satisfy the heat dissipation needs of three-dimensional integrated circuits, which require better heat dissipation methods to be developed. This paper introduces the realization of three-dimensional integrated circuit using silicon via (TSV) technology, which allows the chip to be vertically stacked to transmit information. This paper summarizes the research methods and findings of three-dimensional integrated circuit heat dissipation in recent years, including thermal through silicon via (TTSV) and microchannel cooling. It also emphasizes the advantages and disadvantages of both mehods, and the challenges faced in current research via an overview. The future research trend for both heat dissipation methods mainly consists of combining special algorithms to achieve thermal-electrical codesign and thermal management of three-dimensional integrated circuits.

Realistic Cost to Execute Practical Quantum Circuits using Direct Clifford+T Lattice Surgery Compilation

We report a resource estimation pipeline that explicitly compiles quantum circuits expressed using the Clifford+T gate set into a surface code lattice surgery instruction set. The cadence of magic state requests from the compiled circuit enables the optimization of magic state distillation and storage requirements in a post-hoc analysis. To compile logical circuits into lattice surgery operations, we build upon the open-source Lattice Surgery Compiler. The revised compiler operates in two stages: the first translates logical gates into an abstract, layout-independent instruction set; the second compiles these into local lattice surgery instructions that are allocated to hardware tiles according to a specified resource layout. The second stage retains logical parallelism while avoiding resource contention in the fault-tolerant layer, aiding realism. Additionally, users can specify dedicated tiles at which magic states are replenished, enabling resource costs from the logical computation to be considered independently from magic state distillation and storage. We demonstrate the applicability of our pipeline to large, practical quantum circuits by providing resource estimates for the ground state estimation of molecules. We find that variable magic state consumption rates in real circuits can cause the resource costs of magic state storage to dominate unless production is varied to suit.

A Novel Battery-Supplied AFE EEG Circuit Capable of Muscle Movement Artifact Suppression

In this study, the fundamentals of electroencephalography signals, their categorization into frequency sub-bands, the circuitry used for their acquisition, and the impact of noise interference on signal acquisition are examined. Additionally, design specifications for medical-grade and research-grade EEG circuits and a comprehensive analysis of various analog front-end architectures for electroencephalograph (EEG) circuit design are presented. Three distinct selected case studies are examined in terms of comparative evaluation with generic EEG circuit design templates. Moreover, a novel one-channel battery-supplied EEG analog front-end circuit designed to address the requirements of usage protocols containing strong compound muscle movements is introduced. Furthermore, a realistic input signal generator circuit is proposed that models the human body and the electromagnetic interference from its surroundings. Experimental simulations are conducted in 50 Hz and 60 Hz electrical grid environments to evaluate the performance of the novel design. The results demonstrate the efficacy of the proposed system, particularly in terms of bandwidth, portability, Common Mode Rejection Ratio, gain, suppression of muscle movement artifacts, electrostatic discharge and leakage current protection. Conclusively, the novel design is cost-effective and suitable for both commercial and research single-channel EEG applications. It can be easily incorporated in Brain–Computer Interfaces and neurofeedback training systems.

Frequency Shift in Microwave Circuits Manufactured with Circuit Board Plotters: Case Study of a Parallel Coupled Lines Filter

Board milling is one of the most widespread methods for manufacturing printed circuit boards from low frequencies to the microwave and millimeter wave range. In this contribution, the detrimental effect of defects typical of printed circuit board plotters has been investigated. In detail, a systematic frequency shift in the circuit performance has been observed both in terms of S21 and S11 parameters. The performance degradation has been analyzed and attributed to the inaccurate milling depth, which is typical of many plotters, particularly for less recent models. After the conductor removal step, the unwanted milling of dielectric material changes the electrical properties of the microstrip structure, in turn affecting the circuit performance. This circumstance has been investigated by means of electromagnetic simulations performed on the real case study of a parallel coupled lines filter. Therefore, a filter prototype has been realized and measured to confirm the simulated results. This study can be beneficial to those professionals involved in the design and realization of microwave and millimeter waves circuits with board milling machines.

Robustness and evolvability: Revisited, redefined and applied

Building on and extending existing definitions of robustness and evolvability, we propose and utilize new formal definitions, with matching measures, of robustness and evolvability of systems with genotypes and corresponding phenotypes. We explain and show how these measures are more general and more representative of the concepts they stand for, than the commonly used/referenced measures originally proposed by Wagner. Further, a versatile digital modeling approach (BNK) is proposed that is inspired by NK systems. However, unlike NK systems, BNK incorporates a genotype and a phenotype, in addition to fitness. We develop and apply an Evolutionary Algorithm to a BNK-modeled system to find different types of perfect oscillators. We then map the resulting oscillating systems to possible genetic circuit realizations. Continuing with the synthetic biology theme, we also investigate the effect of noise in DNA synthesis on the predicted functionality of a DNA-based biosensor (i.e., its robustness), and we carry out a theoretical assessment of the evolvability of different types of ribozymes, undergoing directed evolution.

Machine learning based feedforward voltage control for buck converters in envelope tracking applications

Tracking the voltage envelope of 5G base station power supplies poses a significant long-term challenge. To achieve fast and accurate envelope tracking, an efficient and high-frequency power electronics circuit and an excellent voltage controller are essential. This paper presents a novel machine learning (ML) based feedforward control method for precise voltage reference tracking. The method is exemplified using a standard buck converter in both continuous conduction mode (CCM) and discontinuous conduction mode (DCM). A feedforward neural network (FNN) is trained to capture non-ideal and non-linear effects in real circuits. An automated data collection system, developed with MATLAB and Simulink, facilitates data acquisition and model training process. The trained FNN predicts the duty cycle for the buck converter to generate the targeted output voltage and output power. A simulation model is built to validate the effectiveness of the FNN controller in envelope tracking applications.

Parity-Frequency-Space Elastic Spin Control of Wave Routing in Topological Phononic Circuits.

Topological phononic cavities, such as ring resonators with topological whispering gallery modes (TWGMs), offer a flexible platform for the realization of robust phononic circuits. However, the chiral mechanism governing TWGMs and their selective routing in integrated phononic circuits remain unclear. This work reveals, both experimentally and theoretically, that at a phononic topological interface, the elastic spin texture is intricately linked to, and can be explained through a knowledge of, the phonon eigenmodes inside each unit cell. Furthermore, for paired, counterpropagating TWGMs based on such interfaces in a waveguide resonator, this study demonstrates that the elastic spin exhibits locking at discrete frequencies. Backed up by theory, experiments on kHz TWGMs in thin honeycomb-lattice aluminum plates bored with clover-leaf shaped holes show that together with this spin-texture related angular-momentum locking mechanism at a single topological interface, there are triplicate parity-frequency-space selective wave routing mechanisms. In the future, these mechanisms can be harnessed for the versatile manipulation of elastic-spin based routing in phononic topological insulators.

Enhanced Performance of P-Channel CuIBr Thin-Film Transistor by ITO Surface Charge-Transfer Doping.

The process development and optimization of p-type semiconductors and p-channel thin-film transistors (TFTs) are essential for the development of high-performance circuits. In this study, the Br-doped CuI (CuIBr) TFTs are proposed by the solution process to control copper vacancy generation and suppress excess holes formation in p-type CuI films and improve current modulation capabilities for CuI TFTs. The CuIBr films exhibit a uniform surface morphology and good crystalline quality. The on/off current (ION/IOFF) ratio of CuIBr TFTs increased from 103 to 106 with an increase in the Br doping ratio from 0 to 15%. Furthermore, the performance and operational stability of CuIBr TFTs are significantly enhanced by indium tin oxide (ITO) surface charge-transfer doping. The results obtained from the first-principles calculations well explain the electron-doping effect of ITO overlayer in CuIBr TFT. Eventually, the CuIBr TFT with 15% Br content exhibits a high ION/IOFF ratio of 3 × 106 and a high hole field-effect mobility (μFE) of 7.0 cm2 V-1 s-1. The band-like charge transport in CuIBr TFT is confirmed by the temperature-dependent measurement. This study paves the way for the realization of transparent complementary circuits and wearable electronics.

Q-Map: quantum circuit implementation of boolean functions

Quantum computing has gained attention in recent years due to the significant progress in quantum computing technology. Today many companies like IBM, Google and Microsoft have developed quantum computers and simulators for research and commercial use. The development of quantum techniques and algorithms is essential to exploit the full power of quantum computers. In this paper we propose a simple visual technique (we call Q-Map) for quantum realization of classical Boolean logic circuits. The proposed method utilizes concepts from Boolean algebra to produce a quantum circuit with minimal number of quantum gates.

Stemless InSb nanowire networks and nanoflakes grown on InP

Among the experimental realization of fault-tolerant topological circuits are interconnecting nanowires with minimal disorder. Out-of-plane indium antimonide (InSb) nanowire networks formed by merging are potential candidates. Yet, their growth requires a foreign material stem usually made of InP–InAs. This stem imposes limitations, which include restricting the size of the nanowire network, inducing disorder through grain boundaries and impurity incorporation. Here, we omit the stem allowing for the growth of stemless InSb nanowire networks on an InP substrate. To enable the growth without the stem, we show that a preconditioning step using arsine (AsH3) is required before InSb growth. High-yield of stemless nanowire growth is achieved by patterning the substrate with a selective-area mask with nanohole cavities, containing restricted gold droplets from which nanowires originate. Interestingly, these nanowires are bent, posing challenges for the synthesis of interconnecting nanowire networks due to merging failure. We attribute this bending to the non-homogeneous incorporation of arsenic impurities in the InSb nanowires and the interposed lattice-mismatch. By tuning the growth parameters, we can mitigate the bending, yielding large and single crystalline InSb nanowire networks and nanoflakes. The improved size and crystal quality of these nanostructures broaden the potential of this technique for fabricating advanced quantum devices.