Voltage Readout Research Articles

Multifunctional In-Memory Logics Based on a Dual-Gate Antiambipolar Transistor toward Non-von Neumann Computing Architecture.

In-memory computing may make it possible to realize non-von Neumann computing because the logic circuits are unified in the memory units. We investigated two types of in-memory logic operations, namely, two-input logic circuits and multifunctional artificial synapses. These were realized in a dual-gate antiambipolar transistor (AAT) with a ReS2/WSe2 heterojunction, in which polystyrene with a zinc phthalocyanine core (ZnPc-PS4) was incorporated as a memory layer. Here, reconfigurability is a key concept for both types of device operations and was achieved by merging the Λ-shaped transfer curve of the AAT and the nonvolatile memory effect of ZnPc-PS4. First, we achieved electrically reconfigurable two-input logic circuits. Versatile logic circuits such as AND, OR, NAND, NOR, and XOR circuits were demonstrated by taking advantage of the Λ-shaped transfer curve of the dual-gate AAT. Importantly, the nonvolatile memory function provided the electrical switching of the individual circuits between AND/OR, NAND/NOR, and XOR/NAND circuits with constant input signals. Second, the memory effect was applied to multifunctional artificial synapses. The inhibitory/excitatory and long-term potentiation/depression synaptic operations were electrically reconfigured simply by controlling one parameter (readout voltage), making three distinct responses possible even with the same presynaptic signals. These findings provide hints that may lead to the realization of new in-memory computing architectures beyond the current von Neumann computers.

A low noise capacitance to voltage readout circuit based on active feedback charge sensitive amplifier for micro-gyro.

Trans-impedance amplifier (TIA) based capacitance-voltage (C-V) readout circuits are widely used in micro-machined gyroscopes' control system. In this work, the noise performance of a TIA and charge sensitive amplifier (CSA) based C-V readout circuit is analyzed in detail. The theoretical derivation and simulation experiments carried out in this paper show that the thermal noise of high value feedback resistors in TIA dominates the output noise of the circuit, while a CSA-based readout circuit can overcome this shortcoming. Then, a CSA-based C-V readout circuit is designed with a 1.8V transistor on a 180nm complementary metal-oxide-semiconductor. This C-V-based readout circuit occupies an area of 0.039 mm2, which is smaller than the area of a 0603 package resistor. When 1V bias voltage (Vb) is added to the capacitors under test, the tested C-V gain of this circuit is as high as 225 dB, and the tested output noise of the circuit is less than 150 nV/Hz. Finally, the fabricated chip achieved a resolution of 840 zF/Hz at Vb as low as 1V. This CSA-based C-V readout circuit has more advantages in terms of noise and area over the TIA circuit and is more suitable for integration into the interface integrated circuit for micro-gyroscopes.

An area‐effective and low‐power single‐slope ADC for DCG imaging CMOS image sensor

SummaryThis paper introduces an area‐effective and low‐power readout circuit structure tailored for high dynamic range (HDR) CMOS image sensors (CISs) utilizing dual conversion gain (DCG) imaging technology. A switched capacitor amplifier, which is applied at the comparator input port of the column‐parallel single‐slope analog‐to‐digital converter (SS ADC), is proposed to compensate for the charge injection and clock feed‐through introduced when the pixel switches between high conversion gain (HCG) and low conversion gain (LCG) modes. The proposed SS ADC is supplemented by the integration of a configurable counter, and the counter is specifically crafted for performing the A/D conversion of the readout voltage within a DCG pixel. Compared to the conventional DCG readout circuit, the proposed readout circuit use only one ADC for A/D conversion of HCG signals and LCG signals, which greatly reduces the area and power consumption of the readout circuit. Simulation results under 110 nm CMOS technology illustrate that the proposed 10‐bit SS ADC has a DNL of +0.78/−0.91 LSB and an INL of +1.91/−1.69 LSB, with a SNR of 57.2 dB and a SNDR of 55.95 dB, corresponding to an ENOB of 9 bits. The power consumption of the proposed SS ADC is 56.4 μW per column with a conversion time of 12 μs, and the simulation results show that the power consumption is 23.35% lower than the conventional structure and the area is saved by 24.69%.

Two-Terminal Perovskite Optoelectronic Synapse for Rapid Trained Neuromorphic Computation with High Accuracy.

Emerging neural morphological vision sensors inspired by biological systems that integrate image perception, memory, and information computing are expected to transform the landscape of machine vision and artificial intelligence. However, stable and reconfigurable light-induced synaptic behavior always relies on independent gateport modulation. Despite its potential, the limitations of uncontrollable defects and ionic characteristics have led to simpler, smaller, and more integration-friendly two-terminal devices being used as sidelines. In this work, the synergy between ion migration barriers and readout voltage is proven to be the key to realizing stable, reconfigurable, and precisely controllable postsynaptic current in two-terminal devices. Following the same mechanism, optical and electrical signal synchronous triggering is proposed to serve as a preprocessing method to achieve a recognition accuracy of 96.5%. Impressively, the gradual ion accumulation during the training process induces photocurrent evolution, serving as a reference for the dynamic learning rate and boosting accuracy to 97.8% in just 10 epochs. The PSC modulation potential under short optical pulse of 20 ns is also revealed. This optoelectronic device with perception, memory, and computation capabilities can promote the development of new devices for future photonic neural morphological circuits and artificial vision.

Compressive sensing of functional connectivity maps from patterned optogenetic stimulation of neuronal ensembles

Mapping functional connectivity between neurons is an essential step toward probing the neural computations mediating behavior. Accurately determining synaptic connectivity maps in populations of neurons is challenging in terms of yield, accuracy, and experimental time. Here, we developed a compressive sensing approach to reconstruct synaptic connectivity maps based on random two-photon cell-targeted optogenetic stimulation and membrane voltage readout of many putative postsynaptic neurons. Using a biophysical network model of interconnected populations of excitatory and inhibitory neurons, we characterized mapping recall and precision as a function of network observability, sparsity, number of neurons stimulated, off-target stimulation, synaptic reliability, propagation latency, and network topology. We found that mapping can be achieved with far fewer measurements than the standard pairwise sequential approach, with network sparsity and synaptic reliability serving as primary determinants of the performance. Our results suggest a rapid and efficient method to reconstruct functional connectivity of sparsely connected neuronal networks.

A capacitance sensing method with trans-impedance based readout circuit and adaptive filtering for micro-gyro

Trans-impedance amplifier (TIA) based capacitance–voltage (C–V) readout circuit is an attractive choice for micro-machined gyroscope for its simplicity and superior performance. In this work, the noise and the C–V gain characteristics of the TIA circuit are analyzed in detail. Then, a TIA based readout circuit with a C–V gain of about 286 dB is designed, and a series of experiments are conducted to test the performance of the circuit. Both the analysis and test results show that T-network TIA should be avoided as far as possible for its poor noise performance. All results also show that there is a signal-to-noise ratio (SNR) limit for the TIA based readout circuit, and the SNR can only be further improved by filtering. Hence, an adaptive finite impulse response filter is designed to further improve the SNR of the sensed signal. For a gyroscope with a peak-to-peak variable capacitance of about 200 aF, a SNR of 22.8 dB can be achieved by the designed circuit and a SNR of 47 dB can be obtained by further adaptive filtering. Finally, the solution presented in this paper achieves a capacitive sensing resolution of 0.9 aF.

A Potentiometric Uric Acid Biosensor Integrated With Temperature Correction Readout Circuit on Flexible PCB

This study presents the enzymatic potentiometric uric acid sensor with a temperature correction circuit, sensor set readout, and integration on a flexible printed circuit board (FPCB). Coupled with the uric acid sensor calibrated by the temperature sensor, the readout voltage can respond directly to the sensed uric acid value. Complete circuits are surface mounted on commercial electroless nickel immersion gold FPCBs. Such a miniaturized potentiometric sensor provides the shortest signal path to reduce measurement errors and noise interference. The voltage-time measurement system used to measure the sensing characteristics of the potentiometric uric acid sensor is also analyzed. In addition to high linearity and repeatability, the sensor has an average sensitivity of 19.65 mV/(mg/dL), and the error caused by temperature changes is reduced by 81% after temperature correction.

Radiation-Tolerant Thin-Film Electrodes for pH Monitoring in Sterile Media.

Thin-film pH electrodes on thermoplastic substrates can be subjected to γ-radiation (up to 45 kGy) without loss of stability or sensing performance, with important ramifications for monitoring analytes in sterile environments. pH-sensing membranes composed of polyvinyl chloride (PVC), trioctyl trimellitate (TOTM), and a standard hydrogen ionophore were cast onto screen-printed carbon electrodes with exfoliated graphene as a solid contact. Irradiated thin-film electrodes were conditioned in phosphate buffers and monitored for up to 3 months for changes in voltage readout and pH sensitivity, relative to untreated controls. The sensitivities of both irradiated and control electrodes were consistently Nernstian over a 100 day window, with both types exhibiting logarithmic voltage decays but in opposite directions. The γ-irradiated electrodes had excellent long-term stability with quasi-linear voltage drifts of +0.28 mV (∼0.005 pH) per day. Voltage readouts from sterilized thin-film electrodes in cell culture media could be converted by single-point calibration into pH values that fell within 0.07 units relative to a commercial pH meter (calibrated daily).

Enhancement of Sensitivity in AlGaN/GaN HEMT Based Sensor Using Back-Barrier Technique

In the state of the art, most of the Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) based sensors provide current readout rather than voltage readout. Further, to improve the sensitivity, surface side optimization has been done rather than epi-layer optimization. In this paper, a back-barrier (epi-layer) technique is proposed to improve the sensitivity of the GaN based sensor. To measure the sensitivity, voltage readout is used as it provides better sensitivity than that of a current readout. SILVACO ATLAS Technology Computer Aided Design (TCAD) is used to analyze the performance of the proposed technique. In order to perform a realistic simulation, the TCAD simulation is validated with measured data. The proposed back-barrier technique in the GaN HEMT is shown to improve the sensitivity by 14% as compared to the state of the art. Therefore, the use of the proposed back-barrier technique is considered promising for the GaN HEMT based sensors.

Perovskite-Based Memristor with 50-Fold Switchable Photosensitivity for In-Sensor Computing Neural Network.

In-sensor computing can simultaneously output image information and recognition results through in-situ visual signal processing, which can greatly improve the efficiency of machine vision. However, in-sensor computing is challenging due to the requirement to controllably adjust the sensor’s photosensitivity. Herein, it is demonstrated a ternary cationic halide Cs0.05FA0.81MA0.14 Pb(I0.85Br0.15)3 (CsFAMA) perovskite, whose External quantum efficiency (EQE) value is above 80% in the entire visible region (400–750 nm), and peak responsibility value at 750 nm reaches 0.45 A/W. In addition, the device can achieve a 50-fold enhancement of the photoresponsibility under the same illumination by adjusting the internal ion migration and readout voltage. A proof-of-concept visually enhanced neural network system is demonstrated through the switchable photosensitivity of the perovskite sensor array, which can simultaneously optimize imaging and recognition results and improve object recognition accuracy by 17% in low-light environments.

Flexible Pressure Sensor Array with Multi-Channel Wireless Readout Chip.

Flexible sensor arrays are widely used for wearable physiological signal recording applications. A high density sensor array requires the signal readout to be compatible with multiple channels. This paper presents a highly-integrated remote health monitoring system integrating a flexible pressure sensor array with a multi-channel wireless readout chip. The custom-designed chip features 64 voltage readout channels, a power management unit, and a wireless transceiver. The whole chip fabricated in a 65 nm complementary metal-oxide-semiconductor (CMOS) process occupies 3.7 × 3.7 mm2, and the core blocks consume 2.3 mW from a 1 V supply in the wireless recording mode. The proposed multi-channel system is validated by measuring the ballistocardiogram (BCG) and pulse wave, which paves the way for future portable remote human physiological signals monitoring devices.

Implementation of correlated double sampling circuit on glass applied for active pixel sensing array

AbstractWith the gradual popularization of Internet of Things (IoT) and automation related technologies as well as the rapid development of biometric technology, the application requirements for image sensors have also increased. The improvement of the accuracy of the sensing results has always been a project that people continue to study and optimize. The characteristic of the thin film transistor (TFT), which is often used in active pixel sensor (APS), is likely been affected by temperature and the error during fabrication process, thereby affecting the sensing accuracy. The threshold voltage (Vth) variation is one of the most influential factors among all non‐ideal effect. Correlated double sampling (CDS) is a commonly used technique in eliminating the characteristic variation. In this paper, we proposed a novel CDS circuit composed of TFTs and capacitors which can be integrated on substrate with simulation and implementation. The advantage of the circuit is that Vth variation is eliminated and readout voltage dynamic range is adjusted to fit the operation region of IC at the same time.

A Monolithic CMOS-MEMS Reconfigurable/Tunable Capacitive Accelerometer with Integrated Sensing Circuits

MEMS accelerometers have been widely used in various applications with a wide range of signal levels and bandwidth. Therefore it is desired to have a sensor whose characteristics such as sensitivity and bandwidth can be reconfigured/tuned depending on specific applications. This paper presents a reconfigurable/tunable z-axis accelerometer whose mechanical resonant frequency, sensitivity and sensing bandwidth can be tuned by the electrostatic spring softening effect. The proposed accelerometer was designed using a commercial 0.35 μm CMOS foundry service. The tuning electrodes were implemented in the metal and polysilicon layers in the standard CMOS process. An on-chip chopper stabilized readout circuit was designed to convert the capacitance signal to a voltage readout. The sensing structure was released by post-CMOS wet metal etching. Measurement results showed the proposed accelerometer had a sensitivity of 12 mV/g in the range of 0–5 g. The sensitivity and bandwidth tuning ranges are 50% and 18%, respectively, for an applied tuning voltage of 25 V. The demonstrated device is the first reconfigurable/tunable CMOS-MEMS accelerometer in the literature to our best knowledge.

Flexible memory device based on polymer ferroelectric with zinc oxide single-nanowire transistors for robust multilevel operation

We demonstrate a flexible ferroelectric polymer-based memory with a zinc oxide (ZnO) single-nanowire transistor; its enhanced memory properties are attributed to the limited size of the semiconducting single-nanowire, which suppresses leakage currents caused by parasitic capacitance. Memory devices based on hybrid ferroelectric field-effect transistors (Fe-FETs) exhibit an outstanding data retention time, with an on/off ratio of ∼107 for 104 s along with a highly stable endurance for 100 cycles, without drain current degradation at a readout voltage of 0.1 V. Furthermore, these enhanced characteristics lead to a robust performance, overcoming the changes in the hysteresis window caused by flexoelectricity under bending stress; thus, the flexible-polymer Fe-FET with a ZnO single-nanowire channel shows a multilevel switching behavior with three different drain current states under bending conditions.

Coastal buoy data acquisition and telemetry system for monitoring oceanographic and meteorological variables in the Gulf of Mexico

This paper presents a data acquisition and telemetry system designed and built to monitor oceanographic and meteorological parameters. A voltage regulator and readout module was designed for the reading of data from a set of dedicated commercial sensors and to continuously monitor the voltage level of the power supply. In order to monitor the measured parameters and the status of the buoy remotely, a data string was transmitted every hour using an Iridium satellite transceiver. The described system was implemented and tested in four coastal oceanographic buoys that were deployed and operated in remote sites in the Gulf of Mexico (GoM) for several months in 2016. The data recorded by the buoys is used to describe the oceanographic and meteorological conditions at each site. The system proved to be reliable for long-term monitoring at offshore sites, requiring only minor corrective maintenance during their operation in the field.

P‐69: Correlated Double Sampling Circuit Integrated on Glass Used for Active Pixel Sensing Array

In recent years, promoting the sensing accuracy of the image pixel sensor has become a hot issue. For voltage type active pixel sensor (V‐APS), the readout voltage, as well as the sensing signal, will be affected by the thin film transistors (TFTs) characteristic variation, especially the shift in threshold voltage (Vth). In this paper, we introduce a novel correlated double sampling (CDS) circuit, which can be implemented on glass by only using TFTs and capacitors. Thus, the readout voltage variation due to the threshold voltage shift under same light intensity illumination can be eliminated.

Design Optimization of Instrumented Strikers for Charpy V-Notch Pendulum Impact Testing

Abstract The Charpy impact test was originally devised to measure the amount of energy absorbed by a material during fracture. Instrumentation of the striker extended the scope of this inexpensive dynamic test significantly. By not only recording the absorbed energy but also the force applied to the specimen as a function of time, additional information about the material’s properties is obtainable. At the present day, however, no internationally accepted procedure to calibrate or verify the measured dynamic force exists. From an engineering viewpoint, an instrumented striker for which a static force calibration is sufficient to accurately measure the force applied to the specimen during a Charpy impact test would be ideal. To investigate if such an instrumented striker can be designed, the influence of the striker geometry, the location of the strain gauges, and the static force calibration procedure on the force measured by an instrumented International Organization for Standardization striker is assessed using finite element analysis. It is demonstrated that when the strain gauge bridge on the striker is sensitive to the load distribution at the striking edge, the voltage response for the Charpy impact test deviates from the static force calibration curve, and the conversion of the voltage readout to force values introduces an error in the force value and hence a discrepancy between computed and angle-based energies. A striker with a height of 12 mm and strain gauges positioned at 17 mm from the striking edge is nearly insensitive to the load distribution, and a static force calibration is sufficient to accurately measure the force during an impact test.

Large Hall Signal due to Electrical Switching of an Antiferromagnetic Weyl Semimetal State

Developing a technology to electrically manipulate a Weyl semimetal state is a vital step for designing a nonvolatile memory using topologically robust properties. Recently, such manipulation is realized for the first time in the antiferromagnetic Weyl semimetal Mn3Sn using the readout signal of anomalous Hall effect in the Mn3Sn/heavy metal (Pt, W) heterostructures. Here, it is reported that the switching of Hall signal can be significantly enhanced by 1) removing the buffer layer of Ru to adjust the crystal orientation of Mn3Sn, and 2) annealing after deposition of the heavy metal to change the interfacial condition. The switching of the Hall resistance is 0.35 Ω in the Mn3Sn/W sample, which becomes one order of magnitude larger than the previously reported value using Ru/Mn3Sn/Pt heterostructures. Moreover, by increasing the read current, it is found that the readout voltage may go well beyond 1 mV, a milestone for future applications in memory technology.

A compact time-to-amplitude converter for single-photon time-of-flight measurement

This work proposes a compact time-to-amplitude converter (TAC) for single-photon time-of-flight (TOF) measurement. Based on the principle of current mirror integration, the regulated cascode output structure is used to improve the integration linearity. Fabricated in 180 nm standard CMOS technology, the test results show that the proposed TAC achieves an integral nonlinearity of less than 1.1 LSB, and a timing resolution of 78 ps in a full-scale range (FSR) of 20 ns. Moreover, the readout voltage only varies by 1% during 1 ms hold-off time. The simple circuit structure make TAC occupy a small area of 120 µm2 and consume low dynamic power of 36.8 µW. The TOF measurement error is less than 5.2 cm, and the measurement precision is up to 1.61 cm at 150 cm. The presented TAC provides a compact implementation solution to realize high-density TOF sensors.

Origin of the retention loss in ferroelectric Hf0.5Zr0.5O2-based memory devices

For the decade, ferroelectric hafnium oxide films are attracting the interest as a promising functional material for nonvolatile ferroelectric random access memory due to full scalability and complementary metal-oxide-semiconductor integratability. Despite the significant progress in key performance parameters, particularly, the readout charge and voltage as well as the endurance, the developed devices can only be implemented by the electronics industry if they exhibit a standard retention time of 10 years. Material engineering modifies not only target ferroelectric properties, but also the retention time. To understand how to maintain the sufficient retention, the physical mechanism behind it should be clarified. For this purpose, we have fabricated the capacitor memory cell with a high rate of retention loss. Comparing the device performance with the results of capacitance transient spectroscopy, operando hard X-ray photoelectron spectroscopy and in situ piezoresponse force microscopy, we have concluded that the retention loss is caused by the accumulation of the positively charged oxygen vacancies at the interfaces with capacitor electrodes. The redistribution of charges during long-term storage of information is fully defined by the domain structure in memory cell.