Readout Of Silicon Strip Detectors Research Articles

FSDR16—Fast and Low Noise Multichannel ASIC With 5th Order Complex Shaping Amplifier

We report on the design and measurements of a multichannel ASIC FSDR16 prototype implemented in UMC 180 nm CMOS technology and dedicated for the readout of silicon strip detectors. The FSDR16 chip contains 16 channels with the size of 60 μm × 880 μm each, which are built with: charge sensitive amplifier, pole-zero cancellation circuit, 5th order complex shaper based on the follow-the-leader architecture and 7-bit trim DAC. To achieve low noise performance and high speed analog signal processing, the proper signal shaping has to be involved in order to obtain voltage pulse which is as symmetrical and short as possible at the shaper output. The functionality of the chip allows to make a comparison between a typical CR-(RC)5 shaper based on real poles and a complex semi-Gaussian shaper based on complex poles. We present both, the design procedure of such filters and the measurements results with the emphasis on the spread of analog front-end parameters of these architectures in the multichannel system. The FSDR16 chip characterizes low power dissipation Pdiss = 3.5 mW per single channel. The peaking time tp measured from 1% to the peak of complex semi-Gaussian shaper is set to 75 ns (fast mode) or 180 ns (slow mode). Its architecture allows to obtain a shorter pulse width tw (t w/tp = 2.85) measured form 1% to 1% of the curve than in case of a typical CR-(RC) 5 shaper (tw/t p = 3.54). The front-end electronics has been optimized for detector capacitance of CDET = 30 pF and for fast mode of complex semi-Gaussian shaper an equivalent noise charge ENC = 172 e- +26.2 e- /pF, while for slow mode ENC = 139 e-+18.9 e-/pF.

Test results of a self-triggering silicon strip detector readout chip

The n-XYter integrated circuit (ASIC) was designed in a CMOS 0.35 μm technology, as a 128-channel, data-driven silicon detector readout chip and became a prototype readout chip for several experiments at the Facility for Antiproton and Ion Research (FAIR). The details of the circuit architecture have already been published [C. Schmidt, et al., in: Proceedings of the Topical Workshop on Electronics for Particle Physics, Prague, Czech Republic, 03–07 September 2007; A. Brogna, et al., Nucl. Instr. and Meth. A 568 (2006) 301]. In this paper we present test results on discriminator threshold spread and its correction, analogue front-end gain measurements and calibration of the time-stamp circuitry. The measurements were performed using on-chip test pulses. The ASIC was connected to a 1 cm long, 100 μm pitch, AC-coupled silicon strip detector (SSD).

Low-noise multichannel ASIC for high count rate X-ray diffractometry applications

RG64 is a 64-channel ASIC designed for the silicon strip detector readout and optimized for high count rate X-ray imaging applications. In this paper we report on the test results referring to the RG64 noise level, channel uniformity and the operation with a high rate of input signals. The parameters of the RG64-based diffractometry system are compared with the ones based on the scintillation counter. Diffractometry measurement results with silicon strip detectors of different strip lengths and strip pitch are also presented.

Readout of silicon strip detectors with position and timing information

Low-noise front-end amplifiers for silicon strip detectors are already available for decades, providing excellent signal-to-noise ratio and thus very precise spatial resolution, but at the cost of a long shaping time in the microsecond range. Due to occupancy and pile-up issues, modern experiments need much faster electronics. With submicron ASICs, adequate readout and data processing, it is possible to obtain not only spatial hit data, but also accurate timing information—a feature which is rarely exploited so far. We present the concept of a silicon vertex detector readout system intended for an upgrade of the Belle experiment at KEK (Tsukuba, Japan). The APV25 front-end chip, originally developed for CMS at CERN, is used in a way where it delivers multiple samples along the shaped waveform, such that not only the analog pulse height, but also the timing of each particle hit can be determined. We developed a complete readout system including an FADC + Processor VME module which performs zero-suppression in FPGAs. The hit time measurement is also planned on the same module. As fast amplifiers are inherently more susceptible to noise, which largely depends on the load capacitance, the front-end chips should be located as close to the detector as possible. On the other hand, the material budget, especially in a low-energy electron–positron machine such as Belle, should be minimized. We tried to merge those demands with a fully functional “Flex_Module”, where thinned APV25 readout chips are mounted on the silicon sensor.

Design and performance of the ABCD3TA ASIC for readout of silicon strip detectors in the ATLAS semiconductor tracker

The ABCD3TA is a 128-channel ASIC with binary architecture for the readout of silicon strip particle detectors in the Semiconductor Tracker of the ATLAS experiment at the Large Hadron Collider (LHC). The chip comprises fast front-end and amplitude discriminator circuits using bipolar devices, a binary pipeline for first level trigger latency, a second level derandomising buffer and data compression circuitry based on CMOS devices. It has been designed and fabricated in a BiCMOS radiation resistant process. Extensive testing of the ABCD3TA chips assembled into detector modules show that the design meets the specifications and maintains the required performance after irradiation up to a total ionising dose of 10 Mrad and a 1-MeV neutron equivalent fluence of 2×10 14 n/cm 2, corresponding to 10 years of operation of the LHC at its design luminosity. Wafer screening and quality assurance procedures have been developed and implemented in large volume production to ensure that the chips assembled into modules meet the rigorous acceptance criteria.

Integrated readout of silicon strip detectors for position sensitive measurement of X-rays

The paper presents an ASIC (Application Specific Integrated Circuit) dedicated for readout of silicon strip detectors used for position sensitive measurements of X-rays. Requirements concerning the silicon strip detectors and the readout electronics with respect to X-ray detection are discussed briefly. Design of the ASIC and performance of the developed silicon strip detector module are presented. Application of silicon strip detectors to X-ray powder diffractometry is discussed and examples of diffractometric measurements performed using the developed detector module are presented.

Readout of silicon strip detectors

Various architectural and technological options of readout electronics for silicon strip detectors in vertex and tracking applications are discussed briefly. The ABCD3T ASIC for the readout of silicon strip detectors in the ATLAS semiconductor tracker is presented. The architecture of the chip, some design issues and radiation effects are discussed.

Multichannel mixed-mode IC for digital readout of silicon strip detectors

The design of a mixed mode 64-channel ASIC for digital readout of silicon strip detectors used in X-ray imaging applications is presented. The design is implemented in a 0.8 μm CMOS n-well epi-type substrate technology. The single channel consists of a charge sensitive preamplifier, a shaping amplifier, a discriminator and a pseudo-random 20-bit counter. In addition to the 64-channel core which is responsible for signal processing and data storage, the IC comprises additional blocks like an internal calibration circuit, internal DACs and a command decoder which governs communication of the IC with the external world. Those blocks have been designed keeping in mind testability features and using the chips for building multi-chip modules. The equivalent input noise charge measured at room temperature for a detector capacitance of 2.5 pF and signal integration time of 0.7 μs is 167 e − rms. The average power dissipation is 2.5 mW/channel. The channel-to-channel offset spread referred to the input is only 28 e − rms, while the standard deviation of gain spread is 0.5% of the mean value. The chip occupies area of 2.8×6.5 mm 2.

Design and performance of the ABCD chip for the binary readout of silicon strip detectors in the ATLAS semiconductor tracker

The ABCD design is a single chip implementation of the binary readout architecture for silicon strip detectors in the ATLAS semiconductor tracker. The prototype chip has been manufactured successfully in the DMILL process. In the paper we present the design of the chip and the measurement results. The basic analogue performance of the ABCD design has been evaluated using a prototype SCT module equipped with the ABCD chips. The digital performance has been evaluated using a general purpose IC tester. The measurements confirmed that all blocks of the ABCD design are fully functional and the chips meet all basic requirements of the SCT. Wafer screening has been performed using a customised wafer tester.

Performance of a 128 channel analogue front-end chip for readout of Si strip detector modules for LHC experiments

We present a 128-channel analogue front-end chip, SCT 128A-HC, for readout of silicon strip detectors employed in the inner tracking detectors of the LHC experiment. The chip is produced in the radiation hard DMILL technology. The architecture of the chip and critical design issues are discussed. The performance of the chip has been evaluated in detail in the test bench and is presented in the paper. The chip is used to read out prototype analogue modules compatible in size, functionality and performance with the ATLAS SCT base line modules. Several full size detector modules equipped with SCT128A-HC chips has been built and tested successfully in the lab with /spl beta/ particles as well as in the test beam. The results concerning the signal-to-noise ratio, noise occupancy, efficiency and spatial resolution are presented. The radiation hardness issues are discussed.

SCT128B – a prototype chip for binary readout of silicon strip detectors

We present a 128-channel prototype chip for the binary readout of silicon strip detectors which has been designed and manufactured in the radiation hard DMILL technology. The goal of this development was to demonstrate the feasibility of building in the DMILL technology, a radiation hard chip suitable for the binary readout architecture for the ATLAS SCT. A single chip comprises the front-end circuitry, the binary pipeline and the back end readout circuitry. The architecture as well as the designs of the individual blocks are discussed in the paper. Measurements confirm that full functionality of all blocks of the chip have been achieved at a clock frequency of 40 MHz, meeting the design specification.

Beam tests of lead tungstate crystal matrices and a silicon strip preshower detector for the CMS electromagnetic calorimeter

Further tests of lead tungstate crystal matrices made in high-energy electron beams in 1996, using new crystals, new APDs and an improved test setup confirm that an energy resolution of better than 0.6% at 100 GeV can be obtained when the longitudinal uniformity of the struck crystal is adequate. Light loss measurements under low dose irradiation are reported. It is shown that there is no loss of energy resolution after irradiation and it is demonstrated that the calibration change due to light loss can be tracked with a precision monitoring system. Successful tests with a preshower device, equipped with a silicon strip detector readout, are also described.

Performance of the binary readout of silicon strip detectors using the radiation hard SCT128B chip

We present a prototype binary readout module for the ATLAS Silicon Tracker employing a newly developed readout chip, SCT128B, using the DMILL radiation hard technology [1]. The module design and the basic module components including silicon strip sensors, readout chips and a ceramic hybrid are described briefly. The module performance evaluated in the course of lab test and beam test measurements is reported.

SCTA-a rad-hard BiCMOS analogue readout ASIC for the ATLAS Semiconductor Tracker

Two prototype chips for the analogue readout of silicon strip detectors in the ATLAS Semiconductor Tracker (SCT) have been designed and manufactured, in 32 channels and 128 channel versions, using the radiation hard BiCMOS DMILL process. The SCTA chip comprises three basic blocks: front-end amplifier, analogue pipeline and output multiplexer. The front-end circuit is a fast transresistance amplifier followed by an integrator, providing fast shaping with a peaking time of 25 ns, and an output buffer. The front end output values are sampled at 40 MHz rate and stored in a 112-cell deep analogue pipeline. The delay between the write pointer and trigger pointer is tunable between 2 /spl mu/S and 2.5 /spl mu/s. The chip has been tested successfully and subsequently irradiated up to 10 MraB. Full functionality of all blocks of the chip has been achieved at a clock frequency of 40 MHz both before and after irradiation. Noise figures of ENC=720 e/sup ./+33 e/sup .//pF before irradiation and 840 e/sup ./+33 e/sup .//pF after irradiation have been obtained.

Readout electronics for the ATLAS semiconductor tracker

The binary readout architecture as a base-line and the analogue one as a fall-forward option have been adopted recently by the ATLAS SemiConductor Tracker (SCT) group for the readout of silicon strip detectors. A brief overview of different architectures considered before as well as the status of the binary readout development will be presented. A new idea of the binary readout architecture employing a dual threshold scheme will be discussed and new results obtained for the full analogue readout chip realised in the DMILL technology will be reported.

APV5-RH-a 128 channel analogue pipeline for LHC

A 128 Channel ASIC has been designed for the read-out of silicon strip detectors at the LHC. The circuit is based on the proven concept of slow shaping and stored sample deconvolution. It features a new 40 MHz analogue multiplexer to output all 128 channels through a single connection. The circuit is being fabricated on Harris AVLSIRA radiation hardened technology, which has been demonstrated to meet the environmental requirements of the LHC. >

Fast and low-noise front-end electronics for Si detectors at LHC

Requirements on the front-end electronics for readout of silicon-strip detectors in LHC conditions are discussed. The motivation for the RD20 front-end concept is given and the concept is briefly described. The present status of hardware developments is presented.

Radiation effects on the Viking-2 preamplifier-readout chip

We have studied the radiation sensitivity of the Viking-2 VLSI circuit which has been designed for the readout of silicon strip detectors and manufactured at Mietec in 1.5 μm CMOS technology. Both biased and unbiased chips have been irradiated with a 137Cs γ source up to a total dose of 2 kGy (200 krad) after which all tested chips were still fully functional. We report the characteristic changes of device parameters with dose, including equivalent noise charge for different capacitive loads, and determine transistor threshold shifts and change of mobilities.

Studies of radiation damage to CAMEX64 preamplifiers exposed to γ-rays at the Cornell high energy synchrotron source

CAMEX64 preamplifiers, developed at the MPI-Munich for use in the readout of silicon strip detectors, have been exposed to well-measured doses of monochromatic γ-rays from the Cornell high energy synchrotron source (CHESS) and measurements of the resulting radiation damage have been made. Silicon strip detectors with their associated CAMEXes will be installed close to the interaction region in the CLEO-II experiment at Cornell University, where they will be exposed to both charged particle and photon fluences. Powered and unpowered CAMEXes were irradiated and after each exposure measurements of pedestals, gains, coherent and incoherent noise were made, until the devices could no longer be read out. Results are quoted for noise and gain degradation as a function of dose.

CMOS low noise monolithic frontends for Si strip detector readout

A brief summary of first tests of several monolithic frontend chips is presented. They are designed for readout of silicon strip detectors and have in common that they are all based on the same charge-sensitive preamplifier/shaper configuration, for which the main design goal was the lowest possible noise at low power consumption. Measurements show that low-noise levels of ENC = 165e − + 12e −/pF have been reached.