Capacitive Sensor Readout Circuit Research Articles

Capacitive sensor readout circuit based on sample and hold method

This paper presents a capacitive sensor readout circuit using sample and hold method. The proposed readout circuit is used to convert capacitance from sensor to DC (direct current) voltage output. The basic structure of readout circuit consists of the pulse generator circuit, differentiator circuit, amplifier circuit, monostable I circuit, monostable II circuit, and sample and hold circuit. The proposed technique is based on the change of time constant from differentiator circuit corresponding to the measurement capacitance. The sample and hold circuit is used for sampling output voltage from differentiator circuit. The output voltage of the proposed readout circuit is proportional to measurement capacitance. The standard capacitors with different capacitance are used to test the proposed converter performance. Experimental results show that the proposed readout circuit can convert measurement capacitance to output voltage with satisfied values, good linearity and high sensitivity.

Development of a Real-Time Force and Temperature Sensing System with MEMS-LSI Integrated Tactile Sensors for Next-Generation Robots

This study proposes a sensing system that can sense force and temperature at the same time. The system consists of MEMS-LSI integrated tactile sensor devices called sensor nodes, a field-programmable gate array (FPGA) based relay node, and a host PC. For real-time temperature and force data acquisition, a time-sharing force and temperature task processing mechanism was implemented with a dedicated computer architecture in the FPGA configuration and the host program. This study firstly reports the temperature dependency analysis of a capacitive sensor readout circuit in the sensor node by circuit-level simulation. With a fabricated sensor node, sensor output data were measured and analyzed with varying temperatures and applied force. Based on the measured data, linear multiple regression equations for temperature compensation of sensed force data were developed. In the temperature range of 24.8°C–60°C, the average/maximum force errors when considering the temperature effect were −0.98%/65% without the compensation, and 0.072%/17% with the compensation, respectively. One cycle time of temperature and force sensing for one sensor node was 113 ms on average. The experimental results showed that real-time temperature and force sensing and temperature compensation for accurate force sensing could be achieved successfully. The study also demonstrated the system with hot-coffee cup and finger touch examples.

Wide Input Range Supply Voltage Tolerant Capacitive Sensor Readout Using On-Chip Solar Cell

In this paper, a wide input range supply voltage tolerant capacitive sensor readout circuit using on-chip solar cell is presented. Based on capacitance controlled oscillators (CCOs) for ultra-low voltage/power consumption, the sensor readout circuit is directly powered by the on-chip solar cell to improve the overall system energy efficiency. An extended sensing range with high sensing accuracy is achieved using a two-step successive approximation register (SAR) and delta-sigma ([Formula: see text]) analog-to-digital (A/D) conversion (ADC) scheme. Digital controls are generated on-chip using a customized sub-threshold digital standard cell library. Systematic error analysis and optimization including the finite switch on-resistance, buffer input-dependent delay, and SAR quantization nonlinearity are also outlined. High power supply rejection ratio (PSRR) is ensured by using a pseudo-differential topology with ratiometric readout. The complete sensing system is implemented using a standard 0.18[Formula: see text][Formula: see text]m complementary metal-oxide-semiconductor (CMOS) process. Simulation results show that the readout circuit achieves a wide input range from 1.5[Formula: see text]pF to 6.5[Formula: see text]pF with a worst case PSRR of 0.5% from 0.3[Formula: see text]V to 0.42[Formula: see text]V (0.67% from 0.3[Formula: see text]V to 0.6[Formula: see text]V). With a 3.5[Formula: see text]pF input capacitance and a 0.3[Formula: see text]V supply, the [Formula: see text] stage achieves a resolution of 7.1-bit (corresponding to a capacitance of 2.2[Formula: see text]fF/LSB) with a conversion frequency of 371[Formula: see text]Hz. With an average power consumption of 40[Formula: see text]nW and a sampling frequency of 47.5[Formula: see text]kHz, a figure-of-merit (FoM) of 0.78[Formula: see text]pJ/conv-step is achieved.

A 2.5 mW 370 mV/pF high linearity stray-immune symmetrical readout circuit for capacitive sensors

A stray-insensitive symmetrical capacitance-to-voltage converter for capacitive sensors is presented. By introducing a reference branch, a symmetrical readout circuit is realized. The linear input range is increased, and the systematic offsets of two input op-amps are cancelled. The common-mode noise and even-order distortion are also rejected. A chopper stabilization technique is adopted to further reduce the offset and flicker noise of the op-amps, and a Verilog-A-based varactor is used to model the real variable sensing capacitor. Simulation results show that the output voltage of this proposed readout circuit responds correctly, while the under-test capacitance changes with a frequency of 1 kHz. A metal-insulator-metal capacitor array is designed on chip for measurement, and the measurement results show that this circuit achieves sensitivity of 370 mV/pF, linearity error below 1% and power consumption as low as 2.5 mW. This symmetrical readout circuit can respond to an FPGA controlled sensing capacitor array changed every 1 ms.

An interface circuit for measuring capacitance changes based upon capacitance-to-duty cycle (CDC) converter

We present a direct-to-digital capacitive sensor readout circuit that converts capacitance changes of a sensor element to changes of the duty cycle of a square-wave oscillator, which, in turn, is converted to a digital output by a counter. The readout circuit resembles a single-slope analog-to-digital converter structure. There are several advantages of this readout scheme. First, due to its simplicity and low number of components, the power consumption of the circuit is expected to be significantly smaller than in similar digital readout designs. Furthermore, linearization of the output may be achieved using an EEPROM lookup table. Another advantage is the possibility of performing adaptive measurements where the sensor resolution and bandwidth may be changed via the readout circuit software. Finally, we present a theory of the adaptive measurement and an analysis of the design tradeoffs. The capacitance-to-duty cycle readout circuit may achieve large bandwidth and high resolution in a modern low-voltage, low-power CMOS implementation. The performance of a prototype readout circuit built from discrete components is 13-bit effective resolution with a 1-kHz bandwidth.