Read-write Conflict Research Articles

Scalable Distributed Inverted List Indexes in Disaggregated Memory

Memory disaggregation separates compute (CPU) and main memory resources into disjoint physical units to enable elastic and independent scaling. Connected via high-speed RDMA-enabled networks, compute nodes can directly access remote memory. This setting often requires complex protocols with many network roundtrips as memory nodes have near-zero compute power. In this paper, we design a scalable distributed inverted list index for disaggregated memory architectures. An inverted list index maps a set of terms to lists of documents that contain this term. Current solutions either partition the index horizontally or vertically with severe limitations in the disaggregated memory setting due to data and access skew, high network latency, or out-of-memory errors. Our method partitions lists into fixed-size blocks and spreads them across the memory nodes to balance skewed accesses. Block-based list processing keeps the memory footprint of compute nodes low and masks latency by interleaving remote accesses with expensive list operations. In addition, we propose efficient updates with optimistic concurrency control and read-write conflict detection. Our experiments confirm the efficiency and scalability of our method.

Dodo: A scalable optimistic deterministic concurrency control protocol

Deterministic concurrency control is able to avoid the expensive two-phase commit in distributed databases and can solve the single-thread bottleneck of transaction processing in blockchain systems. Most existing deterministic concurrency control protocols rely on prior knowledge of the transaction’s read-write set, which is impractical in most cases. The state-of-the-art deterministic concurrency control protocols Aria and DOCC break this limitation. However, they do not perform well in multi-node and multi-core scalability.To solve the scalability issues, we propose Dodo, a novel deterministic concurrency control protocol. Dodo processes transactions in multi-batches, and each batch is divided into three phases. In the first phase, transactions are executed as read committed and staged. In the second phase, transactions are validated for the read-write conflict. In the third phase, only the continuous un-conflicted transactions at the head of the batch can be committed. For the aborted transaction that will be rerun in the next batch, we utilize its write set in the previous execution to reduce the read-write conflicts in the next batch. In this way, Dodo has the following benefits. First, Dodo does not rely on the prior knowledge of the read-write set. Second, Dodo commits transactions in pre-determined orders (TIDs) providing high multi-node scalability. Third, Dodo runs transactions in each phase concurrently, and the aborted transactions are re-executed in a conflict-less manner, enabling high multi-core scalability. Besides, we propose two optimism-based improvements, lazy decision and early-write visibility, to reduce aborts and blocking. Our evaluation shows that Dodo outperforms Aria and DOCC by up to 16.5x and 8.0x in a single-node setting and scales well in a multi-node setting.

2D Materials‐Based Static Random‐Access Memory

2D transition-metal dichalcogenide semiconductors, such as MoS2 and WSe2 , with adequate bandgaps are promising channel materials for ultrascaled logic transistors. This scalability study of 2D material (2DM)-based field-effect transistor (FET) and static random-access memory (SRAM) cells analyzing the impact of layer thickness reveals that the monolayer 2DM FET with superior electrostatics is beneficial for its ability to mitigate the read-write conflict in an SRAM cell at scaled technology nodes (1-2.1nm). Moreover, the monolayer 2DM SRAM exhibits lower cell read access time and write time than the bilayer and trilayer 2DM SRAM cells at fixed leakage power. This simulation predicts that the optimization of 2DM SRAM designed with state-of-the-art contact resistance, mobility, and equivalent oxide thickness leads to excellent stability and operation speed at the 1-nm node. Applying the nanosheet (NS) gate-all-around (GAA) structure to 2DM further reduces cell read access time and write time and improves the area density of the SRAM cells, demonstrating a feasible scaling path beyond Si technology using 2DM NSFETs. In addition to the device design, the process challenges for 2DM NSFETs, including the cost-effective stacking of 2DM layers, formation of electrical contacts, suspended 2DM channels, and GAA structures, are also discussed.

Solutions for concurrency conflict problem on Hyperledger Fabric

A Hyperledger Fabric is a popular permissioned blockchain platform and has great commercial application prospects. However, the limited transaction throughput of Hyperledger Fabric hampers its performance, especially when transactions with concurrency conflicts are initiated. In this paper, we focus on transactions with concurrency conflicts and propose solutions to optimize the performance of Hyperledger Fabric. Firstly, we propose a novel method LMLS to improve the Write-Write Conflict. This method introduces a lock mechanism in the transaction flow to enable some conflicting transactions to be marked at the beginning of the transaction process. And indexes are added to conflicting transactions to optimize the storage of the ledger. Secondly, we propose a cache-based method to improve the Read-Write Conflict. The cache is used to speed up reading data, and a cache log is added to Hyperledger Fabric to ensure the data consistency. Extensive experiments demonstrate that the proposed novel methods can significantly increase transaction throughput in the case of concurrency conflicts, and maintain high efficiency in transactions without concurrency conflicts.

SiGe Asymmetric Dual-k Spacer FinFETs-Based 6T SRAM Cell to Mitigate Read-Write Conflict

SiGe Asymmetric Dual-<i>k</i> Spacer FinFETs-Based 6T SRAM Cell to Mitigate Read-Write Conflict

Highly flexible SRAM cells based on novel tri-independent-gate FinFET

In this paper, a novel tri-independent-gate (TIG) FinFET is proposed for highly flexible SRAM cells design. To mitigate the read-write conflict, two kinds of SRAM cells based on TIG FinFETs are designed, and high tradeoff are obtained between read stability and speed. Both cells can offer multi read operations for frequency requirement with single voltage supply. In the first TIG FinFET SRAM cell, the strength of single-fin access transistor (TIG FinFET) can be flexibly adjusted by selecting five different modes to meet the needs of dynamic frequency design. Compared to the previous double-independent-gate (DIG) FinFET SRAM cell, 12.16% shorter read delay can be achieved with only 1.62% read stability decrement. As for the second TIG FinFET SRAM cell, pass-gate feedback technology is applied and double-fin TIG FinFETs are used as access transistors to solve the severe write-ability degradation. Three modes exist to flexibly adjust read speed and stability, and 68.2% larger write margin and 51.7% shorter write delay are achieved at only the expense of 26.2% increase in leakage power, with the same layout area as conventional FinFET SRAM cell.

Ultra-low-leakage, Robust FinFET SRAM Design Using Multiparameter Asymmetric FinFETs

Memory arrays consisting of Static Random Access Memory (SRAM) cells occupy the largest area on chip and are responsible for significant leakage power consumption in modern microprocessors. With the transition from planar Complementary Metal-Oxide-Semiconductor (CMOS) technology to FinFETs, FinFET SRAM design has become important. However, increasing leakage power consumption of FinFETs due to aggressive scaling, width quantization, read-write conflict, and process variations make FinFET SRAM design challenging. In this article, we show how Multiparameter Asymmetric (MPA) FinFETs can be used to design ultra-low-leakage and robust 6T SRAM cells. We combine multiple asymmetries, namely, asymmetry in gate work function, source/drain doping concentration, and gate underlap, to address various SRAM design issues all at once. We propose five novel MPA FinFET SRAM cell designs and compare them with symmetric and Single-Parameter Asymmetric (SPA) FinFET SRAM cells using dc and transient metrics. We show that the leakage current of MPA FinFET SRAM cells can be reduced by up to 58 × while ensuring reasonable read/write stability metric values. In addition, high stability metric values can be achieved with 22 × leakage current reduction compared to the traditional symmetric FinFET SRAM cell. There is no area overhead associated with MPA FinFET SRAM cells.

SI-TM

Transactional memory represents an attractive conceptual model for programming concurrent applications. Unfortunately, high transaction abort rates can cause significant performance degradation. Conventional transactional memory realizations not only pessimistically abort transactions on every read-write conflict but also because of false sharing, cache evictions, TLB misses, page faults and interrupts. Consequently, the use of transactions needs to be restricted to a very small number of operations to achieve predictable performance, thereby, limiting its benefit to programming simplification. In this paper, we investigate snapshot isolation transactional memory in which transactions operate on memory snapshots that always guarantee consistent reads. By exploiting snapshots, an established database model of transactions, transactions can ignore read-write conflicts and only need to abort on write-write conflicts. Our implementation utilizes a memory controller that supports multiversion memory, to efficiently support snapshotting in hardware.We show that snapshot isolation can reduce the number of aborts in some cases by three orders of magnitude and improve performance by up to 20x.

SI-TM

Transactional memory represents an attractive conceptual model for programming concurrent applications. Unfortunately, high transaction abort rates can cause significant performance degradation. Conventional transactional memory realizations not only pessimistically abort transactions on every read-write conflict but also because of false sharing, cache evictions, TLB misses, page faults and interrupts. Consequently, the use of transactions needs to be restricted to a very small number of operations to achieve predictable performance, thereby, limiting its benefit to programming simplification. In this paper, we investigate snapshot isolation transactional memory in which transactions operate on memory snapshots that always guarantee consistent reads. By exploiting snapshots, an established database model of transactions, transactions can ignore read-write conflicts and only need to abort on write-write conflicts. Our implementation utilizes a memory controller that supports multiversion memory, to efficiently support snapshotting in hardware.We show that snapshot isolation can reduce the number of aborts in some cases by three orders of magnitude and improve performance by up to 20x.

Tri-Mode Independent Gate FinFET-Based SRAM With Pass-Gate Feedback: Technology–Circuit Co-Design for Enhanced Cell Stability

We present 6T SRAMs with pass-gate feedback using tri-mode independent gate (TMIG) FinFETs as the access transistors. We perform a comprehensive analysis of TMIG FinFETs and the proposed SRAM cell using our simulation framework, which is based on the non-equilibrium Green's function models for FinFETs. We compare our technique with the tied gate (TG) FinFET SRAM and the previously proposed independent gate (IG) FinFET SRAM with pass-gate feedback. The effects of quantum confinement in scaled FinFETs on the device and SRAM characteristics are analyzed in detail. We show that quantum confinement effects lead to severe degradation in access time and write-ability of the IG FinFET SRAM. On the other hand, the SRAM cell proposed in this paper shows 14% improvement in write-ability over the TG FinFET SRAM with comparable read stability, achieving mitigation of the read-write conflict. At the same time, 30% reduction in standby leakage and comparable hold stability is achieved at no cell area penalty, with only 14% increase in the cell access time. We also show that the array-level issues associated with pass-gate feedback are mitigated using the co-design technique presented in this paper.

(Invited) Spacer Thickness Optimization for FinFET-based Logic and Memories: A Device-Circuit Co-Design Approach

We present device-circuit co-design techniques for FinFETs, based on spacer thickness optimization. We show that short channel effects in deeply scaled technologies can be mitigated by engineering the spacer thickness to introduce a gate underlap. FinFETs with symmetric and asymmetric gate underlap are presented and their device characteristics are analyzed. The implication of introducing underlap in FinFETs on circuit design is also discussed. We show that spacer thickness optimization leads to 86% lower leakage and 14% lower dynamic energy consumption with comparable performance. We also present the benefits of FinFETs with asymmetric gate underlap in mitigating the read-write conflict in 6T SRAMs. This technique enhances the read stability by 10% with only 3% lower write margin compared to standard FinFET SRAM. In addition, 58% reduction in leakage, 3% lower write time and 3% higher hold stability is achieved at the cost of 19% higher access time and 4% larger area.

Asymmetrically Doped FinFETs for Low-Power Robust SRAMs

We propose FinFETs with unequal source and drain doping concentrations [asymmetrically doped (AD) FinFETs] for low-power robust SRAMs. The effect of asymmetric source/drain doping on the device characteristics is extensively analyzed, and the key differences between conventional and AD FinFETs are clearly shown. We show that asymmetry in the device structure leads to unequal currents for positive and negative drain biases, which is exploited to achieve mitigation of read-write conflict in 6T SRAMs. The proposed device exhibits superior short-channel characteristics compared to a conventional FinFET due to reduced electric fields from the terminal that has a lower doping. This results in significantly lower cell leakage in AD-FinFET-based 6T SRAM. Compared to the conventional FinFET-based 6T SRAM, AD-FinFET SRAM shows 5.2%-8.3% improvement in read static noise margin (SNM), 4.1%-10.2% higher write margin, 4.1%-8.8% lower write time, 1.3%-3.5% higher hold SNM, and 2.1-2.5 lower cell leakage at the cost of 20%-23% higher access time. There is no area penalty associated with the proposed technique.

An Intelligent Multi-Port Memory

It has become clear that on-chip storage is critical in large FPGAs. Scholars have done some research es on implementing user logic memory models with single-port and dual-port physical arrays. T heir work is based on the assumption that user memory models are either single-port or dual-port. However, their works may not be helpful to multi-processor applications since single or dual-port arrays may not satisfy the simultaneous accesses from different processors. This paper proposes a novel multi-port memory design . In our design, d istributed memory resources of LUT are mapped as 1-port m emory b anks. Data in different m emory b anks can be accessed simultaneously. With the help of port-priority and r/w-priority, our multi-port memory can resolve both write-write conflict and read-write conflict. When write-write conflict occurs, the port with the highest priority can execute its write operation . W hen read-write conflict occurs, either read-then-write or write-then-read type is selected according to r/w-priority. Besides, data-switch paths between ports are implemented by utilizing the read-write conflict. Extend Port Importance Hierarchy (EPIH) algorithm is proposed for basic conflict handling, while Block Access Control (BAC) algorithm is proposed for reducing conflict when processors carry block read/write. Experiment results on Xilinx Virtex-II show that: compared to implementation of N ports in each cell, our design saves 88% LUT resources. Experiment results on Xilinx Virtex-II also show that, as port number N increases, the cell cost increases significantly which restricts the reasonable port number to rather small values in practice . Experiment results on simulation show that BAC algorithm performs more efficiently according to increasing block read/write length.

Cautious transaction schedulers with admission control

We propose a new class of schedulers, called cautious schedulers , that grant an input request if it will not necessitate any rollback in the future. In particular, we investigate cautious WRW-schedulers that output schedules in class WRW only. Class WRW consists of all schedules that are serializable, while preserving the write-read and read-write conflict, and is the largest polynomially recognizable subclass of serializable schedules currently known. It is shown, in this paper however, that cautious WRW- scheduling is, in general, NP-complete. Therefore, we introduce a special type ( type 1R ) of transaction, which consists of no more than one read step (an indivisible set of read operations) followed by multiple write steps. It is shown that cautious WRW-scheduling can be performed efficiently if all transactions are of type 1R and if admission control can be exercised. Admission control rejects a transaction unless its first request is immediately grantable.