An Intelligent Multi-Port Memory

Abstract

It has become clear that on-chip storage is critical in large FPGAs. Scholars have done some research es on implementing user logic memory models with single-port and dual-port physical arrays. T heir work is based on the assumption that user memory models are either single-port or dual-port. However, their works may not be helpful to multi-processor applications since single or dual-port arrays may not satisfy the simultaneous accesses from different processors. This paper proposes a novel multi-port memory design . In our design, d istributed memory resources of LUT are mapped as 1-port m emory b anks. Data in different m emory b anks can be accessed simultaneously. With the help of port-priority and r/w-priority, our multi-port memory can resolve both write-write conflict and read-write conflict. When write-write conflict occurs, the port with the highest priority can execute its write operation . W hen read-write conflict occurs, either read-then-write or write-then-read type is selected according to r/w-priority. Besides, data-switch paths between ports are implemented by utilizing the read-write conflict. Extend Port Importance Hierarchy (EPIH) algorithm is proposed for basic conflict handling, while Block Access Control (BAC) algorithm is proposed for reducing conflict when processors carry block read/write. Experiment results on Xilinx Virtex-II show that: compared to implementation of N ports in each cell, our design saves 88% LUT resources. Experiment results on Xilinx Virtex-II also show that, as port number N increases, the cell cost increases significantly which restricts the reasonable port number to rather small values in practice . Experiment results on simulation show that BAC algorithm performs more efficiently according to increasing block read/write length.