Read Operation Research Articles

Design of a Single-Ended-Write Schmitt-Trigger Based 10T SRAM Cell

Technology scaling is done in order to accommodate more and more transistors in today’s high performance VLSI circuits. These high-performance digital circuits demand large capacity of memory to accomplish faithful operations. However, at scaled technology, SRAM-cell stability is a major issue of concern. Also, increased integration density of these VLSI circuits causes increased power consumption. Leakage power in today’s VLSI circuits has become comparable to dynamic power consumption which also needs to be addressed. In this work, a Schmitt-trigger (ST) based 10T SRAM cell with single-ended-writing and differentially-read feature is proposed. The proposed cell offers enhanced stability and dissipates lower leakage power. Due to separate ports for writing and reading in the proposed cell, the conflict design requirement (which is a condition in conventional 6T cell) is eliminated. Schmitt-trigger based inverters in the proposed cell causes increased threshold voltage of the inverters resulting in enhanced cell stability during read operation. Simulation is carried out on TSPICE using a 65nm Predictive Technology Model (PTM). Results show that the proposed 10T cell provides a 1.7x larger Read static noise margin (RSNM) than the conventional 6T cell. Proposed 10T cell provides Write static noise margin (WSNM) of 155mV during write ‘0’ while 150mV during write ‘1’ operation, respectively, at 0.4V. At a supply voltage of 0.4V, the proposed 10T cell consumes 0.71x lesser static power as compared to that of a conventional 6T cell. However, proposed cell uses more transistors (10 transistors) as compared to that of the conventional 6T cell, therefore, our cell occupies large chip-area as compared to the conventional 6T cell.

Adaptative Zero‐Bit Pattern Scheme for Reducing Energy Consumption of Non‐Volatile Memories

The main hindrances to employing non‐volatile memory (NVM) to the embedded system are the extra energy consumption and long latency of switching states of NVM cells. To mitigate these drawbacks, several schemes have been studied based on the read‐before‐write scheme (RBW), which reduces the number of write operations by skipping writing bits that are the same in the existing values and new values. Thus, they compare all bits before updating the data. However, these studies also need extra read operations for every write operation. To address this problem, a zero‐bit pattern scheme is proposed that skips accessing bit cells determined as zero‐bits. In addition, the granularity of the zero‐bit pattern is dynamically adjusted depending on the pattern of the non‐leading zeroes. The results of the experiments show that dynamic energy is reduced by 43.5% with 4.7% storage overhead. © 2022 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.

Analysis of read speed latency in 6T‐SRAM cell using multi‐layered graphene nanoribbon and cu based nano‐interconnects for high performance memory circuit design

AbstractIn this study, we designed a 6T‐SRAM cell using 16‐nm CMOS process and analyzed the performance in terms of read‐speed latency. The temperature‐dependent Cu and multilayered graphene nanoribbon (MLGNR)‐based nano‐interconnect materials is used throughout the circuit (primarily bit/bit‐bars [red lines] and word lines [write lines]). Here, the read speed analysis is performed with four different chip operating temperatures (150K, 250K, 350K, and 450K) using both Cu and graphene nanoribbon (GNR) nano‐interconnects with different interconnect lengths (from 10 μm to 100 μm), for reading‐0 and reading‐1 operations. To execute the reading operation, the CMOS technology, that is, the16‐nm PTM‐HPC model, and the16‐nm interconnect technology, that is, ITRS‐13, are used in this application. The complete design is simulated using TSPICE simulation tools (by Mentor Graphics). The read speed latency increases rapidly as interconnect length increases for both Cu and GNR interconnects. However, the Cu interconnect has three to six times more latency than the GNR. In addition, we observe that the reading speed latency for the GNR interconnect is ~10.29 ns for wide temperature variations (150K to 450K), whereas the reading speed latency for the Cu interconnect varies between ~32 ns and 65 ns for the same temperature ranges. The above analysis is useful for the design of next generation, high‐speed memories using different nano‐interconnect materials.

Testing of AMBA AXI Protocol

The rapidly expanding VLSI sector has a great need for a very robust verification mechanism that can be developed in a short amount of time in the constantly changing environment where new intellectual property and chips are being designed every day having reduced time-to-market. (SoC) System on Chip design emerged as a primary integrated technique for reducing the design time of the entire system with the introduction of a standardized signal bus architecture used for the connectivity of different modules of the system. One of the major difficulties at hand is how to check these on chip bus protocols, since traditional old methods are ineffective in certifying large SoCs. In this paper, we have verified AMBA AXI protocol which shows write as well as read operations using System Verilog. Keywords: AMBA AXI, APB, AHB.

Inner Product Computation In-Memory Using Distributed Arithmetic

In-memory computing using emerging technologies such as Resistive Random-Access Memory (ReRAM) has been proposed as a promising substitute for future computing applications to address the ‘von Neumann bottleneck’. Multiplication is the key component for inner product computation in every digital signal processing (DSP) application and the complexity of multipliers increases greatly with bit-width. Distributed arithmetic (DA) using look-up tables and adder-shifter module has been proposed for inner product computation to achieve multiplier-less efficient DSP architectures, particularly when one of the vectors is a constant and known in advance. Due to the memory wall, DA can be made furthermore latency and energy-efficient when implemented ‘in memory’. In this work, for the first time, we propose two design techniques to compute inner product completely in memory using DA. This is accomplished by storing the precomputed look-up table contents in a ReRAM array and implementing adder-shifter module also in the same array. The adder-shifter is implemented in memory using majority gates which are in turn realized as READ operations in the memory array. Two methods of mapping: latency-optimized and area-optimized and their comparison in terms of latency and area are presented. The proposed method-1 achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\approx 60$ </tex-math></inline-formula> % energy savings compared to CMOS and the proposed method-2 achieves 10.59 times higher throughput compared to CMOS.

A Low-Power High-Speed Sensing Scheme for Single-Ended SRAM

In this paper, a reference-voltage self-selected pseudo-differential sensing scheme suitable for single-ended SRAM is proposed. The proposed sensing scheme can select different reference voltage according to the offset direction. With the employment of the new sensing scheme, the swing of the read bit-line in the read operation is reduced by 74.6% and 45.5% compared to the conventional domino and the pseudo-differential sense amplifier sensing scheme, respectively. Therefore, the delay and power consumption of the read operation are significantly improved. Simulation results based on a standard 55nm CMOS show that compared with the conventional domino and pseudo-differential sensing schemes, the sensing delay is improved by 66.4% and 47.7%, and the power consumption is improved by 31.4% and 22.5%, respectively. Although the area of the sensing scheme is increased by 50.8% compared with the pseudo-differential sense amplifier sensing scheme, it has little effect on the entire SRAM area.

Robustly Stable Ferroelectric Polarization States Enable Long-Term Nonvolatile Storage against Radiation in HfO2-Based Ferroelectric Field-Effect Transistors.

The ferroelectric field-effect transistors (FeFETs) with HfO2-based ferroelectric layers in the gate stacks are emerging as one of the most promising candidates for the next-generation nonvolatile memory devices due to their scalability and compatibility with conventional Si technology. Moreover, owing to the high radiation hardness of the HfO2-based ferroelectric thin films, HfO2-based FeFETs have attracted great interest in the fields of radiation-hard (rad-hard) memory. However, the reliability of their memory states under irradiation, which represents the validity of the stored information, has not been investigated. Here, we focus on the impact of the total ionizing dose (TID) on erased and programmed states of HfO2-based FeFETs. The TID radiation (X-ray) characteristics of erased and programmed HfO2-based FeFETs are characterized using an on-site read operation. Both the erased and programmed states show robust stability under irradiation at a dose rate of 90 rad(Si)/s, and even at 230 rad(Si)/s, only the erased state shows a slight variation. The possible factors contributing to memory state degradation are discussed. Through the analysis of the threshold voltage shift and subthreshold swing evolution, as well as studies of ferroelectric polarization stability under radiation, it is revealed that the erased state degradation is caused by oxide-trapped charges rather than interface degradation or polarization switching. The physical mechanism of the difference in radiation-induced oxide-trapped charges buildup in programmed and erased FeFETs is analyzed to explain different TID radiation characteristics between them. Our work suggests that the HfO2-based FeFETs have great potential in radiation environment applications.

Nesne-İlişkisel Eşleme (ORM) Araçlarının .NET 6 Ortamında Performans Analizi

ORM tools are frequently used in projects developed by object-oriented programming paradigm. Software developers generally look at the performances of these tools when they select an ORM tool. Most of the performance studies on ORM tools are limited to processing time and RAM usage information, and CPU usage information is not included. Moreover, no ORM performance study has been found in the literature, conducted in .NET 6, which is an open-source and platform-independent new generation .NET platform. In this study, to close the mentioned gap in the literature and guide the software developers, we conduct research for analyzing performances of certain ORM tools in .NET 6. Our study includes CPU usage information as well as processing time and RAM usage information. We develop a software for measuring processing time, RAM and CPU usage while performing read, insert, update, delete, search and sort operations with Dapper, NHibernate and Entity Framework Core (EF Core) ORM tools. As a result, while Dapper is best in terms of processing time for read, delete, search and sort operations, EF Core has the best results for insert and update operations. We conclude that Dapper has the best performance in terms of resource usage, while the rankings of EF Core and NHibernate vary among themselves according to the number of records and operation type.

Low Power Static Random-Access Memory Cell Design for Mobile Opportunistic Networks Sensor Nodes

In the present scenario, the devices supporting neighbor discovery are going through the renovation phase, and crossing the classical barrier such as the trade-off between power dissipation and access time. The presence of opportunistic nodes in place of static nodes has presented multiple challenges for such devices. Therefore, the focus of neighbor discovery has mostly shifted toward such issues where power dissipation and latency of mobile nodes need to be simultaneously improved to achieve uninterrupted and quality communication. Since static random-access memory (SRAM) is an integral part of all such sensor nodes and directly impacts power dissipation and latency, therefore in this paper, we have introduced a novel SRAM cell for such nodes. The proposed eleven transistors (11T) SRAM cell is compared with six recently reported designs to check the improvement of SRAM key design parameters. The compared designs include Standard 6T (S6T), tunable 8T(TU8T), PPN-based 10T (PN10T), Schmitt trigger-based 10T (S10T), bit-line-dependent 11T (DP11T) bit-cell and stable low power 11T (SP11T). The improvement in write ability and read stability of proposed 11T cell is represented by [Formula: see text] and [Formula: see text] enhancement of write and read static margins, respectively, in comparison to S6T/TU8T/PN10T/S10T/DP11T/SP11T. Further, the leakage power dissipation is reduced by [Formula: see text] as compared to S6T/TU8T/S10T/PN10T/DP 11T/SP11T. Additionally, power dissipation and delay of proposed 11T cell during read operation is reduced by [Formula: see text] and [Formula: see text], respectively, as compared to S6T/TU8T/PN10T/S10T/DP11T/SP11T. It is worth mentioning here that the proposed 11T also shows narrower variability in power dissipation and current values during read operation comparing S6T. The proposed 11T design successfully mitigates the half-select issue and allows the SRAM array to attain the bit-interleaved architecture implementation.

An Artificial Neuron with a Leaky Fin‐Shaped Field‐Effect Transistor for a Highly Scalable Capacitive Neural Network

A capacitive neural network with a capacitive crossbar array that can replace a traditional resistive crossbar array can drastically lower static power consumption during reading operations because a capacitor consumes only dynamic power. Herein, a leaky fin‐shaped field‐effect transistor (L‐FinFET) neuron is fabricated and then applied for use in a highly scalable capacitive neural network with leaky integrate‐and‐fire (LIF) operations that are attributed to a leaky charge trap layer in a gate stack. An additional circuit such as a voltage‐to‐current converter (V–I converter) is no longer required when the L‐FinFET is applied to the capacitive neural network, as the L‐FinFET can directly accept a voltage signal from capacitive synapses. Furthermore, a reset circuit is not necessary given the ability to spontaneously restore to the initial state owing to the leaky charge trap layer. A highly scalable capacitive neural network is realizable due to the size‐reduction ability of the L‐FinFET and the simplified circuit. Finally, an entirely hardware‐based capacitive neural network with the L‐FinFET is demonstrated for the recognition of a simple pattern.

A Review of Cell Operation Algorithm for 3D NAND Flash Memory

The size of the memory market is expected to continue to expand due to the digital transformation triggered by the fourth industrial revolution. Among various types of memory, NAND flash memory has established itself as a major data storage medium based on excellent cell characteristics and manufacturability; as such, the demand for increasing the bit density and the performance has been rapidly increasing. In this paper, we will review the device operation algorithm and techniques to improve the cell characteristics and reliability in terms of optimization of individual program, read and erase operation, and system level performance.

Literacy and Numeracy in Children on Autism Spectrum Disorder

ObjectivesThe variability in patterns of acquisition of literacy and numeracy skills in young children with autism spectrum disorder (ASD) is currently not well understood. In the present study, we investigated these skills in cognitively able children with ASD ages 7–12 years.MethodsUsing independent samples t test, we compared autistic children’s scores on word reading, spelling, and numerical operations with those of typically developing children in the same age group. A paired-samples t test was used to assess whether reading, spelling, and numerical operations scores were comparable within the ASD group. Finally, we tested whether verbal IQ mediated the effect of diagnostic status on these scores.ResultsThe main findings of the study are that autistic children had worse scores on numerical operations than the control group (t(54.112) = − 3.326, p = .002, d = − .314), but the groups’ scores were similar in word reading and spelling. The autistic children had significantly better scores on word reading and spelling than on numerical operations. All scores of autistic children were positively associated with their verbal IQ scores. Verbal IQ mediated the effect of diagnostic status on all outcome variables.ConclusionThese findings extend current understanding of patterns of acquisition of literacy and numeracy skills in young children with ASD, suggesting a critical role of verbal abilities in the acquisition of numerical skills.

An adaptive read/write optimized algorithm for Ceph heterogeneous systems via performance prediction and multi-attribute decision making

The advent of the Big Data era has brought considerable challenges to storing and managing massive data. Moreover, distributed storage systems are critical to the pressure and storage capacity costs. The Ceph cloud storage system only selects data storage nodes based on node storage capacity. This node selection method results in load imbalance and limited storage scenarios in heterogeneous storage systems. Therefore, we add node heterogeneity, network state, and node load as performance weights to the CRUSH algorithm and optimize the performance of the Ceph system by improving load balancing. We designed a cloud storage system model based on Software Defined Network (SDN) technology. This system model can avoid the tedious configuration and significant measurement overhead required to obtain network status in traditional network architecture. Then we propose adaptive read and write optimization algorithms based on SDN technology. The Object Storage Device (OSD) is initially classified based on the Node Heterogeneous Resource Classification Strategy. Then the SDN technology is used to obtain network and load conditions in real-time and an OSD performance prediction model is built to obtain weights for performance impact factors. Finally, a mathematical model is proposed for multi-attribute decision making in conjunction with the OSD state and its prediction model. Furthermore, this model is addressed to optimize read and write performance adaptively. Compared with the original Ceph system, TOPSIS_PA improves the performance of reading operations by 36%; TOPSIS_CW and TOPSIS_PACW algorithms improve the elastic read performance by 23 to 60% and 36 to 85%, and the elastic write performance by 180 to 468% and 188 to 611%, respectively.

A 40-nm Embedded SG-MONOS Flash Macro for High-End MCU Achieving 200-MHz Random Read Operation and 7.91-Mb/mm2 Density With Charge-Assisted Offset Cancellation Sense Amplifier

With the expansion of Internet of Things (IoT) by artificial intelligence (AI), there is a strong demand for higher performance, higher intelligence, and lower cost in endpoint devices for crossover area located at the boundary between high-end micro controller unit (MCU) area and low-end micro processor unit (MPU) area, such as home automation, machine vision, robotics, and so on. This article presents a 40-nm embedded split-gate MONOS (SG-MONOS) flash macro with optimized memory array architecture and charge-assisted offset cancellation sense amplifier (CAOC-SA), which achieve high-speed random read operation of 200 MHz and high density of 7.91 Mb/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> suitable for crossover devices.

Highly Accurate Visual Method of Mars Terrain Classification for Rovers Based on Novel Image Features.

It is important for Mars exploration rovers to achieve autonomous and safe mobility over rough terrain. Terrain classification can help rovers to select a safe terrain to traverse and avoid sinking and/or damaging the vehicle. Mars terrains are often classified using visual methods. However, the accuracy of terrain classification has been less than 90% in read operations. A high-accuracy vision-based method for Mars terrain classification is presented in this paper. By analyzing Mars terrain characteristics, novel image features, including multiscale gray gradient-grade features, multiscale edges strength-grade features, multiscale frequency-domain mean amplitude features, multiscale spectrum symmetry features, and multiscale spectrum amplitude-moment features, are proposed that are specifically targeted for terrain classification. Three classifiers, K-nearest neighbor (KNN), support vector machine (SVM), and random forests (RF), are adopted to classify the terrain using the proposed features. The Mars image dataset MSLNet that was collected by the Mars Science Laboratory (MSL, Curiosity) rover is used to conduct terrain classification experiments. The resolution of Mars images in the dataset is 256 × 256. Experimental results indicate that the RF classifies Mars terrain at the highest level of accuracy of 94.66%.

Local bit-line shared pass-gate 8T SRAM based energy efficient and reliable In-Memory Computing architecture

The In-Memory Computing (IMC) architecture based on Conventional 6T, 8T, and 10T SRAM suffers from compute disturbance, compute-failure, and half-select issues, which affect the reliability of In-Memory Boolean Computation (IMBC) operations. To overcome these problems, local bit-line Shared pass-gate Dual-Port 8T (SDP8T) SRAM-based IMC architecture is proposed to perform energy-efficient IMBC operations. The local bit-line shared pass-gate structure addresses the half select issues with a small area overhead and achieves higher array efficiency by incorporating the bit-interleave architecture. The virtual-VSS write-assist is used in SDP8T SRAM to improve the write-margin yield (μ−3σ) by 48.99%, and multi-VTH technique improves Decoupled Read-Margin (DRM) yield by 5.26% when compared to DP8T SRAM. The Dynamical Reset Word Line (DRWL) scheme is proposed to resolve the sneak current problem and make the proposed IMC architecture more resilient to compute disturbance at non-read decouple paths during IMBC operations. Further, the Reference-based Reconfigurable Sense Amplifier (RRCSA) scheme is proposed to achieve reliable (compute-failure free) sensing for IMBC on four operands simultaneously in a single cycle, normal read, and Binary Content Addressable Memory (BCAM) operations. The 4 Kb SRAM array is implemented in 65-nm CMOS technology to analyze the SDP8T-IMC architecture. The operating frequency of 1190 MHz and average-energy consumption of 18.56 fJ/bit are achieved during IMBC operation at 1V. For BCAM operations, it achieves 0.60 fJ/search/bit energy consumption in the worst case (i.e., all data mismatch) at 1V. Cumulatively, the proposed SDP8T-IMC architecture has the highest figure of merits than the recently reported IMC architecture.

New Insights Into Memory Window of Ferroelectric FET Impacted by Read Operations With Awareness of Polarization Switching Dynamics

In this article, the impacts of read operation under transient gate voltage sweep on the memory window (MW) of ferroelectric field-effect transistor (FeFET) are systematically investigated. By taking into consideration the polarization switching dynamics, it reveals a significant dependence on the sweep range and rate of gate voltage. With increasing sweep range, the increase of polarization switching leads to the monotonically increasing MW. However, different from sweep range, the MW of FeFET nonmonotonically varies with the increasing sweep rate, which is caused by the competition between decreased polarization switching and increased voltage drop on ferroelectric (FE) layer during forward sweep. Besides, compared with the MW obtained by pulsed gate voltage, it is found that the MW obtained by swept gate voltage can be the smaller one even without the consideration of charge trapping contribution. Furthermore, the impacts of FE switching time on MW are also discussed, indicating that the MW may not always be a constant even under quasi-static sweeping with low sweep rate, and the relationship between sweep rate of gate voltage and switching speed of FE plays a critical role in MW evaluation.

Design and Analysis of SRAM Cell for Smart Application

In today's circuittechnology, power consumption and savings are key concerns. The driving reasonsbehind these innovations are portable devices that require high throughput andlow power dissipation, such as computers, phones, and Personal DigitalAssistants (PDAs). In portable devices, reducing or decreasing IC dissipatedpower through design optimization is a big problem, and restricted batterylifespan places very severe restrictions on overall power usage. In this study SRAMcircuit for smart applications has been investigated using various factors suchas write, read, dynamic, static power with voltage and temperature. The powerconsumption analysis is the most essential criteria for memory design. Becausedata stability is a critical concern, affecting both the read and write operations.The implemented 9T SRAM in this study is more efficient than the other SRAM interms of power usage. When compared with the existing SRAM circuits taken forcomparison of different parameters, the proposed 9T SRAM, circuit uses lessthan 28.2% write power, while it uses about the same for read operation. Thedata retention voltage for both circuits is 0.29 V, which is utilized to storethe data in the circuit. The 32 nm Bulk CMOS process technology from PTM filesis used for designing and analysis.

Leakage-Current-Canceling Current-Sampling Sense Amplifier for Deep Submicrometer STT-RAM

In the design of nonvolatile memory (NVM), the sense amplifier (SA) contributes a major part of the power consumption due to high-frequency read operations. This brief proposes a leakage-current-canceling current-sampling sense amplifier (LCCS-SA) for the suppression of the read power consumption by operating in near-threshold region. The proposed LCCS-SA adopts the technology of offset cancellation and single-ended differential circuit structure to compensate the effect of the leakage current. The bit-line (BL) leakage-induced read failure is effectively suppressed in near-threshold region. Monte Carlo simulation demonstrates that the proposed LCCS-SA can operate at a supply voltage of 0.4 V and achieves 4.4 times lower read energy per bit compared to the conventional current-sampling-based SA.

Recoverable mutual exclusion with abortability

Recent advances in non-volatile main memory (NVM) technology have spurred research on algorithms that are resilient to intermittent failures that cause processes to crash and subsequently restart. In this paper we present a Recoverable Mutual Exclusion (RME) algorithm that supports abortability. Our algorithm guarantees FCFS and a strong liveness property: processes do not starve even in runs consisting of infinitely many crashes, provided that a process crashes at most a finite number of times in each of its attempts. On DSM and Relaxed-CC multiprocessors, a process incurs O(min (k, log n)) RMRs in a passage and O(f+ min (k, log n)) RMRs in an attempt, where n is the number of processes that the algorithm is designed for, k is the point contention of the passage or the attempt, and f is the number of times that p crashes during the attempt. On a Strict CC multiprocessor, the passage and attempt complexities are O(n) and O(f+n), respectively. Our algorithm uses only the read, write, and CAS operations, which are commonly supported by multiprocessors. Attiya, Hendler, and Woelfel proved that, with any mutual exclusion algorithm, a process incurs at least varOmega (log n) RMRs in a passage, if the algorithm uses only the read, write, and CAS operations (in: Proc. of the Fortieth ACM Symposium on Theory of Computing, New York, NY, USA, 2008). This lower bound implies that the worst-case RMR complexity of our algorithm is optimal for the DSM and Relaxed CC multiprocessors. This paper is an expanded version of our conference paper as reported by Jayanti and Joshi (in: Atig and Schwarzmann (eds) Networked Systems. Springer International Publishing, Cham, 2019), which presented the first Recoverable Mutual Exclusion (RME) algorithm that supports abortability. This algorithm from our conference paper (in: Atig and Schwarzmann (eds) Networked Systems. Springer International Publishing, Cham, 2019) admits starvation when there are infinitely many aborts in a run. In this paper, we fix this shortcoming and prove the algorithm’s properties by identifying an inductive invariant.