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A Novel 3D 2TnC FeRAM Architecture and Operation Scheme with Improved Disturbance for High-Bit-Density Dynamic Random-Access Memory

In this paper, we proposed the development of stackable 3D ferroelectric random-access memory (FeRAM), with two select transistors and n capacitors (2TnC), to address scaling limitations for bit density growth and the complicated manufacturing of 3D dynamic random-access memory (DRAM). The proposed 3D FeRAM has a 3D NAND-like architecture, with stacked metal–ferroelectric–metal (MFM) capacitors serving as memory cells in a unit string. A similar manufacturing process is used to achieve a cost-effective process and high bit density for next-generation DRAM applications. The two access transistors, string–select–line (SSL) and ground–select–line (GSL), are perfect string selections. We confirmed that the grounded back gate (GBG) of the proposed architecture can significantly improve the worst disturbance case compared to a floating back gate (FBG) like the 1TnC structure. Also, we confirmed the feasibility of performing the random-access operation during the read operation regardless of the data pattern of the selected string.

Speed-Dedup: A New Deduplication Framework for Enhanced Performance and Reduced Overhead in Scale-Out Storage

Conventional deduplication systems face critical challenges such as excessive write amplification, high read/write latency, and sub-optimal storage utilization. These limitations often undermine the performance benefits of deduplication by slowing down I/O acknowledgements due to amplified deduplication I/Os, excessive data chunk replication, and strict consistency requirements. To address these issues, we present Speed-Dedup, a novel deduplication framework that employs a deduplicated primary–semi-deduplicated replica object approach. This strategy reduces write amplification by restricting deduplication to the primary object while maintaining a semi-deduplicated replica object used for immediate read/write acknowledgements, thus enhancing I/O latency and storage efficiency. Speed-Dedup also replaces traditional strong consistency models with eventual consistency, allowing for non-blocking read operations and improving overall system throughput. Experimental results demonstrate that Speed-Dedup significantly outperforms traditional methods like GRATE and CAO, showing up to 21% improvement in I/O performance under low deduplication ratios and maintaining 14% or more gains under higher ratios. Additionally, write amplification is substantially reduced and latency improves by over 100% with faster recovery times during system failures. These findings highlight the effectiveness of Speed-Dedup as a scalable and efficient solution.

Sequentialized Virtual File System: A Virtual File System Enabling Address Sequentialization for Flash-Based Solid State Drives

Solid-state drives (SSDs) are widely adopted in mobile devices, desktop PCs, and data centers since they offer higher throughput, lower latency, and lower power consumption to modern computing systems and applications compared with hard disk drives (HDDs). However, the performance of the SSDs can be degraded depending on the I/O access pattern due to the unique characteristics of SSDs. For example, random I/O operation degrades the SSD performance since it reduces the spatial locality and induces garbage collection (GC) overhead. In this paper, we present an address reshaping scheme in a virtual file system (VFS) called sVFS for improving performance and easy deployment. To do this, it first sequentializes a random access pattern in the VFS layer which is an abstract layer on top of a more concrete file system. Thus, our scheme is independent and easily deployed on any concrete file systems, block layer configuration (e.g., RAID), and devices. Second, we adopt a mapping table for managing sequentialized addresses, which guarantees correct read operations. Third, we support transaction processing for updating the mapping table to avoid sacrificing the consistency. We implement our scheme at the VFS layer in Linux kernel 5.15.34. The evaluation results show that our scheme improve the random write throughput by up to 27%, 36%, 34%, and 2.35× using the microbenchmark and 25%, 22%, 20%, and 3.51× using the macrobenchmark compared with the existing scheme in the case of EXT4, F2FS, XFS, and BTRFS, respectively.

A FinFET Based Low-Power Write Enhanced SRAM Cell With Improved Stability

This work introduces a FinFet based low-power 11T SRAM cell with write enhanced feature, which is considered to meet modern technology requirements due to its distinctive features and performance. The proposed 11T SRAM cell is designed in such a way, so that it reduces the overall power consumption, improving access time, and static noise margin (SNM), especially during the write operation. The proposed 11T SRAM cell is compared with other SRAM cells, including conventional 6T (conv6T), dual pull-up transistor 10T (DPUT10T), dual pull-down transistor 10T (DPDT10T), dual transmission gate 9T (DTG9T), and dual transmission gate 10T (DTG10T), at an equitable standard. The results obtained at the supply voltage of 0.5 V @ 27 °C shows the reduction in leakage power during hold 1 operation by 1.61×/1.33×/1.44×/1.63×/1.46×, and reduction in power consumption during read operation by 1.02×/1.55×/ 1.01×/1.81×/1.97× in comparison with conv6T/DPUT10T/ DPDT10T/DTG9T/DTG10T, respectively. Write access time is also improved by a factor of 1.67×/1.71×/2.59×/1.45×/1.97×, respectively. Additionally, read static noise margin (RSNM) and write static noise margin (WSNM) are improved by 2.03×/1.01×/1.65×/1.54×/1.43×, and 1.42×/1.33×/1.41×/1.02×/1.62×, respectively. This demonstrates why the proposed low-power 11T SRAM cell is desirable, especially when compared to the other cells under consideration.

Novel hybrid TFET-FinFET 12T SRAM cells with enhanced write margin and read performance

This work presents two innovative 12T cells combining tunnel field-effect transistor (TFET) and fin field-effect transistor (FinFET) technologies. These cells address reverse bias current issues by incorporating separate paths for reading data and write enhancement cut transistors, enhancing hold/read/write static noise margin (H/R/WSNM), reducing read time, and minimizing power consumption from TFET leakage. At 0.6 V, the first (second) SRAM cell shows a WSNM improvement over O_7T, 8T, CA_10T, 12T, and HF_10T cells by 152 % (93 %), 152 % (93 %), 157.7 % (97.5 %), 95 % (50 %), and 104 % (57 %), respectively. The leakage power of the first (second) 12T TFET SRAM cell is two (four) orders of magnitude lower than O_7T and 8T SRAM cells. These hybrid SRAM cells also exhibit faster read operations across VDD voltage levels (0.3 V–1 V) and the first 12T cell demonstrates shorter write access times than 12T and CA_10T SRAM cells. These characteristics make the proposed cells particularly suitable for energy-efficient IoT devices and medical applications, where balancing power, area, performance, and data integrity is critical.

Skip index: Supporting efficient inter-block queries and query authentication on the blockchain

Decentralized applications, the driving force behind the new Web3 paradigm, require continuous access to blockchain data. Their adoption, however, is hindered by the constantly increasing size of blockchains and the sequential scan nature of their read operations, which introduce a clear inefficiency bottleneck. Also, the growing amount of data recorded on the blockchain makes resource-constrained light nodes dependent on untrusted full nodes for fetching information, with a consequent need for query authentication protocols ensuring result integrity. Motivated by these reasons, in this paper we propose the skip index, an indexing data structure that allows users to quickly retrieve information simultaneously from multiple blocks of a blockchain. Our solution is also designed to be used as an authenticated data structure to guarantee the integrity of query results for light nodes. We discuss the theoretical properties of skip indices, propose efficient algorithms for their construction and querying, and detail their computational complexity. Finally, we assess the effectiveness of our proposal through an experimental evaluation on the Ethereum blockchain. As a reference use case, we focus on the popular CryptoKitties application and simulate a scenario where users seek to retrieve the events generated by the service. Our experimental results suggest that the use of skip indices offers a constant multiplicative speedup, thanks to search times that are at most logarithmic within a chosen search window. This allows to reduce the number of visited blocks by up to two orders of magnitude if compared to the naive sequential approach currently in use.

Design of 8T DTMOS Schmitt Trigger SRAM Cell for IOT Applications

Abstract Internet of things (IoT) based systems require power-efficient circuits to raise the battery lifeline. This study presents a single-ended 8T SRAM cell. The core of the proposed 8T SRAM cell is composed of a Schmitt-Trigger circuit which a dynamic body bias technique is applied to a standard CMOS inverter through a feedback mechanism, whereby the threshold voltages of two MOSFETs can be changed, thus changing the switching voltage. Read operation of the proposed cell is conducted using the shared footer per word transistor. The write path is cut-off during the read operation, improving RSNM. A transmission gate placed in the cell core is used to cut the feedback path during write operation. To prove superiority of the proposed cell it is compared with four state-of-the-art SRAM cells under identical conditions on Cadence Virtuoso using 45nm technology at VDD=0.8 V. The proposed circuit shows a 135.74 % improvement in terms of RSNM and a 44.04 % improvement in terms of peak-to-peak power compared to the 6T DTMOS Cell.

Near-optimal March Tests for Three-Cell and Four-Cell Coupling Fault Models in Random-Access Memories

This research work addresses the problem of testing n×1 RAMs in which complex models of unlinked static three or four-cell coupling faults are considered. As in other works, it is assumed that only physically neighboring memory cells could be involved in a three or four-cell coupling fault. For this reason, these fault models can also be considered to be of the neighborhood pattern sensitive type. As extensions of the well-known model of all unlinked static two-cell coupling faults, the fault models we address are complex including faults sensitized by a transition write operation as well as faults sensitized by a non-transition write or a read operation. For these complex models, near-optimal multirun march tests are proposed. This optimality assessment is based on the fact that, for any group of cells corresponding to the considered fault model, the state graph is completely covered, and each arc is traversed only once, which means that the graph is of the Eulerian type. Additional write operations are only required for data background changes.

Design of Superlattice Ferroelectric-Metal Field-effect Transistor for triple-level cell 3D NAND flash

Superlattice ferroelectric-metal field-effect transistor (SL-FeMFET) based three-dimensional NAND architecture (3D NAND) is investigated for triple-level cell (TLC) operations. The SL-FeMFET shows a novel approach for designing the gate-stack using a superlattice of ferroelectric/dielectric/ferroelectric for achieving large memory window ∼3.48 V with program/erase voltage ±7 V for 3D NAND architecture. By TCAD modeling, we demonstrate TLC operation of SL-FeMFET with improving memory window and alleviating variability caused by floating metal layer in FeMFET structure. In addition, as the vertical gate stack increases from 256-layer to 512-layer, the read-out current with worst cases in seven read operations for TLC sensing are examined using page buffer circuit for sensing operation. The simulation results suggest that SL-FeMFET based 3D NAND architecture can operate 512-layer with sufficient sense margin for TLC operation.

First demonstration of 2T0C-FeDRAM: a-ITZO FET and double gate a-ITZO/a-IGZO FeFET with a record-long multibit retention time of >4-bit and >2000 s.

Conventional DRAM, consisting of one transistor and one capacitor (1T1C), requires periodic data refresh processes due to its limited retention time and data-destructive read operation. Here, we propose and demonstrate a novel 3D-DRAM memory scheme available with a single transistor and a single ferroelectric field-effect transistor (FeFET) DRAM (2T0C-FeDRAM), which offers extended retention time and non-destructive read operation. This architecture uses a back-end-of-line (BEOL)-compatible amorphous oxide semiconductor (AOS) that is suitable for increasing DRAM cell density. Notably, the device structures of a double gate a-ITZO/a-IGZO FeFET, used for data storage and reading, are engineered to achieve an enlarged memory window (MW) of 1.5 V and a prolonged retention time of 104 s. This is accomplished by a double gate and an a-ITZO/a-IGZO heterostructure channel to enable efficient polarization control in hafnium-zirconium oxide (HZO) layers. We present successful program/erase operations of the double gate a-ITZO/a-IGZO FeFET through incremental step pulse programming (ISPP), demonstrating multi-level states with remarkable retention characteristics. Most importantly, we perform 2T0C-FeDRAM operations by electrically connecting the double gate a-ITZO/a-IGZO FeFET and the a-ITZO FET. Leveraging the impressive performance of the double gate a-ITZO/a-IGZO FeFET technology, we have effectively showcased an exceptionally record-long retention time exceeding 2000 s and 4-bit multi-level states, positioning it as a robust contender among emerging memory solutions in the era of artificial intelligence.

Characterization of high-speed writing and reading operations of the superconducting memory cell

Abstract Superconducting memory cells that use flux quanta as their storage medium can achieve ultra-fast access times with ultra-low power consumption. However, the data signal generated by a flux quantum memory (FQM) cell is usually too weak and too fast to be measured directly. Here, we present a method to characterize the real-time operation of an FQM cell. The storage loop of the FQM cell, configured with a Nb/NbN X /Nb Josephson junction, was proven the capability to store multiple flux quanta. The readout was demonstrated by a superconducting quantum interference device composed of underdamped Nb/Al-AlO X /Nb Josephson junctions. The writing and reading operations were achieved by a short pulse ranging from 0.1 ns to 2.5 ns, and a constant bit error rate of ∼2.46% was measured for the fabricated FQM cell. The method presented here can be used to study real-time operation of an FQM cell in a direct manner.

Design of dual port 9T SRAM cell with parallel processing and high performance computing

Abstract To meet industry requirements of higher transistor count SRAM cells this paper is proposing, a nine-transistor configuration static random access memory (SRAM) cell which is accessible by dual bit line and performing simultaneous read and write operations. The suggested 9T (P9T PS) cell is constructed at 32 nm CMOS and is operating at an operating voltage 0.9 V. To justify the refined performance of proposed design various analysis are carried out that shows the static noise margins (SNM) that occurs while executing the read operation is 0.368 V and hold operation by the cell is 0.364 V, while the write operation has an SNM of 0.422 V. The access time for write and read functions of the cell is found to be 1.2 nS and 4.5 nS respectively. The P9T PS SRAM is compared with other dual-port and single-port 9T SRAM cells is stand out to be pre-eminence in performance in terms of noise immunity, temperature variations, power consumption (static and dynamic both), power delay product (PDP), SNM to PDP and area ratio (SAPR) and electric quality matric. Total leakage power for P9T PS cell is found to be 22.1 nW. The P9T PS bit cell is also found to be power efficient as it is consuming minimal power for all of the operations. Area layout of the P9T (PS) is found to be 22.372 μm2. The results are also supported by the process corner variation analysis for four different corners. LT-spice software is used to carry out all the simulations and analysis.

A memristive-photoconductive transduction methodology for accurately nondestructive memory readout

Crossbar resistive memory architectures enable high-capacity storage and neuromorphic computing, accurate retrieval of the stored information is a prerequisite during read operation. However, conventional electrical readout normally suffer from complicated process, inaccurate and destructive reading due to crosstalk effect from sneak path current. Here we report a memristive-photoconductive transduction (MPT) methodology for precise and nondestructive readout in a memristive crossbar array. The individual devices present dynamic filament form/fuse for resistance modulation under electric stimulation, which leads to photogenerated carrier transport for tunable photoconductive response under subsequently light pulse stimuli. This coherent signal transduction can be used to directly detect the memorized on/off states stored in each cell, and a prototype 4 * 4 crossbar memories has been constructed and validated for the fidelity of crosstalk-free readout in recall process.

Developing a Performance Evaluation Benchmark for Event Sourcing Databases

In the domain of software architecture, Event Sourcing (ES) has emerged as a significant paradigm, especially for systems requiring high levels of auditability, traceability, and intricate state management. Systems such as financial transaction platforms, inventory management systems, customer relationship management (CRM) software, and any application requiring a detailed audit trail can significantly benefit from this approach. Numerous aspects of ES remain unexplored, as they have yet to be thoroughly investigated by scientific research. The unique demands of such systems, particularly in terms of database performance and functionality, are not adequately addressed by existing database benchmarks. By establishing benchmarks, organizations can compare different databases to determine which best meets their needs for applications. This aids in selecting the most appropriate technology based on empirical data rather than assumptions or marketing claims.This paper introduces a novel benchmarking framework specifically designed for evaluating databases in the context of event sourcing. The framework addresses critical aspects unique to ES, including event append performance, efficient handling of Projections (separate databases for read operations), strong consistency, ordered data insertion, and robust versioning controls. Through rigorous testing and analysis, this framework aims to fill the gap in existing database benchmarking tools, providing a more accurate and relevant assessment for ES systems. We also conducted experiments that not only demonstrated the effectiveness of our approach but also yielded meaningful results, substantiating its practicality and applicability.

Subthreshold read operations in 3D PCM: 1S1R device modeling and memory array analysis

3-D phase change memory (PCM) is one of the most promising next-generation nonvolatile memory, and the subthreshold sensing strategy can effectively improve its limited endurance. In this study, we propose a one-selector-one-resistor (1S1R) model with Monte Carlo (MC) function and provide array configurations for the worst case and the maximum bit line voltage (VBL-max), respectively. Based on these, the read window margin (RWM) is evaluated with various array sizes, OTS threshold voltage variations (σvar), and bias voltages (VBias). Our results reveal that the RWM increases as the VBL approaches the VBL-max. Larger arrays lead to an increased leakage current difference, while larger σvar values result in decreased cell current difference and VBL-max. The decrease in VBL-max further deteriorates the RWM. Additionally, we analyze the optimal VBias for 2-deck arrays achieves a 7% reduction in leakage energy consumption and a 22.6% increase in RWM compared to the V/2 bias. The optimal VBias depends on OTS devices and array sizes.

TSDSystem: a framework to collect, archive and share time series data at volcanological observatories

This paper presents a framework designed to collect, archive, and share time series data coming from sensor networks at Istituto Nazionale di Geofisica e Vulcanologia, Osservatorio Etneo (Italy), which we have developed and called Time Series Database management System (TSDSystem). The framework proposes a flexible database model for the standardization of sensor networks data and implements an optimized technology for storage and retrieval of acquired time series data. It is designed for the implementation of multiparametric databases and then suitable for development in volcanological observatories worldwide. The proposed framework provides a web service to perform writing and reading data via a standard web communication protocol, which easily enables interaction with other instruments or automatic systems. All results provided by the TSDSystem web service are represented using common data formats in the context of online services. In particular, the station networks metadata representation follows a schema inspired by the International Federation of Digital Seismograph Networks, widely known in seismology. A web GUI (graphical user interface) is provided to test and document the web service. Additionally, basic built-in web applications are supplied with the web GUI to perform joint and synchronized time series data visualization as well as representation of stations on a geographical map. The web GUI also offers administration tools for data access policy management, creation of monitoring dashboards and data publication through web pages. The framework implements an authorization system that can be used to restrict both writing or reading operations. The TSDSystem can also be a useful tool for engineering surveillance systems. The implementing code of the framework is available with an open source license on a public repository together with a user manual.

Ultra8T: A sub-threshold 8T SRAM with leakage detection

In energy-constrained scenarios such as IoT applications, the primary requirement for System-on-Chips (SoCs) is to increase battery life. However, when performing the sub/near-threshold operations, the relatively large leakage current hinders Static Random Access Memory (SRAM) from normal read/write functionalities at the lowest possible voltage (VDDMIN). In this work, we first propose a model that describes a specific relationship between read current and leakage noise in a given column. Based on the model, Ultra8T SRAM is designed to aggressively reduce VDDMIN by using a leakage detection strategy where the safety sensing time on bitlines is quantified without any additional hardware overhead. We validate the proposed Ultra8T using a 256 × 64 array in 28 nm CMOS technology. Post-simulation results show successful read operation at 0.25 V with 1.11 μs read delay, and the minimum energy required is 1.69 pJ at 0.4 V

Neuron Circuit Based on a Split-gate Transistor with Nonvolatile Memory for Homeostatic Functions of Biological Neurons.

To mimic the homeostatic functionality of biological neurons, a split-gate field-effect transistor (S-G FET) with a charge trap layer is proposed within a neuron circuit. By adjusting the number of charges trapped in the Si3N4 layer, the threshold voltage (Vth) of the S-G FET changes. To prevent degradation of the gate dielectric due to program/erase pulses, the gates for read operation and Vth control were separated through the fin structure. A circuit that modulates the width and amplitude of the pulse was constructed to generate a Program/Erase pulse for the S-G FET as the output pulse of the neuron circuit. By adjusting the Vth of the neuron circuit, the firing rate can be lowered by increasing the Vth of the neuron circuit with a high firing rate. To verify the performance of the neural network based on S-G FET, a simulation of online unsupervised learning and classification in a 2-layer SNN is performed. The results show that the recognition rate was improved by 8% by increasing the threshold of the neuron circuit fired.

Modeling and Analysis of Dekker-Based Mutual Exclusion Algorithms

Mutual exclusion is a fundamental problem in concurrent/parallel/distributed systems. The first pure-software solution to this problem for two processes, which is not based on hardware instructions like test-and-set, was proposed in 1965 by Th.J. Dekker and communicated by E.W. Dijkstra. The correctness of this algorithm has generally been studied under the strong memory model, where the read and write operations on a memory cell are atomic or indivisible. In recent years, some variants of the algorithm have been proposed to make it RW-safe when using the weak memory model, which makes it possible, e.g., for multiple read operations to occur simultaneously to a write operation on the same variable, with the read operations returning (flickering) a non-deterministic value. This paper proposes a novel approach to formal modeling and reasoning on a mutual exclusion algorithm using Timed Automata and the Uppaal tool, and it applies this approach through exhaustive model checking to conduct a thorough analysis of the Dekker’s algorithm and some of its variants proposed in the literature. This paper aims to demonstrate that model checking, although necessarily limited in the scalability of the number N of the processes due to the state explosions problem, is effective yet powerful for reasoning on concurrency and process action interleaving, and it can provide significant results about the correctness and robustness of the basic version and variants of the Dekker’s algorithm under both the strong and weak memory models. In addition, the properties of these algorithms are also carefully studied in the context of a tournament-based binary tree for N≥2 processes.

EPO‐R: An efficient garbage collection scheme for long‐term transactions

SummaryThis article proposes EPO‐R, which is an efficient garbage collection scheme designed for multi‐version concurrency control (MVCC) protocols. MVCC generates a version for each update operation, and it can exhaust physical memory for dynamically changing environments such as IoT payments. Eager pruning of obsolete versions (EPO) is a novel garbage collection technique for long‐term transactions. We found room for improvement in EPO, which triggers reclamation invocation. EPO is triggered for each write operation, and it wastes CPU resources. The proposed method EPO‐R is triggered on a read operation to address this issue. The result of experiments with 64 CPU cores and workloads with the combination of short‐term and long‐term transactions demonstrated that EPO‐R exhibited 6.3 times higher throughput than that of EPO. The reason for this can be explained by analyzing the number of unreclaimable versions.