Read-only Memory Research Articles

A CNN-Based E-Nose Using Time Series Features for Food Freshness Classification

In this article, a convolutional neural network (CNN)-based electronic nose system is proposed, which utilizes time series features to classify the freshness of food. The electronic nose is composed of three elements: a highly sensitive miniaturized micro-electromechanical systems (MEMS) metal–oxide (MOX)–semiconductor gas sensor array, a complementary metal–oxide–semiconductor (CMOS) integrated circuit, and a CNN-based classification unit. The gas sensors exhibit exceptional sensitivity, low power consumption, and a small size. The interface circuit for sensor readout is fabricated using a standard 180-nm CMOS process, with an area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.5\times1.5$ </tex-math></inline-formula> mm. The interface chip mainly consists of an analog-to-digital converter (ADC), an electrically erasable programmable read-only memory (EEPROM), an oscillator (OSC), power management, a heater driver, and a digital control circuit. Fixed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}{(}{t}{)}$ </tex-math></inline-formula> exposures are taken at specific intervals under gas input and output conditions. Time series features are extracted from a diverse set of sensor signals, which allows the subtle differences in various food odors at different freshness levels to be identified. The incorporation of time series feature extraction extends the data features, resulting in enhanced classification accuracy with a limited number of sensors. An abstract odor map input to the CNN is formed by combining the steady-state and transient information of the gas sensor response. The final freshness classification accuracy of 20 types of foods is 97.3%. The accuracy is improved by 6.5% after the implementation of time series feature extraction, demonstrating the significance of instantaneous fluctuation information for classification accuracy.

Exploring Effect of Residual Electric Charges on Cryptographic Circuits: Extended Version

We study a new transistor-level side-channel leakage caused by charges trapped in between stacked transistors namely residual electric charges (RECs). Building leakage models is important in designing countermeasures against side-channel attacks (SCAs). The conventional work showed that even a transistor-level leakage is measurable with a local electromagnetic measurement. One example is the current-path leak [1], [2]: an attacker can distinguish the number of transistors in the current path activated during a signal transition. Addressing this issue, Sugawara et al. proposed to use a mirror circuit that has the same number of transistors on its possible current paths. We show that this countermeasure is insufficient by showing a new transistor-level leakage, caused by RECs, not covered in the previous work. RECs can carry the history of the gate's state over multiple clock cycles and changes the gate's electrical behavior. We experimentally verify that RECs cause exploitable side-channel leakage. We also propose a countermeasure against REC leaks and designed advanced encryption standard-128 (AES-128) circuits using IO-masked dual-rail read-only memory with a 180-nm complementary metal-oxide-semiconductor (CMOS) process. We compared the resilience of our AES-128 circuits against EMA attacks with and without our countermeasure and investigated an RECs' effect on physically unclonable functions (PUFs). We further extend RECs to physically unclonable function. We demonstrate that RECs affect the performance of arbiter and ring-oscillator PUFs through experiments using our custom chips fabricated with 180- and 40-nm CMOS processes*.

Precision Hall Effect magnetometer.

The article presents a Hall effect magnetometer for use in a desktop Electron Paramagnetic Resonance spectrometer with a permanent magnet system and scanning coils. High accuracy and long-term stability at a small size and low cost are achieved through the use of digital signal processing, sequential data filtering in the time and frequency domains, as well as digital correction of raw data based on calibration information. The exciting current of the Hall sensor has the form of an alternating-signsquare wave formed by a high-speed H-bridge powered by a stable direct current. Generation of control signals, time selection of data, and their accumulation are performed using Xilinx Field-Programmable Gate Array Artix-7. MicroBlaze embedded 32-bit processor is used to control the magnetometer and interface with adjacent levels of the control system. Taking into account the individual characteristics of the sensor, including the offset voltage, the nonlinearity of the magnetic sensitivity, and their temperature dependences, is carried out by correcting the data obtained by calculating a polynomial depending on the raw magnitude of the field induction and the temperature of the sensor. The polynomial coefficients are individual for each sensor, are determined once during the calibration process, and are stored in the dedicated Electrically Erasable Programmable Read-Only Memory. The magnetometer has a high resolution of 0.1 µT and an absolute measurement error of not exceeding 6 µT.

BEOL-Compatible Bilayer Reprogrammable One-Time Programmable Memory for Low-Voltage Operation

In this work, an engineered submicrometer-scale bilayer stacking in via-type one-time programmable (OTP) memory and self-rectified resistive switching memory [resistive random access memory (ReRAM)] is demonstrated. The current development has achieved that co-existing memory functionality (OTP and ReRAM) with mitigating scaling requirement (fuse voltage trending with via size scaling), low fabrication complexity [via-fuse vs. gate-dielectric anti-fuse (AF)], and match with the current metal fuse technology ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&gt;$ </tex-math></inline-formula> 2 V). In addition, an electrode engineered has been proposed to realize low programming voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim $ </tex-math></inline-formula> 1.9 V) in via-fuse OTP featuring by metal–insulator–metal advanced back-end-of-line (BEOL) process with ruthenium materials. The impact of via-size, programming window, stacked structures, and integration capability has been extensively studied. Our results provide a pathfinding of high density, integration capability, low programming voltage, multifunctionality between programmable read-only memory (PROM), and resistive switching memory co-existing in future embedded applications.

A Blockchain-Based Architecture for Securing Industrial IoTs Data in Electric Smart Grid

There are numerous internet-connected devices attached to the industrial process through recent communication technologies, which enable machine-to-machine communication and the sharing of sensitive data through a new technology called the industrial internet of things (IIoTs). Most of the suggested security mechanisms are vulnerable to several cybersecurity threats due to their reliance on cloud-based services, external trusted authorities, and centralized architectures; they have high computation and communication costs, low performance, and are exposed to a single authority of failure and bottleneck. Blockchain technology (BC) is widely adopted in the industrial sector for its valuable features in terms of decentralization, security, and scalability. In our work, we propose a decentralized, scalable, lightweight, trusted and secure private network based on blockchain technology/smart contracts for the overhead circuit breaker of the electrical power grid of the Al-Kufa/Iraq power plant as an industrial application. The proposed scheme offers a double layer of data encryption, device authentication, scalability, high performance, low power consumption, and improves the industry’s operations; provides efficient access control to the sensitive data generated by circuit breaker sensors and helps reduce power wastage. We also address data aggregation operations, which are considered challenging in electric power smart grids. We utilize a multi-chain proof of rapid authentication (McPoRA) as a consensus mechanism, which helps to enhance the computational performance and effectively improve the latency. The advanced reduced instruction set computer (RISC) machines ARM Cortex-M33 microcontroller adopted in our work, is characterized by ultra-low power consumption and high performance, as well as efficiency in terms of real-time cryptographic algorithms such as the elliptic curve digital signature algorithm (ECDSA). This improves the computational execution, increases the implementation speed of the asymmetric cryptographic algorithm and provides data integrity and device authenticity at the perceptual layer. Our experimental results show that the proposed scheme achieves excellent performance, data security, real-time data processing, low power consumption (70.880 mW), and very low memory utilization (2.03% read-only memory (RAM) and 0.9% flash memory) and execution time (0.7424 s) for the cryptographic algorithm. This enables autonomous network reconfiguration on-demand and real-time data processing.

Edge computing-based intelligent monitoring system for manhole cover.

Unusual states of manhole covers (MCs), such as being tilted, lost or flooded, can present substantial safety hazards and risks to pedestrians and vehicles on the roadway. Most MCs are still being managed through manual regular inspections and have limited information technology integration. This leads to time-consuming and labor-intensive identification with a lower level of accuracy. In this paper, we propose an edge computing-based intelligent monitoring system for manhole covers (EC-MCIMS). Sensors detect the MC and send status and positioning information via LoRa to the edge gateway located on the nearby wisdom pole. The edge gateway utilizes a lightweight machine learning model, trained on the edge impulse (EI) platform, which can predict the state of the MC. If an abnormality is detected, the display and voice device on the wisdom pole will respectively show and broadcast messages to alert pedestrians and vehicles. Simultaneously, the information is uploaded to the cloud platform, enabling remote maintenance personnel to promptly repair and restore it. Tests were performed on the EI platform and in Dongguan townships, demonstrating that the average response time for identifying MCs is 4.81 s. Higher responsiveness and lower power consumption were obtained compared to cloud computing models. Moreover, the system utilizes a lightweight model that better reduces read-only memory (ROM) and random-access memory (RAM), while maintaining an average identification accuracy of 94%.

Recommendation System Using the K-Nearest Neighbor Approach: A Case Study of Dual Camera Quality as a Smartphone Selection Criterion

Many smartphones today need to be more precise about choosing one that suits the user's needs. In fact, smartphone sellers sometimes need help recommending smartphones that suit buyers' needs. Generally, buyers search for smartphone specifications with keywords they desire, but the results appear different from what they expected. Users need the main specifications, such as Random Access Memory (RAM) and Read Only Memory (ROM) capacity, battery, and high camera quality. This research aims to implement the K-Nearest Neighbor (KNN) algorithm for recommendation smartphone selection based on the criteria mentioned. The data test results show that the combination of KNN with four criteria has good performance, as indicated by the accuracy, precision, recall, and f-measure values of 95%, 94%, 97%, and 95%, respectively.

METHODS FOR TABULAR IMPLEMENTATION OF ARITHMETIC OPERATIONS OF THE RESIDUES OF TWO NUMBERS REPRESENTED IN THE SYSTEM OF RESIDUAL CLASSES

Context. Implementation of modular arithmetic operations of addition, subtraction and multiplication by a tabular method based on the use of the tabular multiplication code. The object of the study is the process of tabular implementation of basic arithmetic operations on the residues of numbers represented in the system of residual classes.&#x0D; Objective. The goal of the work is to develop methods for the tabular implementation of the arithmetic operations of multiplication, addition and subtraction of the residues of two numbers based on the use of the tabular multiplication code.&#x0D; Method. Tabular methods for implementing integer arithmetic modular operations of addition, subtraction and multiplication are proposed for consideration. In order to reduce the amount of equipment for a tabular operating unit of computer systems that implements modular operations of addition, subtraction and multiplication by reducing the coincidence circuits AND in the nodes of the tables for implementing arithmetic operations based on the code of table multiplication, two methods for performing arithmetic modular operations of addition and subtraction have been developed. These methods are based on the code of tabular multiplication, the use of which will reduce the amount of equipment of the tabular operating unit. Thus, despite the difference in the digital structure of the tables of modular operations of addition, subtraction and multiplication based on the use of the tabular multiplication code, two new tabular methods for implementing arithmetic modular operations of addition and subtraction have been created. Based on them, algorithms for tabular execution of modular arithmetic operations of addition and subtraction have been developed. Using these algorithms, it is possible to synthesize a structurally simple, highly reliable and fast table operating unit that operates in a system of residual classes, which is based on three separate permanent storage devices (read-only memory), each of which implements only one fourth of the corresponding complete table of values of the modular operation, what is earlier in the theory tabular arithmetic was supposed to be impossible.&#x0D; Results. The developed methods are justified theoretically and studied when performing arithmetic modular operations of addition, subtraction and multiplication using tabular procedures.&#x0D; Conclusions. The conducted examples of the implementation of integer arithmetic modular operations of addition and subtraction can be considered as presented experiments. The results obtained make it possible to recommend them for use in practice in the design of computer systems operating in a non-positional number system in residual classes. Prospects for further research may be to create a tabular method for implementing integer arithmetic modular division operations based on the use of the tabular multiplication code.

GaN Memory Operational at 300 °C

The most commonly used memory cells, namely a 32-bit <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times10$ </tex-math></inline-formula> -bit read-only memory, a 1-bit 4-transistor static random-access memory, D latch, and D flip-flop (DFF), were demonstrated using high temperature (HT) GaN technology on a monolithically integrated GaN-on-Si platform and n-FET-only E/D-mode logic (E: enhancement, D: depletion). The memory cells exhibit stable operation at 300 °C. A maximum clock frequency of 36 MHz at 300 °C was estimated for the DFF using the measured setup time. To the best of the authors’ knowledge, the operational temperature of the reported prototypes represents the highest value for GaN memory, paving the way for the realization of robust mixed-signal systems operating at HT.

Simulative analysis of all-optical reflective semiconductor optical amplifier based 2-to-4 line decoder and read only memory (ROM)

Abstract In this paper, all-optical 2-to-4 line decoder and read-only memory (ROM) are analyzed using a Reflective Semiconductor Optical Amplifier (RSOA) based optical switch. The structures of these 2-to-4 line decoder and read only memory are very simple and the operating speed is 200 Gbps, which can be used in optical hardware systems. The 2-to-4 line decoder output shows a very high extension ratio (ER), contrast ratio (CR), and Q value. These high values indicate the distinguishment between two states (‘1’ and ‘0’) very clearly.

Моделирование функционального узла управления матричным индикатором на базе программируемой логической интегральной схемы

The article presents the process of simulation of the functional control unit of a matrix indicator on the basis of a programmable logic integrated circuit in the Xilinx Vivado Design Suite tool programming environment. Analysis and synthesis of the hardware language constructs, as well as developing RTL models were carried out using the Xilinx ISE software. There have been defined the functional modules common to the matrix indicator control unit: &#x0D; a finite state machine that generates a sequence of characters; a matrix indicator control unit that outputs a sequence &#x0D; of characters to a matrix indicator generating a finite automaton; a button bounce filter; frequency divider. A logic unit model combining functional nodes has been realized. Xilinx ISE CAD produced an RTL model that shows interaction of the nodes and the appearance of the top level. The matrix indicator control unit is presented as four interrelated devices: a column counter that enumerates the columns; a column decoder that takes input values and produces the value "1" only to one of the outputs, the number of which is equal to the number of the column whose value is put to the input; a character code register which receives, stores and transmits character codes; read-only memory which stores encodings of lines for sending an information signal in case of arrival of a particular word or a column. The specific features of implementing the modules on programmable logic are considered. A test module developed in the Verilog language was designed for verification, which is a step-by-step input of values and delays between input. Testing the modules that make up the matrix indicator control unit was carried out.

Experimental Study of Transient Dose Rate Effect on System-in-Package SZ0501

This article investigates the transient dose rate effect (TDRE) on the system-in-package (SiP) SZ0501 experimentally. A specialized program is designed for TDRE tests. With the increase of dose rates, the failure features of the SiP are recorded. Photocurrents on each power supply line are also measured to assist in analyzing SiP failures. In addition, both enabled and disabled programmable read-only memory (PROM) cases are considered to compare their discrepancies. The experimental results show that high frequency (HF) signals in the SiP are much sensitive to TDRE. Also, the logical resource in its field-programmable gate array (FPGA) presents a higher sensitivity than the clock resource, which is a contrary finding to the previous results. Besides, it is found that there seems to be a micro latch-up window in the SiP. Moreover, this SiP demonstrates different TDRE for enabled PROM and disabled PROM cases, and it has an automatic reconfiguration process in the case of enabled PROM. These findings are followed by a detailed analysis and discussion.

Moving Toward Seamless Interinstitutional Electronic Image Transfer.

There is universal agreement that the retirement of medical image transfer via compact disc read-only memory (CD-ROMs) and other physical media is long overdue, especially in a world where it is almost impossible to purchase a new computer with a CD-ROM reader. It is embarrassing that medicine’s most technologically advanced specialty continues to rely on antiquated technology like CD-ROMs and facsimile machines to transfer information essential to radiology workflow and patient care. Despite the efforts of radiology’s leading specialty society initiatives such as Image Share and #DitchtheDisk, the response from industry leaders and the overall diagnostic imaging market has been slow to adopt modern image-sharing standards and interoperability.

Bifunctional HfOx-based Resistive Memory: Reprogrammable and One-Time Programmable (OTP) Memory

The dual functions in HfOx-based ReRAM and 2V-programmable via-fuse technology featuring in simple metal-insulator-metal BEOL process are presented, which can integrate with the current metal fuse technology. The impact of via-size, ReRAM, and via-fusing programming windows, stacked structures, and integration capability has been extensively studied. The performance and reliability risk assessments show that the ReRAM and via fuse can sustain at 438 K for 500 h without any degradation. Our results provide pathfinding of high density, integration capability, low programing voltage, multi-functionality between programmable read-only memory (PROM) and ReRAM co-existing in embedded applications.

An Optical/Ferroelectric Multiplexing Multidimensional Nonvolatile Memory from Ferroelectric Polymer.

Multiplexing physical dimensions to realize multidimensional storage in a single material has been a goal to increase storage density and data security. Multidimensional storage is only achieved in optical storage material (OSM) by far. Poly(vinylidene fluoride) (PVDF), a semicrystalline polymer, is widely studied as a candidate for ferroelectric random access (FeRAM). Herein, the atomic force microscopy (AFM)-based infrared spectroscopy techniqueis used to induce multilevel phase transformations in PVDF ultrathin film on nanometric scales and for writing/readout of IR signals. An optical/ferroelectric multiplexing PVDF memory, where information can be coded with independent four-level optical IR and bilevel ferroelectric signals, is demonstrated. High data security and a storage density up to 180 GBit in.-2 are achieved simultaneously. Owing to the different critical temperature for phase transformation (optical data, <167°C) and polarization switching (ferroelectric data, <100°C), the multiplexing memory can function both as optical read-only memory and FeRAM. This work expands material supporting physical dimensions multiplexing beyond OSM for the first time, opening up new opportunities for future high-capacity, multifunctional nano-memory. The strategy proposed here enables on-demand and tunable programming on IR waves, offering prospects for fabrication of active nano-optical devices.

Design, Fabrication, and Characterization of a Laser-Controlled Explosion-Initiating Device with Integrated Safe-and-Arm, EMP-Resistant, and Fast-Acting Technology Based on Photovoltaic Power Converter.

To augment the intelligence and safety of a rocket or ammunition engine start, an intelligent initiation system needs to be included in the data link. A laser-controlled intelligent initiation system with inherent safety and a laser-controlled explosion-initiating device (LCEID) incorporating electromagnetic pulse (EMP) resistant, safe-and-arms fast-acting modular device based on photovoltaic power converter technology is designed and fabricated in this work. LCEID is an integrated multi-function module consisting of the optical beam expander, GaAs photovoltaic (PV) array, safe-and-arms integrated circuit, and low-energy initiator. These components contribute to EMP resistance, fast-acting, safe-and-arm, and reliable firing, respectively. To achieve intelligent initiation, each LCEID has a unique “identification information” and a “broadcast address” embedded in integrated-circuit read-only memory (ROM), which is controlled by encoded laser addressing. The GaAs PV array was investigated to meet the low-energy initiator firing voltage requirements. Experimental results show that the open-circuit voltage, short-circuit current, and maximum power output of the four-junction GaAs PV array illuminated by a 5.5 W/cm2 laser beam were 220 mA, 21.5 V, and 3.70 W, respectively. When the voltage of the 22 μF energy storage capacitor exceeds 20 V, the laser charging time is found to be shorter than 2.5 s. Other aspects of LCEID, such as laser energy coupling efficiency, the firing process, and the energy-boosting mechanism, were explored. Measurements show that the coupling efficiency of the micro lens with a radius of curvature D = 20 μm and size of r = 50 μm reaches a maximum of 93.5%. Furthermore, for more than 18 V charge voltage, the LCEID is found to perform reliably. The fabricated LCEID demonstrated a high level of integration and intrinsic safety, as well as a finely tailored initiation performance that could be useful in military applications.

Tunable lanthanum doping in double perovskite films for read-only memory

Rare earth ions have been widely investigated as active dopants in various materials because of their distinct optical, electronic and magnetic properties. Halide perovskite resistive memories have attracted increasingly recent interest for tremendous potential applications in computation and data storage techniques. However, it remains unexplored to implement rare earth doping strategy for tuning perovskite resistive memories. Here, we report read-only memories based on environment-friendly and air-stable lead-free double perovskite Cs2AgBiBr6 films, which is particularly tuned by rare earth La3+ doping. We use the vacuum sublimation and solution processing method to obtain Cs2AgBiBr6 crystals doped by different content La3+, and fabricate resistive memory devices based on doped Cs2AgBiBr6 films. The simplest sandwich-like structure composed of ITO/La-doped-Cs2AgBiBr6/Ag only is designed in cross-bar array architecture with high-integration and simple operation. The resistive memory device of La-doped Cs2AgBiBr6 films demonstrate a typical write-once-read-many-times (WORM) behavior with low onset voltage of 1 V and long retention time of 12000 s. In particular, the ON/OFF ratio of the La-doped Cs2AgBiBr6 film is 100 times higher than that of the undoped Cs2AgBiBr6 film. This study provides a new insight to design and manipulate memory devices based on lead-free halide perovskite materials through doping effect of rare earth ions.

THE ENHANCEMENTS IN STORAGE CAPACITY AND LONG-TERM DATA RETENTION OF MULTIDIMENSIONAL FLASH MEMORY IN MODERN MICROCIRCUIT APPLICATIONS

Generally, flash memory is a type of permanent memory for computers in which the contents can be reprocessed or erased electronically. Compared to programmable read-only memory that can erase electricity, operations on it can be performed on modules located in different locations. Flash memory is much less expensive than EEPROM, which is why it has become a dominant technology. Especially, in situations, this stable and long-term data retention is required. Its use is allowed in various cases like digital audio players, photo and video cameras, mobile phones and smartphones, and specialized Android applications on the memory card. Additionally, it is also used on USB flash drives, traditionally used to store and transfer information between computers. The proposed model provides enhancements to the storage capacity of various flash memory modules. In a saturation point, the proposed model achieved 93.03% of NOR Memory management, 89.31% of NAND Memory management, 94.25% of Ferroelectric RAM Memory management, and 94.53% of Magnetic RAM Memory management, 96.05% of Ovonic Unified Memory management and 96.16% of Salcogenide RAM Memory management.

A Highly Miniaturized, Chronically Implanted ASIC for Electrical Nerve Stimulation.

We present a wireless, fully implantable device for electrical stimulation of peripheral nerves consisting of a powering coil, a tuning network, a Zener diode, selectable stimulation parameters, and a stimulator IC, all encapsulated in biocompatible silicone. A wireless RF signal at 13.56 MHz powers the implant through the on-chip rectifier. The ASIC, designed in TSMC's 180 nm MS RF G process, occupies an area of less than 1.2 mm2. The IC enables externally selectable current-controlled stimulation through an on-chip read-only memory with a wide range of 32 stimulation parameters (90-750 µA amplitude, 100 µs or 1 ms pulse width, 15 or 50 Hz frequency). The IC generates the constant current waveform using an 8-bit binary weighted DAC and an H-Bridge. At the most power-hungry stimulation parameter, the average power consumption during a stimulus pulse is 2.6 mW with a power transfer efficiency of ∼5.2%. In addition to benchtop and acute testing, we chronically implanted two versions of the device (a design with leads and a leadless design) on two rats' sciatic nerves to verify the long-term efficacy of the IC and the full system. The leadless device had the following dimensions: height of 0.45 cm, major axis of 1.85 cm, and minor axis of 1.34 cm, with similar dimensions for the device with leads. Both devices were implanted and worked for experiments lasting from 21-90 days. To the best of our knowledge, the fabricated IC is the smallest constant-current stimulator that has been tested chronically.

Advanced Nonvolatile Organic Optical Memory Using Self-Assembled Monolayers of Porphyrin-Fullerene Dyads.

Photo-switchable organic field-effect transistors (OFETs) represent an important platform for designing memory devices for a diverse array of products including security (brand-protection, copy-protection, keyless entry, etc.), credit cards, tickets, and multiple wearable organic electronics applications. Herein, we present a new concept by introducing self-assembled monolayers of donor–acceptor porphyrin–fullerene dyads as light-responsive triggers modulating the electrical characteristics of OFETs and thus pave the way to the development of advanced nonvolatile optical memory. The devices demonstrated wide memory windows, high programming speeds, and long retention times. Furthermore, we show a remarkable effect of the orientation of the fullerene–polymer dyads at the dielectric/semiconductor interface on the device behavior. In particular, the dyads anchored to the dielectric by the porphyrin part induced a reversible photoelectrical switching of OFETs, which is characteristic of flash memory elements. On the contrary, the devices utilizing the dyad anchored by the fullerene moiety demonstrated irreversible switching, thus operating as read-only memory (ROM). A mechanism explaining this behavior is proposed using theoretical DFT calculations. The results suggest the possibility of revisiting hundreds of known donor–acceptor dyads designed previously for artificial photosynthesis or other purposes as versatile optical triggers in advanced OFET-based multibit memory devices for emerging electronic applications.