Fabricating advanced Fully Depleted SOI (FD-SOI) Complementary Metal Oxide Semiconductor Field Effect Transistors (CMOS) require numerous material and process improvements. Junctions between metal contacts and the channel are considered to be of major importance as they have a direct impact on device performances. A well-controlled increase of the active dopant concentration in the sources and drains regions close to the channel is indeed required to lower the contact resistance. The Selective Epitaxial Growth of tens of nm thick heavily in-situ doped SiGe:B or Si:P Raised Sources and Drains (RSDs) on each side of pMOS or nMOS devices will lower that contact resistance, inject some uniaxial compressive or tensile strain in the channel and yield enough material for (gemano-)silicidation.We study here the impact of process conditions on (i) the incorporation of phosphorus, (ii) the Si:P lattice deformation and (iii) the electrical resistivity of blanket, highly doped Si:P films (>1×10²¹ atoms.cm-3) grown at relatively high temperatures. We then evaluate Si:P growth selectivity on patterned structures.Layers were deposited in an industrial RP-CVD epitaxy reactor at relatively high temperatures (600-750°C) with conventional Si, P and Cl gaseous precursors. Reactor pressures were high (above 100 Torr). The Si:P layers were characterized thanks to XRD, Spectroscopic Ellipsometry, AFM, 4 point probe, Tof-SIMS and Haze measurements.A SiH2Cl2 + PH3 + HCl + H2 chemistry was first of all used to grow those Si:P layers on blanket Si(001) wafers. The partial pressure of phosphine P(PH3) was increased to enhance the phosphorous content [P] in films. Figure 1 shows XRD scans for such layers. Even if [P] increased as P(PH3) increased, the resulting P concentrations were not that high ([P] increased from 0.3% up to 1.6% for a 4-fold increase of P(PH3). Layer resistivities are provided in Figure 2. As expected, there is a resistivity drop from 0.507 mOhm.cm down to 0.405 mOhm.cm whenP(PH3) increases from 8 up to 32Torr. Above 32Torr, there is a plateau close to 0.4 mOhm.cm. This plateau is most likely due to the formation of electrically inactive PxV clusters above a given P concentration.Looking for highly doped SiP layers, we evaluated other solutions to increase [P]. Figure 3 shows HRXRD scans for films grown with a fixed PH3 flow and various SiH2Cl2 partial pressures. Increasing the SiH2Cl2 partial pressure resulted, for a given PH3 flow, in higher Si:P growth rates and P concentrations, as shown in Figure 4 (data coming from Fig. 3 HRXRD profiles). An increase of the PH3 partial pressure with a weak silicon flow indeed ended up in P surface saturation and P desorption.In Figure 5, we show a HRXRD scan typical of a highly tensile-strained, good crystalline quality Si:P film with a phosphorus concentration of 4.35×10²¹ atoms.cm-3. The electrical resistivity of that layer is 0.82 mΩ.cm. Above a P concentration threshold, the electrical resistivity indeed re-increases as [P] increases and reaches really high values (formation of huge numbers of electrically inactive PxV clusters). A Tof-SIMS depth profile of [P] in that sample is provided in Figure 6. TheP concentration from HRXRD is close to the one from Tof-SIMS (4.62×10²¹ cm-3), which is steady as a function of depth. Increasing too much the P content in the Si:P lattice to, ideally, obtain ultra-highly doped and really tensile-strained layers (to increase electron mobility in the channel nearby) is at first sight a no-go, as it results in electrical resistivity degradation. A significant fraction of electrically inactive PxV clusters can however be dissolved with the right annealing scheme to simultaneously have low resistivity and high tensile strain.In order to prepare the integration of such layers into FD-SOI devices, we then investigated selectivity on blanket oxide wafers (not shown here). Finally, we evaluated selectivity for mid P content Si:P layers ([P] = 3.6%) on actual FD-SOI devices. Figure 7 top-view SEM images show 2D Si:P RSDswithout any poly-nuclei on SiO2 isolation, SiN hard mask and spacers of gates. We thus succeeded in introducing highly doped tensile-strained SiP layers into FD-SOI devices. Figure 8 micro-Reciprocal Space Map around the (113) Bragg reflection used to to extract [P] in a 50×100 µm2 measurement box. It was 3.2%, a value slightly lower than on bulk, blanket Si, possibly because of loading effects. Figure 1
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