Reactive Ion Etching Step Research Articles

Low-loss silicon nitride photonic ICs for near-infrared wavelength bandwidth.

Low-loss photonic integrated circuits (PICs) are the key elements in future quantum technologies, nonlinear photonics and neural networks. The low-loss photonic circuits technology targeting C-band application is well established across multi-project wafer (MPW) fabs, whereas near-infrared (NIR) PICs suitable for the state-of-the-art single-photon sources are still underdeveloped. Here, we report the labs-scale process optimization and optical characterization of low-loss tunable photonic integrated circuits for single-photon applications. We demonstrate the lowest propagation losses to the date (as low as 0.55 dB/cm at 925 nm wavelength) in single-mode silicon nitride submicron waveguides (220×550 nm). This performance is achieved due to advanced e-beam lithography and inductively coupled plasma reactive ion etching steps which yields waveguides vertical sidewalls with down to 0.85 nm sidewall roughness. These results provide a chip-scale low-loss PIC platform that could be even further improved with high quality SiO2 cladding, chemical-mechanical polishing and multistep annealing for extra-strict single-photon applications.

Metal nanoparticle arrays via a water-based lift-off scheme using a block copolymer template

Metal nanoparticles (NPs) can exhibit unique electronic, magnetic, optical, and catalytic properties. Highly ordered, dense arrays of non-close-packed, surface-supported metal NPs are thus of potential use in a wide range of applications. Implementing such arrays over large surfaces can, however, be both technologically challenging and prohibitively expensive using conventional top-down nanofabrication techniques. Moreover, many existing patterning methods are too harsh for sensitive substrate surfaces and their applications. To address this, we here investigate a fabrication protocol involving a water-based lift-off scheme in which the template pattern generation is rapidly and inexpensively achieved through block copolymer (BCP) self-assembly. A three-layer lift-off stack consisting of, from top to bottom, a poly(styrene-block-2-vinyl pyridine) template, a SiO x intermediate hardmask, and a water-soluble poly(vinyl alcohol) sacrificial layer is employed in this endeavor. Solvent-induced surface reconstruction (SISR) is used to generate an initial surface topography in the BCP template which is subsequently transferred to the layers beneath in a sequence of reactive ion etching steps. Through judicious selection of stack materials and dry etch chemistries, a layered, high-aspect-ratio, nanoporous mask is thus implemented. After metal deposition, the mask and excess material are simply removed in a lift-off step by dissolving the bottommost sacrificial layer in water. The incorporation of an intermediate hardmask and a water-soluble sacrificial layer obviates the need for harmful and/or corrosive lift-off solvents and decouples the BCP self-assembly process from the influence of substrate properties. We demonstrate the generation of well-ordered arrays of Au NPs capable of supporting sharp, localized surface plasmon resonances. We also investigate improvements to large-scale uniformity, as this is found sensitive to the SISR termination step in the original protocol. Extensions of the technique to other BCP morphologies and materials deposited ought to be straightforward.

Fabrication of High-Density Out-of-Plane Microneedle Arrays with Various Heights and Diverse Cross-Sectional Shapes

HighlightsHigh-density out-of-plane microneedle arrays were fabricated with a single photolithography and two deep reactive ion etching (DRIE) steps in anisotropic and isotropic modes, respectively.Microneedles in various heights were monolithically created by the identical DRIE processes and scanning electron microscopy images showed extremely sharp sub-micron (~145-nm-wide) tip.Diverse cross-sectional shapes of microneedles were implemented by altering photomask patterns.

Etch-free additive lithographic fabrication methods for reflective and transmissive micro-optics.

With the widespread application of micro-optics in a large range of areas, versatile high quality fabrication methods for diffractive optical elements (DOEs) have always been desired by both the research community and by industry. Traditionally, multi-level DOEs are fabricated by a repetitive combination of photolithography and reactive-ion etching (RIE). The optical phase accuracy and micro-surface quality are severely affected by various etching artifacts, e.g., RIE lag, aspect ratio dependent etching rates, and etching artifacts in the RIE steps. Here we propose an alternative way to fabricate DOEs by additively growing multi-level microstructures onto the substrate. Depth accuracy, surface roughness, uniformity and smoothness are easily controlled to high accuracy by a combination of deposition and lift-off, rather than etching. Uniform depths can be realized for both micrometer and millimeter scale features that are simultaneously present in the designs. The grown media can either be used directly as a reflective DOE, or as a master stamp for nanoimprinting refractive designs. We demonstrate the effectiveness of the fabrication methods with representative reflective and transmissive DOEs for imaging and display applications.

A Micromachined Resonant Low-Pressure Sensor With High Quality Factor

This article presents a micromachined resonant low-pressure sensor with high quality factor. In this sensor, an island-diaphragm structure was developed, translating low pressures under measurements to frequency shifts of resonators, and improving quality factors of resonators by eliminating modal interferences between resonators and the pressure-sensitive diaphragm. Numerical simulations were conducted, confirming that the developed resonant low-pressure sensor can work properly in the measurement range without modal interference due to the island-diaphragm structure. The fabrication process of the developed resonant low-pressure sensor including key steps of deep reactive ion etching, resonator release and anodic bonding was conducted in this study. Experimental characterization showed high quality factors of resonators (>30000), which were significantly better than previous study (<10000). Moreover, low fitting errors (within ±2 Pa), low hysteresis (within ±2 Pa) and high accuracies (measurement errors within ±2 Pa) were also characterized in the low pressure range of 0.1 kPa-1 kPa and the temperature range of −40 °C–60 °C, validating the high performances of the developed resonant low-pressure sensor.

Organic Single Crystal Patterning Method for Micrometric Photosensors

AbstractLight detection technologies are of interest due to their applications in energy conversion and optical communications. Single‐crystal organic semiconductors, such as rubrene, present high detectivities and charge carrier mobility, making them attractive for light‐sensing applications. Growth of high crystallinity organic crystals is achieved using vapor processes, forming crystals of arbitrary shapes and orientations and requiring posterior patterning processes. However, patterning the organic semiconductors using industry‐standard microfabrication techniques is not straightforward, as these often cause irreversible damage to the crystals. Here the fabrication of patterned micrometric rubrene photosensors is demonstrated through a combination of photolithography and Reactive Ion Etching steps. Protective layers during microfabrication minimize degradation of optoelectronic properties of the organic single crystals during fabrication. Crystals undergoing the patterning process presented a survival rate of 39%. Photoresponse values of up to 41 mA W−1 are obtained under illumination at 500 nm. This opens a route for the industrial‐scale fabrication process of high‐performance optoelectronic devices based on organic crystals semiconductors.

Temperature-Dependent Current Dispersion Study inβ-Ga₂O₃ FETs Using Submicrosecond Pulsed I–V Characteristics

A comprehensive study of drain current dispersion effects in β-Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> field-effect transistors (FETs) has been done using dc and pulsed measurements. Both the virtual gate effect in the gate-drain access region and mobile traps under the gate are the most plausible explanations for the experimentally observed pulsed current dispersion and high-temperature threshold voltage shift, respectively. Unpassivated devices show significant current dispersion between dc and pulsed I- V response in gate lag measurements characterized by time constants in the range of 400-690 μs both at room temperature and higher temperatures. The increasing time constant with temperature suggests a complex electron capture and emission process in the virtual gate. The reactive ion etching step during the device fabrication is most likely responsible for introducing the traps. The effect of traps can be minimized by using surface passivation layers, in this case, silicon nitride, which shows significant improvement in the current dispersion. This work demonstrates the detrimental effect that the traps can have on the current dispersion, which significantly limits the high-frequency operation of the device.

A new improved vertical comb type differential capacitive sensing micro accelerometer using silicon-on-insulator wafer technology

A new and improved approach using vertical combs for the differential capacitive sensing of acceleration using silicon-on-insulator (SOI) wafer technology is presented. The design, which supports a ± 30 g operational range demonstrates the enhanced linear range that is achievable using an SOI approach, which overcomes the limitations of the dissolved wafer process (DWP) technology based on the diffusion layer depth in silicon, used for the fabrication of MEMS accelerometers. Two technological approaches are compared, one having the same thicknesses of fixed and movable interdigitated fingers (DWP) and the other having different thicknesses, using an SOI wafer. A remarkable sensitivity improvement, by a factor of up to two, is achieved for the capacitance change per unit g (deltaC g−1) using the new differential SOI design presented here. The bandwidth of the device is also improved significantly in the SOI design, compared to the DWP design. Furthermore, the effect of temperature (−40 °C to 125 °C) has an almost negligible influence on (deltaC) due to the built-in differential concept of comb-type fingers compared to DWP technology. Cross-axis sensitivity is also very low due to the stable, robust design of the accelerometer offering less stiction sideways and better pull-in stability. Simple analytical relations for dynamically changing overlap capacitance are derived and presented. These analytical results are compared with simulations using Coventorware software and are in agreement to within 1.8% in a linear range of operation up to a tip deflection of 8.5 µm. The effects of fabrication tolerances, including all the process steps, on the sensitivity (deltaC g−1) and bandwidth (BW), are also studied and the results presented. An overall figure of merit (FOM) is included which is better in this study compared to the available literature. Furthermore, only two wafers are needed to fabricate the proposed differential capacitive sensors, compared to conventional push–pull three plate systems using three wafers. A separate deep reactive ion etching (DRIE) step on two different wafers offers better debris removal as compared to the interdigitated fingers cut by a single DRIE step.

Nanopillar and nanohole fabrication via mixed lithography

We report a fabrication method for the production of nanopillar (NP) or nanohole (NH) arrays together with a micrometer-sized structure within a single layer. On a 200 mm silicon wafer, we produced 200–400 nm NP or NH arrays using electron beam lithography (EBL). The EBL patterns on a positive-tone EB resist—either a poly(methyl methacrylate) or chemically semi-amplified resist—were transferred to a hard mask oxide (HMO) layer using reactive-ion etching (RIE), as the first etching step. We used the HMO as an intermediate layer to connect the EB patterns to photolithography patterns. On the EB-patterned HMO layer, large-scale photolithography patterns were produced on a photoresist (PR), and transferred to the HMO layer using the second RIE step. After removing the PR, the mixed EB and photolithography patterns in the HMO layer were transferred to the target layer in the third RIE step. Our method offers an efficient way to combine nanometer-sized EBL patterns with high-throughput photolithography patterns in a single layer.

Reliable Nanofabrication of Single-Crystal Diamond Photonic Nanostructures for Nanoscale Sensing.

In this manuscript, we outline a reliable procedure to manufacture photonic nanostructures from single-crystal diamond (SCD). Photonic nanostructures, in our case SCD nanopillars on thin (<1 m) platforms, are highly relevant for nanoscale sensing. The presented top-down procedure includes electron beam lithography (EBL) as well as reactive ion etching (RIE). Our method introduces a novel type of inter-layer, namely silicon, that significantly enhances the adhesion of hydrogen silsesquioxane (HSQ) electron beam resist to SCD and avoids sample charging during EBL. In contrast to previously used adhesion layers, our silicon layer can be removed using a highly-selective RIE step, which is not damaging HSQ mask structures. We thus refine published nanofabrication processes to ease a higher process reliability especially in the light of the advancing commercialization of SCD sensor devices.

Microfluidic platform for cell analysis using through-polydimethylsiloxane micro-tip electrode array

In this study, we present the fabrication and measurement of a microfluidic system combined with a through-polydimethylsiloxane (PDMS) microtip electrode that can be used to measure the photosynthetic reaction of green algae cells in the microfluidic channel. The conventional single-cell based method has a disadvantage of low efficiency. To solve this problem, we propose a method of electrical feed-through interconnection of a microfluidic channel platform using a microtip electrode array. Silicon microtip arrays were fabricated using a combination of processes using deep reactive ion etching (DRIE) and reactive ion etching (RIE) steps. In the RIE process, the shape of the cylindrical silicon pillar changed from a cylinder to a probe shape according to the local change of the side-wall etching rate of the silicon pillar. The local ultra-micro electrode (UME) structure was fabricated using a self-alignment fabrication method without additional photolithography steps, and its electrochemical properties were confirmed using a cyclic voltammetry (CV) experiment. The photosynthetic algae cells were stacked in the PDMS microfluidic chip and then combined with the microtip electrode array using an acrylic jig. After assembling the microtip electrode array, the microtip was confirmed to penetrate the PDMS thin film through the CV experiment. When irradiated with light, the current induced by the oxygen produced by a photosynthetic reaction in the algae cells (stacked in the PDMS microfluidic chip) was measured using the microtip electrode array. Further, experiments were conducted to measure the force applied by the acrylic jig when combining the microtip electrode array with the PDMS microfluidic chip.

Improving the mechanical quality factor of ultra-low-loss silicon resonators

In its as-fabricated state, a silicon mechanical resonator with a very high quality factor at liquid helium temperatures is found to have two energy loss mechanisms which can be removed with a 3 h anneal at 300 °C. Because of the silicon wafer processing history, these mechanisms are likely introduced during the resonator fabrication process. One energy loss mechanism contributes to the overall background damping over the entire measured temperature range, 400 mK ≤ T ≤ 300 K, at a level of ΔQ−1≈3×10−9, and gradually reappears after aging on the order of 100 d timescales. The second energy loss mechanism is a broad peak, ΔQ−1≈2×10−8, centered near 100 K. This peak does not re-appear upon aging and is tentatively attributed to the tetrafluoromethane reactive ion etch step, despite the fact that the silicon resonator is protected with silicon nitride and photoresist during the process.

Isotropic Oxidation by Plasma Oxidation and Investigation of RIE Induced Effects for Development of 4H-SiC Trench MOSFETs

In this work, we examined the oxidation growth rates of the (0001) Si-face and (11−20) a-faces of 4H-SiC by carrying out oxidation in the 850°C-950 °C temperature range in a plasma afterglow furnace for application to trench MOSFETs. At 900 °C, this method results in almost equal oxide thickness on the Si-face and a-face which would nominally correspond to trench bottom and sidewalls in trench devices. Our results indicate that after NO annealing, the electronic properties of the plasma oxidized SiO2/SiC interface is comparable to control samples with gate oxides formed by dry oxidation at 1150 °C followed by NO annealing. Next, the effect of reactive ion etching (RIE) of 4H-SiC surfaces prior to gate oxidation was investigated using planar 4H-SiC MOS capacitors. Our experiments show that oxidation followed by NO annealing of surfaces with smooth morphology following the RIE step, results in similar interface charge and trap densities as MOS capacitors which did not undergo the RIE etching.

Nanoporous silicon nitride-based membranes of controlled pore size, shape and areal density: Fabrication as well as electrophoretic and molecular filtering characterization.

A new route will be presented for an all-parallel fabrication of highly flexible, freestanding membranes with well-defined porosity. This fabrication is based on arrays of well-defined Au nanoparticles (NPs) exhibiting a high degree of hexagonal order as obtained in a first step by a proven micellar approach. These NP arrays serve as masks in a second reactive ion etching (RIE) step optimized for etching Si and some important Si compounds (silicon oxide, silicon nitride) on the nanoscale. Application to commercially available silicon nitride membranes of well-defined thickness, delivers a diaphragm with millions of nanopores of intended and controlled size, shape, and areal density with narrow distributions of these parameters. Electrophoretic transport measurements indicated a very low flow resistance of these porous membranes in ionic solutions as expected theoretically. Size-selective separation of protein molecules was demonstrated by real-time fluorescence microscopy.

Taper silicon nano-scaffold regulated compact integration of 1D nanocarbons for improved on-chip supercapacitor

On-chip supercapacitors (SCs) hold the great promise as energy storage components integrated with silicon-based electronics. The target for improving the energy density is proposed to make SCs more competitive relative to batteries for on-chip applications. In this study, a novel approach is presented to fabricate a new class high energy SC electrode via compact integration of fullerene-like carbon decorated carbon nanotubes (FC-CNTs) regulated by the employed dry etched silicon taper nanorod (Si-TNR) scaffold. The involved dry reactive ion etching (RIE), electron-beam deposition (EBD), and atmospheric pressure chemical vapor deposition (APCVD) processing steps are fully compatible with the manufacturing techniques for silicon microelectronics, emphasizing the potential for practical mass production. The enhanced mass loading of carbon active material in specific footprint area (3mgcm−2) via compact integration, the design on highly interconnected FC-CNT network for excellent electronic transport property, as well as the meso-macro porous structure for rapid ion transportation, synergistically enable a remarkable areal capacitance without compromising the capability of rapid energy storage (192mFcm−2 at 1mVs−1, 123mF cm−2 at 1000mVs−1), representing the performance beyond the current state-of-the-art carbon based on-chip SCs.

Demonstration of an As2S3-on-LiNbO3 Grating Coupler and its Application of Measuring a Grating-based Filter

We demonstrate the design, fabrication, and measurement results for an As2S3 grating coupler on a LiNbO3 substrate. The proposed coupler was fabricated by a single lithography step followed by a single reactive ion etching step, which substantially reduces the processing steps compared to previously reported coupling between vertically integrated As2S3 and LiNbO3 waveguides. The measured grating coupling loss is 3.75 dB at 1563 nm for TE polarization. In addition, a sidewall Bragg grating cavity was fabricated using the grating input and output couplers. The Bragg grating response had a full width at half maximum (FWHM) of 0.0375 nm around the resonance wavelength and a cavity free spectral range (FSR) of 0.36 nm. Applications of these vertically integrated As2S3 grating couplers include 2-D beam steering using the electro-optic tuning afforded by the LiNbO3 substrate and electro-optic sensing.

Solar Water Splitting Photoelectrodes Structured By Laser Interference Lithography

One of the most environmentally friendly ways to produce hydrogen is by electrochemical splitting of water, using only sunlight as an energy source. In a photoelectrochemical cell with a semiconductor photoanode, water oxidation takes place on the surface of the electrode, at the interface between semiconductor and electrolyte. While photoelectrodes with structured surfaces tend to outperform planar ones, an increased surface area can be accompanied by enhanced surface recombination, which is deleterious to photoelectrode performance. Furthermore, the geometry of the surface structuring can influence light absorption and transport processes, and consequently the water splitting efficiency. In order to investigate the effect of surface structuring on water splitting performance, model photoelectrodes are needed, where the geometry and aspect ratio of the surface features can be controlled. In this work, we report on the use of laser interference lithography to generate precisely defined surface patterns on n+Si substrates. The geometry and aspect ratio of the surface features is determined during a reactive ion etching step. After etching, the samples are conformally coated with TiO2 by atomic layer deposition. Photoelectrochemical characterization of the electrodes is complemented by extensive physicochemical studies in an effort to identify the structural parameters with highest impact on performance in the photodriven water oxidation reaction. Figure 1

Fabrication and characterization of two‐dimensional cubic AlN photonic crystal membranes containing zincblende GaN quantum dots

AbstractWe successfully developed a process to fabricate freestanding cubic aluminium nitride (c‐AlN) membranes containing cubic gallium nitride (c‐GaN) quantum dots (QDs). The samples were grown by plasma assisted molecular beam epitaxy (MBE). To realize the photonic crystal (PhC) membrane we have chosen a triangular array of holes. The array was fabricated by electron beam lithography and several steps of reactive ion etching (RIE) with the help of a hard mask and an undercut of the active layer. The r/a‐ ratio of 0.35 was deter‐ mined by numerical simulations to obtain a preferably wide photonic band gap. Micro‐photoluminescence (µ‐PL) measurements of the photonic crystals, in particular of a H1 and a L3 cavity, and the emission of the QD ensemble were performed to characterize the samples. The PhCs show high quality factors of 4400 for the H1 cavity and about 5000/3000 for two different modes of the L3 cavity, respectively. The energy of the fundamental modes is in good agreement to the numerical simulations. (© 2015 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Improved tungsten nanofabrication for hard X-ray zone plates

We present an improved nanofabrication method of high aspect ratio tungsten structures for use in high efficiency nanofocusing hard X-ray zone plates. A ZEP 7000 electron beam resist layer used for patterning is cured by a second, much larger electron dose after development. The curing step improves pattern transfer fidelity into a chromium hard mask by reactive ion etching using Cl2/O2 chemistry. The pattern can then be transferred into an underlying tungsten layer by another reactive ion etching step using SF6/O2. A 630nm-thick tungsten zone plate with smallest line width of 30nm was fabricated using this method and characterized. At 8.2keV photon energy the device showed an efficiency of 2.2% with a focal spot size at the diffraction limit, measured at Diamond Light Source I-13-1 beamline.

Nanoforest of black silicon fabricated by AIC and RIE method

A nanoforest of black silicon was prepared using a method combining aluminum-induced crystallization (AIC) and reactive-ion etching (RIE). During the AIC period, a rough layer, incorporating AlSix intermetallics, was formed. This layer acted as an etch mask for the RIE step. X-ray photoelectron spectroscopic (XPS) measurements were performed to further analyze the formation of black silicon. Compared to Si3N4 and polysilicon, the black silicon exhibits a high degree of infrared absorption for wavelengths of about 3 to 5μm and 8 to 14μm, respectively. In addition, black platinum overlaid on the base of black silicon further improves the infrared absorption. This nanostructure forests of black silicon could be incorporated into the fabrication process for gas detectors, photovoltaic devices, and imaging applications to improve the infrared absorption characteristics.