Rate Low-density Parity-check Research Articles

Single-Shot Decoding of Linear Rate LDPC Quantum Codes With High Performance

We construct and analyze a family of low-density parity check (LDPC) quantum codes with a linear encoding rate, distance scaling as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$n^\epsilon $ </tex-math></inline-formula> for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\epsilon &gt; 0$ </tex-math></inline-formula> and efficient decoding schemes. The code family is based on tessellations of closed, four-dimensional, hyperbolic manifolds, as first suggested by Guth and Lubotzky. The main contribution of this work is the construction of suitable manifolds via finite presentations of Coxeter groups, their linear representations over Galois fields and topological coverings. We establish a lower bound on the encoding rate <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$k/n$ </tex-math></inline-formula> of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$13/72 = 0.180\ldots $ </tex-math></inline-formula> and we show that the bound is tight for the examples that we construct. Numerical simulations give evidence that parallelizable decoding schemes of low computational complexity suffice to obtain high performance. These decoding schemes can deal with syndrome noise, so that parity check measurements do not have to be repeated to decode. Our data is consistent with a threshold of around 4% in the phenomenological noise model with syndrome noise in the single-shot regime.

Capacity Analysis and Improvement of LDM-Based Multiple-PLP Configurations in ATSC 3.0

This article analyzes the capacities of various layered-division multiplexing (LDM)-based multiple physical layer pipe (M-PLP) configurations in Advanced Television Systems Committee (ATSC) 3.0. Further, this article proposes an extended multi-layer LDM that consists of a core layer and one or more enhanced layer(s) combined with different injection levels. The proposed multi-layer LDM can be combined with time-division multiplexing (TDM) and/or frequency division multiplexing (FDM) to multiplex more than two PLPs. This article provides the structures of a transmitter and receiver for the multi-layer LDM and various M-PLP configurations based on the proposed multi-layer LDM. In addition, by extending to a multi-layer LDM, the low rate low-density parity-check (LDPC) codes are proposed to improve the transmission efficiency of an extremely robust service with lower data rate, such as robust audio, in the core layer of the multi-layer LDM. Simulation results show that the M-PLP configurations based on more than two layers can obtain the improved reception performance compared to the M-PLP configurations based on only two layers supported by the PHY standard in ATSC 3.0. However, since the performance degradation of layered time-division multiplexing (LTDM) with fewer layers is not significant compared to multi-layer LDM, LTDM can be a good solution to efficiently transmit M-PLPs.

Iterative Decoding of LDPC-Based Product Codes and FPGA-Based Performance Evaluation

Low-density parity-check (LDPC) codes have the potential for applications in future high throughput optical communications due to their significant error correction capability and the parallel decoding. However, they are not able to satisfy the very low bit error rate (BER) requirement due to the error floor phenomenon. In this paper, we propose a low-complexity iterative decoding scheme for product codes consisting of very high rate outer codes and LDPC codes. The outer codes aim at eliminating the residual error floor of LDPC codes with quite low implementation costs. Furthermore, considering the long simulation time of computer simulation for evaluating very low BER, the hardware platform is built to accelerate the evaluation of the proposed iterative decoding methods. Simultaneously, the fixed-point effects of the decoding algorithms are also be evaluated. The experimental results show that the iterative decoding of the product codes can achieve a quite low bit error rate. The evaluation using field programmable gate array (FPGA) also proves that product codes with LDPC codes and high-rate algebraic codes can achieve a good trade-off between complexity and throughput.

A modified design of Raptor codes for small message length

Raptor codes are a class of fountain codes which can get capacity-achieving performance over various channels. Traditional Raptor codes can obtain perfect performance for large message length. However, small message length can cause significant performance deterioration. In this paper, a modified design of Raptor codes for small message length is proposed. The proposed Raptor codes are obtained by pre-coding the information symbols by low rate low-density parity-check codes and utilizing a low constant average degree distribution with high intermediate symbol recovery rate. Simulation results demonstrate that, although traditional Raptor codes can get good asymptotical performance, our proposed Raptor codes outperform traditional Raptor codes for small message length over binary erasure channels and binary input additive white Gaussian noise channels.

Polar Channel Coding Schemes for Two-Dimensional Magnetic Recording Systems

This paper proposes new two-dimensional magnetic recording (TDMR) systems using polar channel coding as practical error correction coding. It is known that the time and space complexities of the encoding/decoding algorithms based on polar channel coding are $\mathcal {O}(N \log N)$ , where $N$ is the codeword (block) length. If we compare the error-correction performance of a polar code with that of a low-density parity-check (LDPC) code in the same rate, it is known that the polar code has a longer length and its decoder still has a lower implementation complexity than the LDPC decoder. Therefore, relatively low-complexity coding schemes are preferable for any TDMR systems under high rates and relatively long codeword lengths. In this paper, the proposed TDMR system serially concatenates a two-dimensional (2-D) modulation code with one-dimensional (1-D) polar codes in each down-track direction. These element polar codes are designed on the fundamentals of the channel polarization theory, which are applied for channels with memory. Actually, it evaluates the performance of the signal processing scheme with concatenated coding and generalized partial response equalization for the proposed TDMR system using bit-patterned media by computer simulations. As a result, it shows that the block error rate performance of the proposed TDMR system with the 2-D modulation and polar channel coding schemes is superior to that of the 1-D system with the conventional 1-D high rate modulation and LDPC coding schemes.

A Novel UEP Fountain Coding Scheme for Scalable Multimedia Transmission

In this paper, we propose an efficient scheme to construct fountain codes that can provide unequal error protection (UEP) property. To reduce the coding complexity and improve the performance of previous duplicate UEP schemes in the literature, we implement different rate low-density parity-check codes instead of the duplication process and replace the high-complexity classical robust soliton distribution by low constant average degree distributions with high intermediate symbol recovery rates. Asymptotic analysis of both the duplicate scheme and our scheme is obtained by deriving unequal density evolution formulas over the binary erasure channel. Compared to previous UEP schemes, our scheme has lower complexity. Experimental results show that our scheme can obtain better decoding performance, especially for smaller input information length. Comparison of peak signal-noise ratio performance for the scalable video coding shows that, for moderate input information length, our scheme can provide a better basic video quality at lower overhead, but needs larger overhead to achieve a high video quality.

Check node unit for LDPC decoders based on one‐hot data representation of messages

A novel check node unit architecture for low-density parity check (LDPC) decoders, which avoids the usage of carry-based comparators for the computation of the required first and second minimum values, is presented. It relies on a one-hot representation of the input messages’ magnitude, obtained by q-to-2 q decoders. The two minimums are computed using an OR tree and a modified leading zero counter. The proposed architecture is imprecise, as the second minimum is not computed correctly when it is equal to the first one. The implementation results and the analysis of the error correction capability show that the proposed imprecise unit is highly suited for high rate LDPC codes; it presents up to 30% better hardware cost, a higher working frequency, while the loss of the decoding capability is negligible with respect to standard implementations.

A Golay complementary TS-based symbol synchronization scheme in variable rate LDPC-coded MB-OFDM UWBoF system

In this paper, a Golay complementary training sequence (TS)-based symbol synchronization scheme is proposed and experimentally demonstrated in multiband orthogonal frequency division multiplexing (MB-OFDM) ultra-wideband over fiber (UWBoF) system with a variable rate low-density parity-check (LDPC) code. Meanwhile, the coding gain and spectral efficiency in the variable rate LDPC-coded MB-OFDM UWBoF system are investigated. By utilizing the non-periodic auto-correlation property of the Golay complementary pair, the start point of LDPC-coded MB-OFDM UWB signal can be estimated accurately. After 100km standard single-mode fiber (SSMF) transmission, at the bit error rate of 1×10−3, the experimental results show that the short block length 64QAM-LDPC coding provides a coding gain of 4.5dB, 3.8dB and 2.9dB for a code rate of 62.5%, 75% and 87.5%, respectively.

스마트그리드를 위한 초고속 전력선통신기술 연구

In this paper, we study on the reliability of Very High-rate Power Line Communication (VH-PLC) for Smart Grid, so that the resultant data rate is over 400Mbps at a physical layer. Firstly, reviewing the research trend of the PLC, we discuss the required techniques for supporting the Smart Grid. Considering a pre-specification with the value of several parameters, we investigate a multi-carrier modulation technique to overcome limitations of higher rate transmission under power line channel environments. Then, we propose a system specification of the VH-PLC in the sense of enhancing two features. One is resolving the problem of the co-existence of the deployed high-speed PLC according to the published standardization of KS X 4600-1 in Korea. The other is getting better performance on the grid adopting the diverse element techniques, such as multi-carrier modulation, a subcarrier utilization mode, a variable rate LDPC (Low Density Parity Check) code, and a time and frequency diversity technique. Further, a simulation tool, composed of an Event-Driven simulator and a Time-Driven simulator, is developed for the purpose of verifying the system performance and continuously cross-checking the test bench signal of the proposed VH-PLC system.