Rapid Thermal Annealing System Research Articles

The influence of annealing atmosphere on sputtered indium oxide thin-film transistors

Indium oxide (In2O3) thin films sputtered at room temperature were annealed under different atmospheres and examined for thin-film transistor (TFT) active channel applications. The annealing process was performed in a rapid thermal annealing system at 350 °C under O2, Ar, forming gas (FG, 96% N2/4% H2), and N2. It was found that the annealed In2O3 TFTs exhibited high field-effect mobility (μ FE > 40 cm2 V−1s−1), high on/off current ratio (I on/off∼ 108), and controlled threshold voltage (V TH) for the enhancement- and depletion-mode operations. Note that the annealing atmosphere has a significant effect on the electrical performance of the In2O3 TFTs by inducing changes in oxygen-related species, particularly oxygen vacancies (VO) and hydroxyl/carbonate species (O–H/C–O). For the O2-, Ar-, FG-, and N2-annealed TFTs, μ FE was in increasing order accompanied by a negative shift in V TH, which is a result attributed to the larger VO in the In2O3 thin films. Furthermore, the ΔV TH of the FG-, and N2-annealed TFTs in a positive bias stress test was greater than that of the O2-, Ar-annealed devices, attributing to their lower density of O–H/C–O groups in the In2O3 thin films. Our results suggest that the annealing atmosphere contributes to the internal modifications of the In2O3 structure and in turn altered the electrical characteristics of TFTs. These annealed In2O3 TFTs with high performance are promising candidates for realizing large-area, transparent, and high-resolution displays.

(Invited, Digital Presentation) Investigation of Polarization Behavior of HfO2 Thin Films Via Piezoelectric Characterization

Nonvolatile memory based on field-effect transistors with ferroelectric gate dielectrics (FeFET) was first proposed in the 1960s[1]. Later, in the 1990s, FeFETs were proposed to operate as neuromorphic devices and were actively studied[2]. However, it has not been realized due to the difficulty of forming ferroelectric thin films on Si and obtaining a good Si/ferroelectric interface. This situation was greatly changed by the discovery of ferroelectricity in hafnium oxides [3]. Now, FeFETs have attracted attention again due to the high CMOS process compatibility of hafnium oxides as well as their good ferroelectricity even in ultra-thin films. FeFETs have many potential applications, including steep switching transistors and reservoir computing as well as nonvolatile memory. In addition, the understanding of the ferroelectric properties of HfO2-based thin films has been deepened. On the other hand, reliability issues such as robustness, switching endurance, fatigue characteristics, wake-up effects, and imprinting still remain to be addressed for practical applications. These are problems common to ferroelectric thin films, but because HfO2 is an ultra-thin film, they are not easy to analyze. Therefore, in this study, we focused on the evaluation of ferroelectricity by the direct piezoelectric effect. In contrast to the inverse piezoelectric response, the direct piezoelectric response is, in principle, independent of the film thickness, so we expect that the direct piezoelectric response could be analyzed even for HfO2-based thin films.TaN/Hf0.5Zr0.5O2 (HZO)/TaN capacitor was prepared on a Si wafer. TaN electrodes were deposited by DC sputtering method. The thickness of the TaN films was 10 nm. The HZO film was then deposited by the RF magnetron sputtering method using HfO2 and ZrO2 targets. The fabricated capacitor was annealed in a rapid thermal annealing system at 700 °C. The details of the deposition are described in Ref. 4. The direct piezoelectric response of the HZO film was measured using the wafer flexure technique [5]. The strain was applied periodically to the sample, and the charge induced via the direct piezoelectric response wasmeasured using a lock-in amplifier. While the conventional ferroelectric characterization, including the P-E measurement, might be influenced by the space charge, leakage current so on, the direct piezoelectric response only depends on the remaanenrt polarization because there are no other physical phenomena similar to the direct piezoelectric response. We investigated the state of polarization during the retention and wake-up process. The film showed a time-dependent imprint at room temperature during polarization retention. The internal electric field that generated the imprint gradually increased from 0.05 to 0.6 MV/cm. In contrast, the magnitude of the direct piezoelectric response did not change during the polarization retention. Similar analyses were also carried out for the wake-up process. Based on the obtained results, we concluded that the non-ferroelectric layer exists at the interface between the HZO film and TaN electrode and gradually transitions to ferroelectric phases through the electric field cycle[6]. The presentation will also cover the domain observation of HZO films by the direct piezoeelectric response.[1] J. L. Moll and Y. tarui, IEEE trans. Elect. Dev., ED-10, 338 (1963)[2] H. Ishiwara, Jpn. J. Appl. Phys., 32, 442 (1993)[3] T. S. Boscke, J. Muller, D. Brauhaus, U. Schroder, and U. Bottger, Appl. Phys. Lett. 99, 102903 (2011).[4] S. Migita, H. Ota, H. Yamada, K. Shibuya, A. Sawa, and A. Toriumi, Jpn. J. Appl. Phys., Part 1 57, 04FB01 (2018).[5] J. F. Shepard, P. J. Moses, and S. Trolier-McKinstry, Sens. Actuators, A 71, 133 (1998).[6] K. Takada, M. Murase, S. Migita, Y. Morita, H. Ota, N. Fujimura, and T. Yoshimura, Appl. Phys. Lett. 119, 032902 (2021)

Cost-Effective Formation of Ti/Ni/Ti/Au Ohmic Contacts to n-type SiC Using SiO2 Encapsulation Layer during Phosphorous Implant Activation

The purpose of this research is to develop a cost-effective formation of ohmic contacts to n-type SiC through ion implantation and activation. Although Nitrogen is commonly used as an n-type dopant, especially for in-situ doping during epitaxial growth, Phosphorus was chosen as dopant for this work due to the following reasons: Phosphorus has higher solubility than Nitrogen. Thus, it is easier to achieve higher concentration locally through ion implantation, which is needed for quality ohmic contact.Phosphorous has a higher activation rate at lower activation temperature, which could be beneficial if the availability of furnace equipment and cap layer material is limited.Phosphorus-implanted doping profile can be accurately detected through SIMS analysis against a constant in-situ doped nitrogen background doping of the n-type epi layer. Phosphorus was implanted using the implantation series shown in Table 1. As indicated, the three multiple energy implants, with the highest energy of 200keV and the lowest energy of 50keV, will form a 200-nm-deep box profile against a n- epitaxial layer (0.4μm, 2×1017cm-3) used as a RESURF layer for device fabrication (see Figure 1 and 2). Obtaining a good box profile with high doping concentration is necessary in achieving quality ohmic contact with low contact resistance.After ion implantation, the dopants must be thermally activated, and crystal damage must be recovered through annealing at high temperature between 1400~1700°C. The process of ion implantation and activation is shown in Figure 1. Traditionally, cap layers, such as pyrolyzed negative photoresist and AlN, have been used during implant activation to prevent surface deterioration. But using pyrolyzed negative photoresist as a cap layer requires a complex furnace setup, where inert gasses, such as Ar or N2, are needed to prevent the cap layer from oxidizing and evaporating. The deposition of a thick AlN layer requires a DC sputtering system where a 3-inch AlN sputtering target could cost over $500~. The AlN cap layer also requires KOH etch for removal after activation, which can also etch the SiC layer underneath. Because of the above reasons, we propose the use of 1µm thick SiO2 to encapsulate the front and back of implanted sample using PECVD deposition. The SiO2 encapsulation layer withstands temperature up to ~1500°C in air ambient, and the activation temperature and the ambient are set to these values for evaluation and analysis. As shown in Figure 3, if there is sufficient thickness (>1µm) of SiO2, the surface is protected from the deterioration caused by high temperature, and surface roughness is suppressed to the minimum as summarized in Table 2.Ti/Ni/Ti/Au (20nm/90nm/5nm/120nm) were deposited using e-beam evaporation system and annealed at 1050℃ for 2min using Heatpulse 610 RTA (Rapid Thermal Annealing) system in N2 ambient. This unique metal contact stacks are effective in forming quality ohmic contacts even when oxidation during annealing is inevitable. It has been widely understood that only Ni layer is necessary to form nickel silicide during thermal formation of ohmic contacts, but when oxygen is present from incomplete inert gas ambient or poor vacuum conditions, contact layer surface starts to oxides, forming a green NiO (nickel oxide) layer. This unwanted layer significantly deteriorates current conduction. The Ti layer (5nm) over the Ni layer in the proposed metal stacks reacts with oxygen easily, preventing further oxidation inward and achieving quality ohmic contact through effective nickel silicide formation. Even when state-of-the-art semiconductor fabrication equipment is unavailable, the proposed ohmic metal contact stacks will still be effective.Two-contact two-terminal patterns using the above ohmic metal stacks were initially fabricated for the confirmation of activation process. The plots in Figure 5 show the current conduction capability of evaluation pattern with an activation temperature of 1300°C and 1500°C, compared with a non-implanted epitaxial layer. As shown in the figure, with 1300°C annealing, the activation ratio is only ~20% and negative effects from the epi layer degradation dominates over carrier activation. Whereas, with 1500°C annealing, the activation ratio is roughly 70% and current conduction increases by a factor of 4 through the dopant activation process.The specific contact resistance ρC is significantly improved through N+ implant with an obtained value of 2.461×10-5 Ω·cm2 from the TLM evaluation plot in Figure 6. While the N+ implant is effective in reducing contact resistance, the high temperature activation annealing still slightly deteriorates the conductivity of the drift layer, where increase in sheet resistance RS is observed.The proposed ohmic metal stacks and SiO2 encapsulation enable cost-effective formation of ohmic contacts to n-type SiC where complex fabrication equipment setup is unavailable. Figure 1

Short duration growth of high-quality multi-layered graphene by temperature-controlled rapid heating chemical vapor deposition

Chemical vapor deposition using a rapid thermal annealing (RTA) system at atmospheric pressure with diluted methane gas (0.48 vol%)/Ar enabled the growth of high-quality multi-layered graphene on a Cu substrate at 1000 °C within a short time span. The minimum temperature rise time (including the reduction time) and growth time were 300 and 90 s, respectively. These conditions gave graphene films exhibiting 98.6% substrate coverage. The lateral sizes of the resulting graphene domains ranged from 0.2 to 1.2 μm with an average size of 0.46 μm while the film thicknesses were estimated to range from two to several layers based on the Raman 2D/G peak ratios. The Raman D peak indicative of defects was not detected on the graphene films. Precise control of the growth temperature within the range of 900 °C–1000 °C promoted reduction reactions and improved the quality of the graphene.

Unusually-high growth rate (∼2.8 μm/s) of germania nanowires and its hierarchical structures by an in-situ continuous precursor supply

Low-dimensional nanostructured semiconductors are becoming the promising materials for high-performance nanophotonics, nanoelectronics, and quantum devices. To enable these applications, it requires an efficient methodology to control the dimension of these materials during synthesis processes, and to achieve mass production of these materials with high reproducibility, perfect crystallinity, and low production cost. In this study, an ultra-fast, facile synthesis strategy is presented for reproducible monocrystalline hexagonal germania (GeO2) nanowires (NWs) and hierarchical structures. These GeO2 nanostructures were grown by one-step-annealing of the Ni film-covered GeSn epilayers in a rapid thermal annealing (RTA) system without any gaseous or liquid Ge sources. It was found that after short annealing for 60 s at 675 °C, the long GeO2 NWs of more than 170 μm are obtained, indicating that the growth rate is several magnitude orders higher than that of the common chemical vapor deposition (CVD) methods. The mechanism of the growth was studied by changing the growth temperature, catalyst type, and surface oxidation. The results indicate that this record-fast growth (>2.8 μm/s) of NW is due to the continuously generated in-situ GeO vapors from the Ni-catalyst decomposition of supersaturated GeSn epilayer. This work presents a rapid, and low-cost method to synthesis high-density GeO2 NW and its hierarchical structures which have the potential applications for optoelectronic communication/detection, superhydrophobic surfaces, photocatalyst, and sensing.

Improvement in Performance of Cu2ZnSn(S,Se)4 Absorber Layer with Fine Temperature Control in Rapid Thermal Annealing System

Improvement in Performance of Cu2ZnSn(S,Se)4 Absorber Layer with Fine Temperature Control in Rapid Thermal Annealing System

(Invited) Vertically Stacked Junction Devices Fabricated Using Single-Crystal Graphene on SiC Substrate

Graphene is a potential post-silicon nanomaterial because of its tremendous properties. Single-crystal graphene epitaxially grown on a SiC substrate is the most promising candidate for future electron devices. Single-crystal graphene with a 100 mm2 size has been successfully fabricated using a high-temperature rapid thermal annealing system [1]. In this study, two types of stacked graphene devices using graphene on SiC are demonstrated. The first device is a bi-crystal system consisting of two graphene samples as shown in Fig. 1 (a). These samples are directly bonded in a face-to-face manner. Contact pins are attached to the graphene surface for ohmic contact. The electrical characteristics of the stacked graphene junction were ohmic at a low bias voltage below 20 V. The linear characteristic at a low bias voltage is attributed to the linear dispersion relation in the band structure of graphene, Dirac cone. At a high bias voltage, the conductance of the graphene junction drastically increased. This nonlinear behavior originates from a semi-metallic property far from the Dirac point. Thermal imaging results indicated that electrical power was directly converted to infrared radiation. The radiation efficiency was estimated to be approximately 10%, which was high compared to that of a previously reported graphene blackbody emitter. The infrared emission spectrum measured using FT-IR was blackbody-like [2]. The peak wavelength of the measured spectrum was almost constant at 10.2 µm with changing applied power. The estimated junction voltage was approximately 5 V at a bias voltage of 80 V. Hot electrons were injected to the graphene layer. The results suggested that infrared emissions from the graphene–graphene stacked junction could be attributed to a nonthermal emission mechanism, such as phonon–plasmon coupling. The other vertically stacked graphene junction is a tunneling diode as shown in Fig. 1 (b). An insulative layer is sandwiched between two graphene samples. A structured water layer [3] formed by deionized water treatment on the epitaxial graphene sample acts as a tunneling barrier. Nonlinear I–V characteristics were observed. The dynamic range of the current change reached the sixth order of magnitude. The estimated thickness of the structured water layer was approximately 0.5 nm. As the tunneling barrier was sufficiently thin, a direct tunneling phenomenon could be observed in a low bias regime. In a high bias regime, the Fowler–Nordheim tunneling phenomenon was observed. A sandwich structure of a vertically stacked graphene junction with a sub-nm-thick structured water layer was constructed through simple water treatment and a direct bonding technique [4]. [1] T. Aritsuki, et al., Jpn. J. Appl. Phys. 55 (2016) 06GF03. [2] N. Murakami, et al., Jpn. J. Appl. Phys. 60 (2021) SCCD01. [3] M. Kitaoka, et al., Jpn. J. Appl. Phys. 56 (2017) 085102. [4] J. Du, et al., Jpn. J. Appl. Phys. 58 (2019) SDDE01. Figure 1

AlGaN/AlN/SiC Metal-Oxide-Semiconductor Heterostructure Field-Effect Transistors with Al2O3 Gate-Oxide and Step-Graded AlGaN Channel

Al0.75Ga0.25N/n-AlxGa1-xN/Al0.75Ga0.25N/AlN metal-oxide-semiconductor heterostructure field-effect transistors (MOS-HFETs), grown on a SiC substrate, with step-graded Si-doped (n = 3 × 1018 cm-3) widegap AlxGa1-xN channel and Al2O3 gate-dielectric are investigated. Increased Al-compositions with x = 0.25, 0.5, and 0.75 towards the buffer were devised in the composite widegap channel. The high-k Al2O3 dielectric/passivation layer was grown by using a non-vacuum ultrasonic spray pyrolysis deposition (USPD) method. Experimental comparisons were made with respect to a conventional Schottky-gate HFET.The epitaxial structure of the studied Al2O3-dielectric Al0.75Ga0.25N/n-AlxGa1-xN/Al0.75Ga0.25N/AlN MOS-HFET (sample A) and Schottky-gate HFET (sample B). Both devices have the identical epitaxial structure grown on a SiC substrate by using a low-pressure metal-organic chemical vapor deposition (LP-MOCVD) system. The layer structure includes an undoped AlN buffer, a 20-nm undoped Al0.75Ga0.25N barrier, a 150-nm step-graded Si-doped (n = 3 × 1018 cm-3) AlxGa1-xN channel (x = 0.25, 0.5, and 0.75), and a 20-nm undoped Al0.75Ga0.25N barrier. Standard photolithography and lift-off techniques were used for device processing. For sample B, mesa etching was performed with respect to a 100-nm thick Ni barrier by using an inductively coupled-plasma reactive ion etcher (ICP-RIE). Flow rates were tuned and set at 10 sccm and 20 sccm for the mixed etching gases of BCl3 and Cl2, respectively. The 20-nm undoped Al0.75Ga0.25N barrier was etched away before deposition of source/drain electrodes. Ti (10 nm)/Al (50 nm)/Ni (10 nm)/Au (50 nm) were evaporated. The source/drain ohmic contacts were formed by annealing the sample for 25 seconds at 900°C by using a rapid thermal annealing (RTA) system (ULVAC MILA-5000). Then, 30-nm thick Al2O3 layer was deposited on the Al0.75Ga0.25N barrier by using the USPD technique. Finally, gate electrode of Ni (100 nm)/Au (50 nm) was evaporated after gate photolithography. As for sample A, the gate electrode was formed directly on the surface of Al0.75Ga0.25N barrier without oxide deposition.Improved device performance of the present MOS-HFET design have been obtained, including maximum drain-source current density (IDS, max ) of 130.1 A/mm at VGS = 10 V and VDS = 20 V, IDS at VGS = 0 V (IDSS0 ) of 83.1 mA/mm, on/off-current ratio (Ion /Ioff ) of 1.4 × 107, maximum extrinsic transconductance (gm, max ) of 11.8 mS/mm, two-terminal off-state gate-drain breakdown voltage (BVGD ) of -404 V, and three-terminal on-state drain-source breakdown voltage (BVDS ) of 364 V at 300 K. The present MOS-HFET design has also shown high spectral responsivity (SR) of 737 A/W under 250-nm deep-UV radiation at 300 K.

Band gap tuning of Cu(In,Ga)Se2 thin films by electrodeposition and their subsequent selenization using a rapid thermal annealing system

Band gap tuning of electrodeposited Cu(In1-x,Gax)Se2 thin films through varying In3+ and Ga3+ concentrations in the electrolytic bath is demonstrated. Cyclic voltammetry was used to determine best Cu(In1-x,Gax)Se2 deposition potentials at the different bath conditions. Band gap tuning of Cu(In1-x,Gax)Se2 was achieved, through incorporation of varying In3+ and Ga3+ levels during film growth, in the range of 1 to 1.4 eV, corresponding to Ga content 0 ≤ Ga/(In + Ga) ≤ 0.64. Deposited films were characterized by EDS/SEM, XRD, and Raman spectroscopy to determine chemical composition, morphology, and crystal structure. Results show that as-deposited Cu(In1-x,Gax)Se2 thin films are of low crystallinity, with Se and Cu-Se compounds present as a secondary phase. Selenization of electrodeposited Cu(In1-x,Gax)Se2 films was performed using a rapid thermal processing system at 550 °C in an overpressure reactive atmosphere of N2/H2 (96%:4%) and elemental Se vapor. Selenization treatment promoted recrystallization and elimination of secondary phases, resulting in an increase in grain size while maintaining film composition. Processed films with Ga/(In + Ga) = 0.35 were processed into devices, achieving 2.6% efficiency.

Electrical and optical properties of InGaN/GaN MQWs light-emitting diodes with Ni/Au/ITO transparent p-contacts

In the present study, optical and electrical properties of e-beam deposited Ni/Au/ITO (1.5/1/50 nm) contacts on p-GaN are investigated and compared with conventional thin Ni/Au (5/5 nm) semitransparent p-contacts. The contacts were annealed at 560 °C for 5 min in N2 + O2 ambient in a rapid thermal annealing system. The current–voltage (I–V) characteristics of both metal schemes showed linear behavior. The specific contact resistances and sheet resistances extracted from measured resistance versus contact pads spacing of Ni/Au and Ni/Au/ITO contacts were recorded ~ 2.71 × 10−3 Ω-cm2, 4.94 × 10−4 Ω-cm2, 2.021 × 105 Ω/□ and 2.1898 × 105 Ω/□, respectively. The normalized transmittance of Ni/Au/ITO film was recorded 81.6% at 463 nm, which was 8.5% higher than the conventional Ni/Au film (73.1%). Scanning electron microscopy images of contacts showed that the adhesion quality of Ni/Au/ITO contacts was superior to annealed Ni/Au contacts. It was found that electroluminescence intensity was higher (7.5%) for LED chip with Ni/Au/ITO p-contacts than LED chip with Ni/Au contacts. The forward voltages (VF) of LEDs with Ni/Au and Ni/Au/ITO contacts at 20 mA current injection were found 2.8 V and 2.91 V, respectively. These results indicate that Ni/Au/ITO may be used as transparent p-contacts for fabrication of high-performance GaN LEDs due to their better optical and adhesive properties compared to the conventional Ni/Au (5/5 nm) contacts on p-GaN.

Electrical and optical properties of metal‐sandwiched ZnO/Ti/Cu/Ti/ZnO transparent conductive thin film

Metal-sandwiched zinc oxide (ZnO)/titanium (Ti)/copper (Cu)/Ti/ZnO thin film systems were fabricated using magnetron sputtering technology and then annealed using a rapid thermal annealing system at temperatures from 100 to 400°C. The influence of the Ti film thicknesses and annealing temperatures on the surface morphologies, sheet resistance and optical properties were studied. The surface morphologies change a little with the annealing temperature rises. The sheet resistances reduce with the Ti film thickness or annealing temperature increasing. Both the max transmittance and figure of merit reduce with the increase of Ti film thickness. The max transmittance increases with the temperature increasing from 100 to 300°C and then reduces. However, the figure of merit increases with the temperature increasing which indicates that the metal-sandwiched ZnO/Ti/Cu/Ti/ZnO thin film system annealed at 400°C has the optimal performance.

Ultra-fast plasmonic back reflectors production for light trapping in thin Si solar cells

A fast method is presented to fabricate plasmonic light trapping structures in just ten minutes (>5 × faster than the present state of art), with excellent light scattering properties. The structures are composed of silver nanoparticles (Ag NPs) deposited by thermal evaporation and self-assembled using a rapid thermal annealing (RTA) system. The effect of the RTA heating rate on the NPs production reveals to be crucial to the decrease of the annealing process. The Ag NPs are integrated in thin film silicon solar cells to form a plasmonic back reflector (PBR) that causes a diffused light reflectivity in the near-infrared (600–1100 nm wavelength region). In this configuration the thicknesses of the AZO spacer/passivating layers between NPs and rear mirror, and between NPs and silicon layer, play critical roles in the near-field coupling of the reflected light towards the solar cell absorber, which is investigated in this work. The best spacer thicknesses were found to be 100 and 60 nm, respectively, for Ag NPs with preferential sizes of about 200 nm. The microcrystalline silicon (μc-Si:H) solar cells deposited on such improved PBR demonstrate an overall 11% improvement on device efficiency, corresponding to a photocurrent of 24.4 mA/cm2 and an efficiency of 6.78%, against 21.79 mA/cm2 and 6.12%, respectively, obtained on flat structures without NPs.

FORMATION OF TRIANGULAR Cu MICROCRYSTALS IN Ti/Cu/Si THIN FILMS DURING ANNEALING

Sandwich stacked Ti/Cu/Si thin films were deposited on a single-side polished Si(111) substrate using DC magnetron sputtering system and annealed using a rapid thermal annealing (RTA) system. Complex dendritic patterns, whose branches are composed of Cu rods and triangular Cu microcrystals were obtained on Ti/Cu thin film annealed at 700[Formula: see text]C. The shape of one triangular Cu microcrystal is a truncated equilateral triangular pyramid with a flat top. Triangular Cu microcrystals grow in the number when Ti/Cu thin films are annealed at 800[Formula: see text]C. Experimental results show that anisotropy affects the growth of surface patterns and the top Ti capping layer works as a protection for the underlying Cu layer from oxidation.

STUDY ON ITO THIN FILMS PREPARED BY MULTI-ANNEALING TECHNIQUE

Indium tin oxide (ITO) thin films have been successfully prepared by a solution process followed by a multi-annealing method. In this study, we focus on the use of multi-annealing method, for which each layer was annealed at a suitable temperature, instead of a conventional annealing way, by means of a rapid thermal annealing system, in order to improve the film quality. The crystalline structure and surface morphology of the ITO thin films were investigated by using X-ray diffraction (XRD) spectrometer, atomic force microscope (AFM) and scanning electron microscope (SEM). It has been obtained that all of ITO films exhibit a single phase with (222)- and (440)-preferred orientations. The AFM and SEM observations show that the particle size of ITO films was about 10 nm and the ITO film thickness was 180 nm, respectively. In sequence, the electrical properties of ITO thin films were evaluated by using four-point probe and Hall effect measurement methods, and the optical properties were investigated by UV/VIS spectrometer. The results show that the best ITO films have electrical resistivity of 2.6 × 10-3 Ω.cm and transparency higher than 90 %, which strongly supports to the application of electrode in solar cell, LED or transistor devices from viewpoints of low-cost production and low-energy consumption.

Luminescence in the Visible Region from Annealed Thin ALD‐ZnO Films Implanted with Different Rare Earth Ions

Epitaxial ZnO thin films grown by atomic layer deposition on GaN/Al2O3 substrates are implanted with Yb, Dy, and Pr ions to a fluence of 5 × 1014 at cm−2 and subsequently anneals at 800 °C using a rapid thermal annealing (RTA) system. Structural properties of implanted and annealed ZnO films and the optical response are evaluated by channeling Rutherford backscattering (RBS/c) and photoluminescence spectroscopy (PL), respectively. RTA leads to a partial removal of the post‐implantation defects with simultaneous native defects transformation and optical activation of RE ions. It is found that two groups of defects: defects formed during implantation process and native defects, play an important role in the luminescence in the visible region. The room temperature PL spectra obtained from annealed ZnO:RE films do not show sharp PL lines from transitions within the RE 4f shell, but show near band gap emission and defect related emission, which energy emission is controlled by the RE atoms. It suggests a presence of RE‐related complexes that are formed during high‐temperature annealing in oxygen atmosphere. The excitonic and defect emission modified by RE ions create an optical response of the system resulting in a specific color of the emitted light.

Effects of vacuum rapid thermal annealing on the electrical characteristics of amorphous indium gallium zinc oxide thin films

We investigated the effects of vacuum rapid thermal annealing (RTA) on the electrical characteristics of amorphous indium gallium zinc oxide (a-IGZO) thin films. The a-IGZO films deposited by radiofrequency sputtering were subjected to vacuum annealing under various temperature and pressure conditions with the RTA system. The carrier concentration was evaluated by Hall measurement; the electron concentration of the a-IGZO film increased and the resistivity decreased as the RTA temperature increased under vacuum conditions. In a-IGZO thin-film transistors (TFTs) with a bottom-gate top-contact structure, the threshold voltage decreased and the leakage current increased as the vacuum RTA temperature increased. As the annealing pressure decreased, the threshold voltage decreased, and the leakage current increased. X-ray photoelectron spectroscopy indicated changes in the lattice oxygen and oxygen vacancies of the a-IGZO films after vacuum RTA. At higher annealing temperatures, the lattice oxygen decreased and oxygen vacancies increased, which suggests that oxygen was diffused out in a reduced pressure atmosphere. The formation of oxygen vacancies increased the electron concentration, which consequently increased the conductivity of the a-IGZO films and reduced the threshold voltage of the TFTs. The results showed that the oxygen vacancies and electron concentrations of the a-IGZO thin films changed with the vacuum RTA conditions and that high-temperature RTA treatment at low pressure converted the IGZO thin film to a conductor.

Large ferroelectric polarization of TiN/Hf0.5Zr0.5O2/TiN capacitors due to stress-induced crystallization at low thermal budget

We report on atomic layer deposited Hf0.5Zr0.5O2 (HZO)-based capacitors which exhibit excellent ferroelectric (FE) characteristics featuring a large switching polarization (45 μC/cm2) and a low FE saturation voltage (∼1.5 V) as extracted from pulse write/read measurements. The large FE polarization in HZO is achieved by the formation of a non-centrosymmetric orthorhombic phase, which is enabled by the TiN top electrode (TE) having a thickness of at least 90 nm. The TiN films are deposited at room temperature and annealed at 400 °C in an inert environment for at least 1 min in a rapid thermal annealing system. The room-temperature deposited TiN TE acts as a tensile stressor on the HZO film during the annealing process. The stress-inducing TiN TE is shown to inhibit the formation of the monoclinic phase during HZO crystallization, forming an orthorhombic phase that generates a large FE polarization, even at low process temperatures.

The gas sensing properties of hafnium oxide thin films depending on the annealing environment

The main focus of this study is to investigate the NO2 gas-sensing properties of HfO2 thin films, taking into the account the importance of the annealing environment and temperature. HfO2 films were produced with 10 nm and 20 nm thicknesses by atomic layer deposition (ALD). They were annealed under N2 and O2 environment with rapid thermal annealing system at two different temperatures. It was found that the NO2 responses of annealed in N2 environment were higher than annealed in O2 environment. The response of 10 nm thickness HfO2 thin film was calculated 22% for N2 environment whereas, it was calculated 18% for O2 environment. The highest gas response is obtained for 10 nm thickness of HfO2 thin film annealed in N2 environment. The performance of the HfO2 thin films reveals that the gas responses rely on annealing temperature as well as annealing atmosphere. The linear dependences of the sensitivity were also observed as the NO2 gas concentrations varied from 10 ppm to 30 ppm in logarithmic forms, indicating that HfO2 thin films offer promising potential for future practical applications in monitoring the NO2 gas.

Optimization of Post-selenization Process of Co-sputtered CuIn and CuGa Precursor for 11.19% Efficiency Cu(In, Ga)Se2 Solar Cells

In this work, CuInGa alloy precursor films are fabricated by co-sputtering of CuIn and CuGa targets simultaneously. After selenization in a tube-type rapid thermal annealing system under a Se atmosphere, the Cu(In, Ga)Se2 (CIGS) absorber layers are obtained. Standard soda lime glass (SLG)/Mo/CIGS/CdS/i-ZnO/ITO/Ag grid structural solar cells are fabricated based on the selenized CIGS absorbers. The influences of selenization temperatures on the composition, crystallinity, and device performances are systematically investigated by x-ray energy dispersive spectroscopy, x-ray diffraction, Raman spectroscopy, and the current density–voltage (J–V) measurement. It is found that the elemental ratio of Cu/(In + Ga) strongly depends on the selenization temperatures. Because of the appropriate elemental ratio, a 9.92% conversion efficiency is reached for the CIGS absorber selenized at 560°C. After the additional optimization by pre-annealing treatment at 280°C before the selenization, a highest conversion efficiency of 11.19% with a open-circuit (Voc) of 456 mV, a short-circuit (Jsc) of 40.357 mA/cm2 and a fill factor of 60.82% without antireflection coating has been achieved. Above 13% efficiency improvement was achievable. Our experimental findings presented in this work demonstrate that the post-selenization of co-sputtered CuIn and CuGa precursor is a promising way to fabricate high quality CIGS absorbers.

(Invited) Structural Control of Electrodeposited L10-FePt Nanodot Arrays Towards Reduction of Ordering Temperature

Electrodeposition has been widely used as a fabrication method of micro/nano structures due to its precise control of growth and high deposition uniformity at nanoscale. Utilizing these features, we have attempted to fabricate ferromagnetic nanodot arrays [1] by combining electron beam lithography (EBL) and electrodeposition for use in bit patterned media (BPM), which have been suggested as one of the few designs capable to achieve ultrahigh density in magnetic recording medium [2]. L10-FePt ordered alloy has been considered as one of the most promising candidates for the use in BPM due to its high magnetocrystalline anisotropy, Ku [2]. In previous work, we have succeeded to fabricate FePt nanodot arrays with 35 nm in pitch [1], however, high temperature annealing at ca. 600 oC was needed for the phase transition to L10 ordered structure, which caused a deterioration of nanodot arrays. In order to solve this problem, in the present work, we have attempted to fabricate uniform L10-FePt nanodot arrays by applying multilayered FePt structure [3] and FePt-Cu alloy structure [4] to lower the ordering temperature. Nanopore patterned substrates were fabricated by EBL onto sputter deposited Ru (60 nm thick) / Ti (5 nm thick) / n-Si (100) substrate. Utilizing these substrates, FePt was potentiostatically electrodeposited under the conditions summarized in Table 1 to fabricate FePt nanodot arrays. Post annealing treatment of deposited FePt was carried out in argon atmosphere (Ar 90 % and H2 10 %) using rapid thermal annealing system. Multilayered FePt were fabricated by pulse deposition of Fe-rich layer and Pt-rich layer with -1.4 and -0.8 V (vs. Ag/AgCl), and the thickness of each layer was set to around 2 nm by adjusting the pulse duration. For the fabrication of FePt-Cu alloy, CuSO4 was added into the bath condition of Table1. In order to analyze the effect of multilayered structure on phase transition and coercivity of FePt, magnetic properties and crystal structures of multilayered FePt film and continuous FePt film, which was deposited with constant potential of -1.0 V (vs. Ag/AgCl), with thickness of 20 nm after annealing at 450 oC for 1 h were analyzed. As a result, perpendicular coercivity increased from 1.7 kOe to 6.6 kOe in the multilayered structure compared to continuous film, and x-ray diffraction (XRD) patterns of multilayered film showed clear diffraction peaks of L10 ordered structure, whose intensity were very small in the continuous film. In addition, ordering parameter, S, of FePt films were calculated form the axial ratio (c/a), which was determined from the XRD patterns, and it was found that S was increased from 0.24 to 0.80 in multilayered structure, indicating that phase transition of FePt was facilitated in the multilayered structure resulting in the increase of coercivity at low ordering temperature. Based on these results, fabrication of multilayered FePt nanodot arrays with 35 nm in pitch was attempted, and uniform nanodot arrays without deterioration of dots were successfully formed after post annealing process at 450 oC for 1 h. Subsequently, lowering the ordering temperature of FePt was attempted by addition of Cu into FePt films to form ternary FePt-Cu alloy. XRD patterns of FePt-Cu films after annealing at 450 oC for 1 h showed peaks of L10 ordered structure without elemental Cu peaks, and (001) peak of L10 structure was shifted to higher 2θ angle compared to FePt binary alloy, providing evidence that Cu was alloyed with FePt to shrink the lattice in the c-axis. In addition, perpendicular coercivity of FePt-Cu film was higher than that of FePt film at annealing temperature of 450 oC, indicating that reducing the ordering temperature was successfully attained by the addition of Cu to FePt. These results demonstrated a successful fabrication of uniform L10-FePt nanodot arrays with Tbit/in2 level density, by controlling the fine structure of FePt nanodot arrays by applying multilayered structure or addition of Cu to lower the ordering temperature. This work was financially supported in part by JSPS KAKENHI Grant Number 25249104. [1] T. Homma, S. Wodarz, D. Nishiie, T. Otani, S. Ge, and G. Zangari, Eletrochem. Soc. Trans., 64, 1-9 (2015) [2] B. D. Terris, and T. Thomson, J. Phys. D: Appl. Phys., 38, R199-R222 (2005) [3] Y. Endo, N. Kikuchi, O. Kitakami, and Y. Shimada, J. Appl. Phys., 89, 7065-7067 (2001) [4] T. Maeda, T. Kai, A. Kikitsu, T. Nagase, and J. Akiyama, Appl. Phys. Lett., 80, 2147-2149 (2002) Figure 1