Rapid Single Flux Quantum Logic Research Articles

Sequential Circuits Synthesis for Rapid Single Flux Quantum Logic Based on Finite State Machine Decomposition

Rapid Single Flux Quantum (RSFQ) logic is a promising technology to supersede Complementary metal-oxidesemiconductor (CMOS) logic in some specialized areas due to providing ultra-fast and energy-efficient circuits. To realize a large-scale integration design, electronic design automation (EDA) tools specialized for RSFQ logic are required due to the divergences in logic type, timing constraints, and circuit structure compared with CMOS logic. Logic synthesis is crucial in converting behavioral circuit description into a circuit netlist, typically combining combinational and sequential circuit synthesis. For the RSFQ logic, the sequential circuit synthesis is challenging, especially for non-linear sequential blocks with feedback loops. Thus, this paper presents a sequential circuit synthesis algorithm based on finite state machine (FSM) decomposition, which ensures design functionality, lowers costs, and improves the RSFQ circuit performance. Additionally, we present the synthesis processes of the feedback logic and the 2-bit counter to demonstrate how the proposed algorithm operates, and ISCAS89 benchmark circuits reveal our method’s ability to synthesize large-scale sequential circuits.

Striking a Good Balance Between Area and Throughput of RSFQ Circuits Containing Feedback Loops

Electronic design automation solutions are being developed to support the synthesis and physical design optimization of Rapid Single Flux Quantum (RSFQ) logic circuits with hundreds of thousands of logic cells. The clocked feature of synchronous RSFQ cells results in gate-level pipelined designs, requiring a large number of path-balancing D-flipflops (DFFs). In addition, one also faces the challenge of maintaining high throughput for RSFQ circuits containing feedback loops. To enforce the coincidence of the input and feedback patterns, one can apply a new input pattern every <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$L$</tex-math></inline-formula> cycles, where <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$L$</tex-math></inline-formula> is the length of the feedback loop. Consequently, the throughput of circuits with feedback loops is only <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$1/L$</tex-math></inline-formula> of the clock frequency. In this paper, we present two methods to improve the performance and area of RSFQ circuits, especially targeting circuits with feedback loops: (i) An area-oriented optimization method that removes the path-balancing DFFs by capturing and repeating input patterns. (ii) A throughput-oriented optimization method that enables an RSFQ circuit to receive and correctly process an input pattern every clock cycle. For a large circuit such as S526 in the ISCAS89 benchmark circuits, the circuit can initially receive an input pattern only every 9 cycles. As a result of applying our area-oriented optimization, the circuit admits 33% fewer logic cells while receiving input patterns every 11 cycles. Alternatively, our throughput-oriented optimization yields a circuit that can receive new input patterns on every cycle with nearly the same cell count.

Power Optimization of 50 GHz ERSFQ Circuits

The Energy-efficient Rapid Single Flux Quantum (ERSFQ) logic family offers zero-static power dissipation. Any ERSFQ circuit requires a feeding Josephson transmission line (FJTL), a relatively large active transmission line, which serves as an accurate voltage source. For proper operation, the FJTL needs to be continuously pumped at a frequency that is equal to or higher than the highest clock frequency of the ERSFQ circuit. We selected an on-chip pseudo-random binary sequence (PRBS) generator as the example circuit since it naturally facilitates quantitative measurements of operating bias margins in terms of bit error rate (BER). Using external and internal flux pump sources, we performed extensive experimental studies on BER for ERSFQ PRBS generators operating at clock frequencies up to 50 GHz. We paid special attention to the over-pumping regime, where the FJTL pump frequency is higher than the PRBS clock frequency and confirmed its superiority in improving BER. At 35.56 GHz clock frequency, a group of 4 PRBS generators and 4 individual FJTLs with the bias current ratio (BCR) equal to 1, had a BER lower than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> and bias margins of ±25% for internal and external flux pump sources over-pumping at 6.25% above clock frequency. The maximal operational clock frequency of a single ERSFQ PRBS generator with intrinsic pump source (+6.25% over-pumping) and BER <10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> was 49.53 GHz. We also focused on optimization of the FJTL's size to reduce the power consumption and the area occupied by the FJTL itself. All chips were fabricated at MIT-Lincoln Laboratory using the SFQ5ee fab node. Future steps required for better understanding of ERSFQ operation are discussed.

Adopting a Standard Track Routing Architecture for Next-Generation Hybrid AC/DC-Biased Logic Circuits

The adiabatic quantum-flux-parametron (AQFP) and rapid single flux quantum (RSFQ) logic families both provide distinct advantages for data processing using superconductor electronics. The development of next-generation AQFP-RSFQ hybrid logic circuits provides the opportunity to combine the benefits of both of these logic families. Adopting a standard track routing architecture for both AQFP and RSFQ layouts provides a unified framework for physical layout synthesis. We demonstrate a standard track routing architecture developed under the ColdFlux project and its implementation within AQFP. An additional advantage of the standard track routing architecture is that it provides a systematic way to overcome metal density requirements for modern-day fabrication processes. It also provides a methodical approach towards strategic moat placement for protection against unwanted flux trapping. Implementations of passive transmission line (PTL) connections and their physical placement for hybrid AQFP-RSFQ circuits are discussed. Several AQFP layouts for the ColdFlux project are redesigned to adopt the standard track routing architecture. Experimental simulation of moat performance is also presented.

$\upalpha$-Soma: Single Flux Quantum Threshold Cell for Spiking Neural Network Implementations

The main challenge for the hardware implementation of spiking neural networks is the design of a reliable neuron. Soma, which is the nucleus of the neuron, is a key part of such a design. More precisely, the soma design must accurately capture the excitatory/inhibitory interactions, intrinsic charge dynamics, refractory period, spike encoding, neuronal action potential, and output spike firing processes in order to mimic the corresponding biological processes. This work presents the design of an artificial soma cell with excitatory and inhibitory inputs, called <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\alpha$</tex-math></inline-formula> -Soma. The key idea is to design and employ a new interconnect cell, named <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\alpha$</tex-math></inline-formula> -cell, and integrate this cell within the proposed soma cell design. The design implementation utilizes the Rapid Single Flux Quantum (RSFQ) logic circuit technology. We demonstrate the correct functionality, high performance, and energy efficiency of the proposed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\alpha$</tex-math></inline-formula> -Soma cell with detailed circuit simulations under different spiking conditions.

Timing verification of rapid single flux quantum logic cell

Digital simulation is popular in rapid single flux quantum (RSFQ) large-scale integrated (LSI) circuit design for its high efficiency and low resource requirements. However, its reliability highly depends on the timing parameters extracted by analog simulation. Therefore, it is essential to establish a closed-loop verification process of the timing parameters, including delay, setup time (ST), and hold time (HT). Current verification methods, which utilize the ring oscillator, can only measure the delay of the SFQ cells and any circuit structure that can efficiently test ST and HT have yet to be reported. In this paper, we will introduce a timing verification method that can finely estimate the delay, ST, and HT of RSFQ sequential cells. The resolution of our unique test circuit is one Josephson junction delay in the Josephson transmission line (JTL). We also perform a closed-loop verification process between simulation and measurement by bringing the process parameters derived from the process control monitor (PCM) on the same batch back to the post-simulation. The process parameters contain Josephson junction critical current density JC and the sheet resistance of the Mo resistor RSh. With our method, the post-simulation analysis of several cells' delay, ST, and HT in the SIMIT-Nb03 cell library closely follows the test results. The consistency between the simulation and test indicates that the proposed timing verification method is efficient and reliable. With the measured timing parameters of cells, the reliability of the static timing analysis (STA) in circuit design before tape-out would be increased, which would improve the yield of circuits after fabrication.

QuCTS—Single-Flux Quantum Clock Tree Synthesis

Superconductive rapid single-flux quantum (RSFQ) is an emerging cryogenic technology, promising a significant boost in performance and ultralow power consumption. The operating frequency achieved by RSFQ digital integrated circuits is several orders of magnitude greater than traditional CMOS circuits. The fundamental difference of RSFQ circuits, however, renders traditional clocking techniques appropriate for CMOS unsuitable for RSFQ technology. Most RSFQ logic gates, such as AND and OR, are sequential in nature. The number of pipeline stages is therefore significantly greater in RSFQ as compared to CMOS, complicating the clock distribution network design process. This issue is further exacerbated with the need for splitters to achieve a fanout greater than one and the need for transmission lines rather than ordinary metallic wires as in CMOS. In this work, QuCTS—single-flux Quantum (SFQ) Clock Tree Synthesis—is presented. QuCTS utilizes a two-stage framework for synthesizing clock networks. In the clock skew scheduling stage, the clock signal arrival time of each gate is chosen to maximize the robustness of the circuit to timing variations. In the clock tree synthesis stage, the layout of the clock distribution network is generated based on a novel delay equilibration technique. QuCTS is the first clock tree synthesis tool for RSFQ circuits utilizing useful clock skew. The synthesized network satisfies the clock arrival time requirements while minimizing the associated overhead, such as the interconnect length and number of delay elements. The tool is validated on a set of benchmark circuits. In a prototypical case study, a clock tree is generated for the AMD2901 with 1049 clock sinks in 53 min while satisfying the clock arrival time.

Compact Stochastic Computing Circuits Using the Latching Function of RSFQ Circuits for Computing Polynomials

Stochastic computing (SC) is a method of expressing a numerical value by the appearance ratio of 1 in a bitstream to perform an operation. Rapid single flux quantum (RSFQ) circuits can handle SC naturally and operate at ultra-high speed. RSFQ SC circuits are suitable for applications tolerating error. This paper presents a design method of RSFQ SC circuits to calculate polynomials. Using the proposed design method, an internal circuit is designed to feed bitstreams of coefficients from bitstreams of constant to reduce large stochastic number generators. The method inserts storage elements to reduce correlations of signals, and thereby reduce the calculation error of the circuit. Additionally, it minimizes the number of inserted D flip-flops utilizing the latching function of gate inputs of RSFQ logic gates.

Pulse Interfaces and Current Management Techniques for Serially Biased RSFQ Circuits

As digital superconductor circuits based on Rapid Single Flux Quantum (RSFQ) logic scale up in complexity, so does the total current required to provide dc bias. Serial biasing (SB) is a promising solution that can be used to reduce the current by placing identical digital blocks on islands with isolated grounds and bias them sequentially. There are typically two implementations that are essential for the SB approach: the design of a driver-receiver pair (DRP) for inter-island pulse transport and the current management technique to handle the bias current flowing into and out of an island. While a DRP with good fidelity is essential for any serially biased circuit, the current management becomes critical for designs with relatively large bias current. In this paper, we address the latter. First, we propose a grapevine biasing scheme for serial bias current management. Second, we implement the technique using two exemplar circuits: the parallel counter and the digital decimation filter. We report the low and high speed test results up to 50 GHz for both circuits fabricated at MIT-LL in the SFQ5ee 10 kA&#x002F;2 &#x2126; fab node.

Implementation of an 8-bit bit-slice AES S-box with rapid single flux quantum circuits

Rapid single flux quantum (RSFQ) circuits are a kind of superconducting digital circuits, having properties of a natural gate-level pipelining synchronous sequential circuit, which demonstrates high energy efficiency and high throughput advantage. We find that the high-throughput and high-speed performance of RSFQ circuits can take the advantage of a hardware implementation of the encryption algorithm, whereas these are rarely applied to this field. Among the available encryption algorithms, the advanced encryption standard (AES) algorithm is an advanced encryption standard algorithm. It is currently the most widely used symmetric cryptography algorithm. In this work, we aim to demonstrate the SubByte operation of an AES-128 algorithm using RSFQ circuits based on the SIMIT Nb03 process. We design an AES S-box circuit in the RSFQ logic, and compare its operational frequency, power dissipation, and throughput with those of the CMOS-based circuit post-simulated in the same structure. The complete RSFQ S-box circuit costs a total of 42237 Josephson junctions with nearly 130 Gbps throughput under the maximum simulated frequency of 16.28 GHz. Our analysis shows that the frequency and throughput of the RSFQ-based S-box are about four times higher than those of the CMOS-based S-box. Further, we design and fabricate a few typical modules of the S-box. Subsequent measurements demonstrate the correct functioning of the modules in both low and high frequencies up to 28.8 GHz.

Application of Phase-Based Circuit Theory to RSFQ Logic Design

In contrast to transistor-based semiconductor circuits, there is currently no widely accepted formalized circuit theory or design methodology for superconductor rapid single flux quantum (RSFQ) logic circuits. Experienced designers intuitively consider flux loops, nodal phase, and branch currents when making design choices, but the lack of a formalized design process makes it difficult for inexperienced RSFQ circuit designers to construct a functioning logic cell without a reference. This results in new circuit designers, mostly recycling templates from published circuit designs without fully understanding why the circuits function as they do. Inexperienced RSFQ circuit designers often follow an iterative process where cell parameter values are adjusted, and the cell is run through electronic simulation engines until the desired functionality is reached. We propose the development of a formalized circuit design theory for RSFQ logic from first principles using phase-based circuit analysis. The circuit is designed using dc analysis to establish the dc operating point of the circuit. Phase-based analysis and simulation are then used to verify the dynamic circuit functionality. To demonstrate this method, we discuss examples for well-known RSFQ cells. We analyze the initial operating margins of these designs and discuss design accuracy and efficiency. Methods for current regulation to minimize current leakage between cells are discussed. We also present how this design methodology can be used to design new circuits such as an RSFQ XNOR cell. We investigate how an inverting (NOT) cell can be combined with other logic cells to minimize cell latency.

Logic Design and Simulation of a 128-b AES Encryption Accelerator Based on Rapid Single-Flux-Quantum Circuits

A 128-b rapid single-flux-quantum (RSFQ) Advanced Encryption Standard (AES) encryption accelerator based on bit-slice architecture is proposed for the first time. Unlike the traditional methods, the method of looking up only one 256-B table to complete the entire AES round function is proposed. The proposed method can reduce nearly 50% of the hardware cost compared to the traditional method. The simple lookup table, shift, and xor operations are used in the proposed accelerator where one 256-B table needs to be stored for lookup table operations. The RSFQ logic circuits of the proposed accelerator are designed and simulated at the logic level. It consists of 136 558 JJs based on the Open Dataset of CONNECT Cell Library for AIST ADP2. The simulation results show the proposed accelerator works correctly.

An Automatic Placement Algorithm for Superconducting Rapid Single-Flux-Quantum Logic Circuits

With the demand for data processing and storage increasing rapidly, the existing CMOS-based computing system is gradually unable to meet the amplification demand because of its high-power consumption. Due to high frequency and low power consumption, superconducting rapid single-flux-quantum (RSFQ) logic circuit technology is an attractive candidate. In this paper, we propose a novel placement method based on the layer layout. We layer the gates according to the logic level, which is the length of the longest path in terms of the number of clocked gates from any primary input (PI) of the circuit to the gate. Dummy gates are inserted so that any two adjacent layers can form a bipartite graph. Then the gates of each layer are reordered to minimize the half-perimeter wirelength (HPWL). Finally, the gates of each layer are assigned vertical positions to make the edges as straight as possible. The distance between adjacent layers is determined by the number of bending points of the edges between layers. We use several superconducting RSFQ logic circuits to evaluate the effectiveness of our proposed placement method, which uses HPWL and area as evaluation metrics. The experimental results show that compared with the Simulated Annealing (SA)-based placement method, the proposed approach can reduce the total HPWL and total area by an average of 77.77% and 57.56%, respectively.

A Timing Fault Model and an Efficient Timing Fault Simulation Method for Rapid Single-Flux-Quantum Logic Circuits

We examine digital behavior of faults caused by a change of the order of the pulse arrivals in Rapid Single-Flux-Quantum (RSFQ) logic circuits. Based on the timing fault model, we present a flow of automatic test pattern generation for testing digital RSFQ chips. As the test pattern generation repeatedly executes fault simulation, the scalability depends on computational cost of the simulation. We propose an efficient fault simulation method based on two ideas. First, we share computation for the fault-free circuit and faulty circuits as much as possible. Secondly, we exploit the pipelined behavior of RSFQ logic circuits to suppress computation for unnecessary signals. We have implemented our simulation method and obtained evaluation results to show that our method is effective for large circuits.

Design and implementation of bit-parallel RSFQ shift register memories

In this paper, a shift register (SR) memory based on rapid single flux quantum (RSFQ) logic for bit-parallel access is proposed. The memory cell changes from a row in the memory array to a column to increase the bit of data accessed per one clock cycle. The design of the 8 bit × 2 bit (8 × 2) memory is introduced. The memory consists of four parts: a SR memory array, an input buffer, an output buffer, and a controller, in which the controller is used to produce a control signal at a certain clock cycle specified by the address data. We have obtained the low speed test of the 8 × 2 memory fabricated by 6 kA cm−2 Nb process (SIMIT-Nb03), all bit-parallel access operations (write, read, clear and write, and read again) have been verified. We also simulated the 8 × 8 memory with data width expansion and obtained the maximum operating frequency of 34 GHz after the place and route with the SIMIT-Nb03 cell library. Based on the hierarchical storage, we have used the 8 × 8 memory as a basic block to construct large size of memory system, the access time and bandwidth have been evaluated. The bit-parallel memory shows higher bandwidth than bit-serial memory with the same capacity, especially for large capacity memory.

A Compact Interface Between Adiabatic Quantum-Flux-Parametron and Rapid Single-Flux-Quantum Circuits

Each superconductor logic family has distinct features and advantages. For instance, adiabatic quantum-flux-parametron (AQFP) circuits operate with very high energy efficiency, and rapid single-flux-quantum (RSFQ) circuits operate at very high clock frequencies. To build a hybrid system that combines the above advantages, we propose a compact interface between AQFP and RSFQ circuits that converts current signals in AQFP logic into flux signals in RSFQ logic using a non-adiabatic quantum-flux-parametron gate. Compared to a previously proposed AQFP/RSFQ interface, the proposed interface has far fewer Josephson junctions (4 vs. 11). We optimize the circuit parameters of the AQFP/RSFQ interface and demonstrate the interface at low speed as proof of concept. Furthermore, we demonstrate data propagation between AQFP circuits along a long passive transmission line via the AQFP/RSFQ interface at low speed to show that the AQFP/RSFQ interface can alleviate the interconnect length limit in AQFP circuits.

Reconfigurable Superconducting FFT Processor Using Bit-Slice Block Share Processing Unit

We have proposed a reconfigurable high speed and very economical Rapid Single Flux Quantum (RSFQ) superconducting logic design based on the Fast Fourier Transform (FFT) Processor. We have designed a 256 – point FFT processor with the help of a bit-slicing block sharing unit. RSFQ is one of the superconducting device logics comprises of Josephson Junction. The computation complexity of this superconducting FFT is less when the number of points increased. We have proposed three different designs depending on the split radix FFT, the bit-serial radix 2 FFT, and the mixed radix FFT algorithms. The proposed design will slice the 256 – point FFT into eight 32 – point FFT each and each 32 – point FFT is divided into eight 4 – point FFT each for the reduction in hardware cost. For complex multiplication, the computation complexity of our design will be less than N/2 Log2 N for the radix 2 algorithm based on the Block share processing Unit (BSPU) and further, it is reduced for split radix & mixed radix algorithms based on BSPU based RSFQ logic. Due to this, the speed of the processor is improvised compared to general FFT algorithm based semiconductor technology. we have computed and calculated the latency at 10 GHz for our designs. The main aim of this proposed design is to reduce the complex computation time and better performance of the processor with less hardware cost. This proposed design can furthermore continue to several N2 – point by using synchronous clock tree.

Design and Characterization of Track Routing Architecture for RSFQ and AQFP Circuits in a Multilayer Process

Place and route tools for synthesized superconductor logic circuits, either for dc-biased rapid single flux quantum (RSFQ) or ac-biased adiabatic quantum flux parametron (AQFP), are required to automate the design of complex logic circuits. For hand-crafted circuit layout, logic cells, clock, and bias distribution, and signal interconnect can be optimized for tight fit and the adherence to design rules. For complex systems with thousands of logic gates, a hand-crafted approach is not efficient and automated place and route tools are a necessity. Such tools require logic cell layout for placement with a minimum set of rules, followed by an interconnect design that allows maximum routability and strict adherence to layer fill requirements. In this article, we present the design and characterization of a routing architecture that allows rule-based automated place and route for both RSFQ and AQFP logic families. We show that a layout tile size of 10 × 10 μm can be designed to accommodate all design rules for layout fill densities, passive transmission line routing, bias current distribution, and the vias needed to stitch multiple ground planes and provide shielded signal and bias tracks. We also characterize the performance of the layout architecture in terms of transmission line parameters and bias current coupling with powerful simulation tools developed for the SuperTools project. The result is a track layout that doubles as chip fill, is now used for integrated circuit layout under SuperTools and is also applicable to any similar fabrication process with at least eight superconductor metal layers.

An Effective and Efficient Automatic Test Pattern Generation (ATPG) Paradigm for Certifying Performance of RSFQ Circuits

Rapid single flux quantum (RSFQ) logic, based on Josephson junctions (JJs), is seeing a resurgence as a way for providing high performance in the era beyond the end of physical scaling of complementary metal-oxide-semiconductor (CMOS). Due to its use of fabrication processes with large feature sizes, the defect density for RSFQ is lower than its CMOS counterpart. Hence, process variations and other RSFQ-specific nonidealities are major causes of chip failures. Because of the nature of its quantized pulse-based operation, even highly distorted pulses are interpreted logically correctly by cells, but the timings are affected. Therefore, timing verification and delay testing increase in importance in RSFQ. Our goal is to ensure that designs and fabricated chips provide desired performance. To achieve this goal, we propose new methods and tools for timing verification and delay testing of fully path balanced RSFQ logic circuits that use concurrent-flow clocking scheme. We address several radically new phenomena in the RSFQ technology, especially the existence of single-pattern delay tests and the need to propagate delayed values via multiple pipeline stages. We then characterize cells under process variations and identify delay excitation conditions, sensitization conditions, and conditions for propagation of the logic errors caused by timing violations due to process variations. We then propose a completely new paradigm for automatic test pattern generation (ATPG) which utilizes these new phenomena to select multicycle paths as targets and to generate test patterns that are guaranteed to excite the worst-case delay along each target multicycle path. Finally, we present theoretical proofs and Monte Carlo simulation results for benchmark circuits under process variations to demonstrate that the patterns generated by our new ATPG are effective (invoke maximum delays of target multicycle paths) and efficient (require small numbers of patterns).

Static Timing Analysis (STA) with Timing Bleed: Certifying Much Higher Performance for Rapid Single Flux Quantum (RSFQ) Logic

Josephson-junction based technologies, such as RSFQ, are receiving growing investments due to their high speeds and low power.As the time interval between the data input and the clock becomes smaller, clock-to-Q delay of a flip-flop increases. In conventional timing analysis, setup time is defined as the interval where clock-to-Q delay increases by 10%. This allows the pipeline to be divided into separate stages and STA to be performed independently for each stage.However, since RSFQ is pipelined at gate-level, setup time is a significant portion of the clock period and makes this timing constraint extremely conservative. Instead, we define setup time based on the probability of causing a logic error and develop a new STA method that allows larger increases in clock-to-Q delay, i.e., timing bleed, whenever the data input arrives late. We present results of simulations for benchmark circuits with process variations to demonstrate that our new method certifies much higher speeds for RSFQ logic.