Random Access Memory Research Articles

Random access memory page caching: a strategy for enhancing shared virtual memory multicomputer systems performance

This study examines a modified approach to optimizing the performance of support vector machine (SVM)-type multicomputer systems through a distinct type of caching method that allocates space in the random access memory (RAM) of a computing node for caching pages. The article extensively describes research on enhancing the performance of the SVM system through memory page caching in RAM at the hardware level by implementing the SVM system based on field-programmable gate arrays (FPGA). A systematic comparative evaluation highlights a discernible enhancement in system performance relative to systems not equipped with the revised caching algorithm. These findings could prove instrumental for subsequent studies focused on optimizing the performance of SVM systems, providing empirical data to inform future investigations and potential applications in multicomputer system performance enhancement.

Analysis of the parasitic capacitance effects on the layout of latch-based sense amplifiers for improving SRAM performance

Static random-access memory (SRAM) technology is utilized in designing cache memory to enhance the processing performance of computer systems. The sense amplifier (SA) circuit, a crucial component of memory design, significantly impacts data access time and power consumption. In comparison to conventional differential sense amplifiers (DSA) designs, latch-based sense amplifiers (LSA) used in memory-based computing platforms have specific requirements, including robust noise resistance in harsh working environments and low power consumption, particularly for internet of thing (IoT) embedded computing applications. However, the performance can be degraded due to various factors that arise during the layout, such as conductor resistance or the development of parasitic capacitance. Therefore, this study employs low-voltage 22 nm UMC CMOS technology for LSA design layout and analyzes the factors influencing design performance post-layout process. Layout design optimization techniques are applied to mitigate the impact of parasitic capacitance on important signal lines such as data line/data line bar (DLL/DLLB). Based on the performance analysis results, it is possible to achieve a reduction in power consumption of up to 15% and a 5% decrease in read delay time by implementing circuit layout LSA design optimization techniques.

Nanocrystal Materials for Resistive Memory and Artificial Synapses: Progress and Prospects.

Resistive random-access memory (RRAM) is considered to be the most promising next-generation non-volatile memory because of its low cost, low energy consumption, and excellent data storage characteristics. However, the on/off (SET/RESET) voltages of RRAM are too random to replace the traditional memory. Nanocrystals (NCs) offer an appealing option for these applications since they combine excellent electronic/optical properties and structural stability and can address the requirements of low-cost, large-area, and solution-processed technologies. Therefore, the doping NCs in the function layer of RRAM are proposed to localize the electric field and guide conductance filaments (CFs) growth. The purpose of this article is to focus on a comprehensive and systematical survey of the NC materials, which are used to improve the performance of resistive memory (RM) and optoelectronic synaptic devices and review recent experimental advances in NC-based neuromorphic devices from artificial synapses to light-sensory synaptic platforms. Extensive information related to NCs for RRAM and artificial synapses and their associated patents were collected. This review aimed to highlight the unique electrical and optical features of metal and semiconductor NCs for designing future RRAM and artificial synapses. It was demonstrated that doping NCs in the function layer of RRAM could not only improve the homogeneity of SET/RESET voltage but also reduce the threshold voltage. At the same time, it could still increase the retention time and provide the probability of mimicking the bio-synapse. NC doping can significantly enhance the overall performance of RM devices, but there are still many problems to be solved. This review highlights the relevance of NCs for RM and artificial synapses and also provides a perspective on the opportunities, challenges, and potential future directions.

A Simple, Robust, and Versatile MATLAB Formulation of the Dynamic Memdiode Model for Bipolar-Type Resistive Random Access Memory Devices

Modeling in an emerging technology like RRAM devices is one of the pivotal concerns for its development. In the current bibliography, most of the models face difficulties in implementing or simulating unconventional scenarios, particularly when dealing with complex input signals. In addition, circuit simulators like Spice require long running times for high-resolution results because of their internal mathematical implementation. In this work, a fast, simple, robust, and versatile model for RRAM devices built in MATLAB is presented. The proposed model is a recursive and discretized version of the dynamic memdiode model (DMM) for bipolar-type resistive switching devices originally implemented in LTspice. The DMM model basically consists of two coupled equations: one for the current (non-linear current generator) and a second one for the memory state of the device (time-dependent differential equation). This work presents an easy-to-use tool for researchers to reproduce the experimental behavior of their devices and predict the outcome from non-trivial experiments. Three study cases are reported, aimed at capturing different phenomenologies: a frequency effect study, a cycle-to-cycle variability fit, and a stochastic resonance impact analysis.

Large Field-like Spin-Orbit Torque and Enhanced Magnetization Switching Efficiency Utilizing Amorphous Mo.

Spin-orbit torque magnetic random access memory (SOT-MRAM) has great promise in high write speed and low power consumption. Mo can play a vital role in constructing a CoFeB/MgO-based MRAM cell because of its ability to enhance the perpendicular magnetic anisotropy (PMA), thermal tolerance, and tunneling magnetoresistance. However, Mo is often considered as a less favorable candidate among SOT materials because of its weak spin-orbit coupling. In this study, we experimentally investigate the SOT efficiencies in Mo/CoFeB/MgO heterostructures over a wide range of Mo thicknesses and temperature. Decent damping-like SOT efficiency |ξDL| = 0.015 ± 0.001 and field-like SOT efficiency |ξFL| = 0.050 ± 0.001 are found in amorphous Mo. The ξFL/ξDL ratio is greater than 3. Furthermore, efficient current-induced magnetization switching is demonstrated with the critical current density comparable with heavy metal Ir and W. Our work reveals new understanding and possibilities for Mo as both an SOT source component and PMA buffer layer in the implementation of SOT-MRAMs.

Exploration and optimization of novel replacement and prefetching strategies for inefficiencies of advanced MRAM-based hybrid cache systems

Abstract With the emergence of cutting-edge hardware systems such as cloud computing, edge computing, and on-chip neural network accelerators, how to design advanced memory strategies to substitute the traditional ones for maximizing the potential performance of non-volatile memory (NVM) under the existing hardware conditions, has become an urgent research issue for both academia and industrial communities. It is promising and innovative to improve computer systems in the layer of data exchanging with the emerging advanced semiconductor devices. In the paper, to address the inefficiencies of write-intensive, high power consumption, low hit rate and so on, which exist in hybrid Magnetic Random Access Memory (MRAM) cache systems, three novel cache replacement strategies and two cache prefetching strategies are put forward. The proposed triple novel replacement strategies, including historical frequency and time judgments, duplicate data-aware deletion, and dynamic relevance factors computing, can be utilized to compensate for the shortcomings of the traditional Least Recently Used (LRU) replacement strategy, respectively. In the two novel prefetching strategies, region distribution parameters and Listnet ranking network are imported into the caching process, respectively, to achieve optimized hitting performance. The simulation results demonstrate that the proposed replacement strategies can achieve up to 61.76%, 84.91%, 56.49%, and 53.21% optimization of write count, hit rate, dynamic power, and IPC compared to the conventional one. The proposed prefetching strategy can achieve up to 91.27%, 49.25% hit rate and IPC optimization. Meanwhile, the synthetic evaluation of the replacement and prefetching strategies are elaborated in the paper, including multi-core characteristics, information entropy, interplays and the performance constraints between replacement and prefetching mechanism, which would facilitate more credible ideas for future memory inefficiencies management and strategy design.

Stabilization of Morphotropic Phase Boundary in Hafnia via Microwave Low‐Temperature Crystallization Process for Next‐Generation Dynamic Random Access Memory Technology

The morphotropic phase boundary (MPB), which arises from the combination of antiferroelectric and ferroelectric phases, demonstrates the highest dielectric constant (κ) compared to other phases. This emphasizes its potential as a leading contender for dielectric films in future dynamic random access memory (DRAM) capacitors. MPB‐based high‐κ materials using hafnia have shown a trade‐off between equivalent oxide thickness (EOT) and leakage current density (Jleak) when the crystallization temperature increases with scaling the thickness. Herein, a microwave annealing (MWA) method that can achieve low‐temperature crystallization below 350 °C is employed. The purpose of this method is to mitigate the trade‐off relationships and achieve the strict criteria of current DRAM capacitors. These criteria include low EOT (less than 4 Å) and Jleak (less than 10−7 A cm−2 at 0.8 V) characteristics. The MWA is capable of relatively low‐temperature annealing by supplying energy to the films through both thermal energy and dipole vibration energy. As a result, a record‐low EOT of 3.76 Å and a low leakage current characteristic of 4.2 × 10−8 A cm−2 at 0.8 V are achieved concurrently. It is confident that the research can be important in addressing the challenges associated with reducing the size of next‐generation DRAM capacitors.

NEM-GNN: DAC/ADC-less, Scalable, Reconfigurable, Graph and Sparsity-Aware Near-Memory Accelerator for Graph Neural Networks

Graph neural networks (GNNs) are of great interest in real-life applications such as citation networks and drug discovery owing to GNN’s ability to apply machine learning techniques on graphs. GNNs utilize a two-step approach to classify the nodes in a graph into pre-defined categories. The first step uses a combination kernel to perform data-intensive convolution operations with regular memory access patterns. The second step uses an aggregation kernel that operates on sparse data having irregular access patterns. These mixed data patterns render CPU/GPU-based compute energy-inefficient. Von Neumann based accelerators like AWB-GCN [ 7 ] suffer from increased data movement, as the data-intensive combination requires large data movement to/from memory to perform computations. ReFLIP [ 8 ] performs resistive random access memory based in-memory (PIM) compute to overcome data movement costs. However, ReFLIP suffers from increased area requirement due to dedicated accelerator arrangement, and reduced performance due to limited parallelism and energy due to fundamental issues in ReRAM-based compute. This article presents a scalable (non-exponential storage requirement), DAC/ADC-less PIM-based combination, with (i) early compute termination and (ii) pre-compute by reconfiguring SOC components. Graph and sparsity-aware near-memory aggregation using the proposed compute-as-soon-as-ready (CAR) broadcast approach improves performance and energy further. NEM-GNN achieves ∼80–230x, ∼80–300x, ∼850–1,134x, and ∼7–8x improvement over ReFLIP, in terms of performance, throughput, energy efficiency, and compute density.

FASA-DRAM: Reducing DRAM Latency with Destructive Activation and Delayed Restoration

DRAM memory is a performance bottleneck for many applications, due to its high access latency. Previous work has mainly focused on data locality, introducing small but fast regions to cache frequently accessed data, thereby reducing the average latency. However, these locality-based designs have three challenges in modern multi-core systems: (1) inter-application interference leads to random memory access traffic, (2) fairness issues prevent the memory controller from over-prioritizing data locality, and (3) write-intensive applications have much lower locality and evict substantial dirty entries. With frequent data movement between the fast in-DRAM cache and slow regular arrays, the overhead induced by moving data may even offset the performance and energy benefits of in-DRAM caching. In this article, we decouple the data movement process into two distinct phases. The first phase is Load-Reduced Destructive Activation (LRDA), which destructively promotes data into the in-DRAM cache. The second phase is Delayed Cycle-Stealing Restoration (DCSR), which restores the original data when the DRAM bank is idle. LRDA decouples the most time-consuming restoration phase from activation, and DCSR hides the restoration latency through prevalent bank-level parallelism. We propose FASA-DRAM, incorporating destructive activation and delayed restoration techniques to enable both in-DRAM caching and proactive latency-hiding mechanisms. Our evaluation shows that FASA-DRAM improves the average performance by 19.9% and reduces average DRAM energy consumption by 18.1% over DDR4 DRAM for four-core workloads, with less than 3.4% extra area overhead. Furthermore, FASA-DRAM outperforms state-of-the-art designs in both performance and energy efficiency.

Nociceptor‐Enhanced Spike‐Timing‐Dependent Plasticity in Memristor with Coexistence of Filamentary and Non‐Filamentary Switching

AbstractIn the era of big data, traditional computing architectures face limitations in handling vast amounts of data owing to the separate processing and memory units, thus causing bottlenecks and high‐energy consumption. Inspired by the human brain's information exchange mechanism, neuromorphic computing offers a promising solution. Resistive random access memory devices, particularly those with bilayer structures like Pt/TaOx/TiOx/TiN, show potential for neuromorphic computing owing to their simple design, low‐power consumption, and compatibility with existing technology. This study investigates the synaptic applications of Pt/TaOx/TiOx/TiN devices for neuromorphic computing. The unique coexistence of nonfilamentary and filamentary switching in the Pt/TaOx/TiOx/TiN device enables the realization of reservoir computing and the functions of artificial nociceptors and synapses. Additionally, the linkage between artificial nociceptors and synapses is examined based on injury‐enhanced spike‐time‐dependent plasticity paradigms. This study underscores the Pt/TaOx/TiOx/TiN device's potential in neuromorphic computing, providing a framework for simulating nociceptors, synapses, and learning principles.

Improvement of synaptic property of GeSe based CBRAM by engineering the deposition condition of switching matrix

A study of effect of deposition condition of germanium selenide (GeSe) switching layer to Conductive bridging random access memory (CBRAM) device property was conducted to enhance memory property and synaptic property. The devices deposited under the varied deposition conditions were analyzed by current distribution of each state (Low-resistance state [LRS], High-resistance state [HRS]), conduction mechanism analysis, chemical analysis, and synaptic analysis according to pulse conditions. When we deposited switching layer at lowest power (40 W), more Ag ions move to the switching matrix and make lower operation voltage. But there were some disadvantages, which were worst distribution and higher HRS current, less memory window, nonlinear and rapid increase of potentiation process. Conversely, although the device deposited at high voltage increased the operating voltage, but there are improvements, such as the highest memory window and improved linearity of potentiation. The best sample was conducted the synaptic property measurement, and the device successfully mimicked the biological synaptic property with the good linearity of potentiation and depression, spike-rate dependent plasticity (SRDP) and spike-timing dependent plasticity (STDP) properties.

A Study on Unified Modelling Approach for Memristor: Next Generation Semiconductor Devices

This research investigates the voltage-current (V-I) characteristics of three distinct memristor models, each representing a unique composition and behaviour. The model, denoted as TiN-TiOx-HfOx-Pt-Bilayered Memristor model, is a compact representation designed for Metal–Oxide Resistive Random Access Memory (RRAM). Matlab tool is used for the simulation to analyse V-I characteristics of Memristor. Through comprehensive analysis and simulations, we aim to provide a detailed insight into the intrinsic behaviours of the memristor models. Understanding the V-I characteristics of these models is crucial for their potential applications in emerging memory technologies. This Study elaborate the mathematical modelling of memristor with the outcome untuned V-I Characteristics - DC Switching characteristics. The findings contribute to the broader field of memristor research, fostering advancements in electronic memory devices and computational systems

Orientation-dependent tunneling electroresistance in Pt/Pb(Zr,Ti)O3/Nb:SrTiO3 ferroelectric tunnel junctions

Orientation anisotropy is a well-known essential character for polarization characteristics of ferroelectric materials, which has been widely investigated in conventional ferroelectric random access memories. In this work, we study the effects of orientation on the tunneling electroresistance (TER) of ferroelectric tunnel junctions (FTJs). Rhombohedral Pb(Zr[Formula: see text],Ti[Formula: see text])O3 (PZT) that has the polar axis along the [Formula: see text] orientation is adopted as potential barriers and two kinds of FTJs that are composed of (001)- and (111)-oriented PZT barriers and Nb:SrTiO3 (Nb:STO) electrodes, respectively, are fabricated. The (111)-oriented Pt/PZT/Nb:STO FTJ exhibits a giant ON/OFF ratio of [Formula: see text], about 30 times that of the (001)-oriented device, due to the lowered PZT barrier in the ON state and the widen Schottky barrier in the OFF state based on current and capacitance analyses. In addition, compared to the (001)-oriented device, the (111)-oriented FTJ shows a sharper and faster switching between the ON and OFF states according to the nucleation-limited-switching dynamics model, giving rise to good linearity in memristive behaviors for synaptic plasticity and reliable retention and endurance properties for the resistance switching. The improved TER properties are ascribed to larger effective polarizations and 180∘ switching in the (111)-oriented PZT barrier. These results facilitate the design and fabrication of high-performance FTJ devices with the optimization of crystallographic orientation and polarization switching characteristics.

Tiny machine learning empowers climbing inspection robots for real-time multiobject bolt-defect detection

Ensuring the structural integrity of steel construction is critical, necessitating effective methods for detecting bolt defects. Traditional inspection methods are reliable but require significant labor and struggle with the accessibility of complex structures. This research introduces a real-time bolt-defect detection system that integrates tiny machine learning (TinyML) with a magnetic climbing robot to enhance inspection efficiency and scope. The system employs the faster objects, more objects (FOMO) algorithm optimized for edge computing on microcontrollers. This approach enables accurate bolt identification, including normal, loose, and missing bolts. The average system accuracy is 82%, with precision and recall values from 0.57 to 0.89 and 0.67 to 0.87, respectively. The system demonstrates balanced detection, evidenced by an F1 score improvement of up to 62%. The FOMO model displays compelling performance on defect detection tasks, achieving an F1 score of approximately 75%, outperforming the MobileNetV2 Single Shot Multibox Detector with Feature Pyramid Networks Lite and You Only Look Once version 5 small. The efficiency of the FOMO model is highlighted by its low hardware requirements at less than 0.1 MB of flash memory and 893.8 KB of random access memory for the 32-bit floating-point data format and is reduced for the 8-bit integer data format, with inference times of 142 ms and 86 ms, respectively. These findings contrast with the higher resource demands and slower inference time of the compared models, indicating the suitability of the FOMO model for low-capacity microcontrollers and its feasibility for real-time applications. The performance analysis across scenarios confirms the high precision (average 0.77) and recall (average 0.76), validating the robustness of the model in diverse environmental conditions. The system offers an advancement over traditional bolt-defect detection methods in accuracy and efficiency by leveraging TinyML and a magnetic climbing robot, setting new benchmarks for real-time inspection technology. The quantitative results underscore the performance of the system, presenting a scalable, cost-effective solution for improving the safety and durability of steel structures.

TEFLON: Thermally Efficient Dataflow-Aware 3D NoC for Accelerating CNN Inferencing on Manycore PIM Architectures

Resistive random-access memory (ReRAM) based processing-in-memory (PIM) architectures are used extensively to accelerate inferencing/training with convolutional neural networks (CNNs). Three-dimensional (3D) integration is an enabling technology to integrate many PIM cores on a single chip. In this work, we propose the design of a thermally efficient dataflow-aware monolithic 3D (M3D) NoC architecture referred to as TEFLON to accelerate CNN inferencing without creating any thermal bottlenecks. TEFLON reduces the Energy-Delay-Product (EDP) by 4 2\% , 46\% , and 45 \% on an average compared to a conventional 3D mesh NoC for systems with 36-, 64-, and 100-PIM cores respectively. TEFLON reduces the peak chip temperature by 25 K and improves the inference accuracy by up to 11 \% compared to sole performance-optimized SFC-based counterpart for inferencing with diverse deep CNN models using CIFAR-10/100 datasets on a 3D system with 100-PIM cores.

Theoretico-experimental analysis of bistability in the oscillatory response of a TaOx ReRAM to pulse train stimuli

Fading memory is the capability of a physical system to approach a unique asymptotic behaviour, irrespective of the initial conditions, when stimulated by an input from a certain class. Standard stimuli from the AC periodic class typically induce fading memory effects in non-volatile memristors, as uncovered for the first time back in 2016. Very recently, a deep investigation of resistance switching phenomena in a TaOx resistive random access memory cell revealed the capability of the nano-device to exhibit one of two possible oscillatory behaviours, depending upon the initial condition, when subject to a particular periodic excitation. This interesting finding was, however, left unexplained. Bistability is the simplest form of local fading memory. In a system, endowed with local fading memory under a given stimulus, the initial condition does not affect the long-term behaviour of the state as long as it is drawn from the basin of attraction of either of the distinct coexisting state-space attractors (two limit cycles for the periodically forced memristor acting as a bistable oscillator). Here, the history of the system, encoded in the initial condition, is, thus, erasable only locally through ad hoc stimulation. Motivated by the discovery of local history erase effects in our resistive random access memory cell, this study applies a powerful system-theoretic tool, enabling the analysis of the response of first-order systems to square pulse train-based periodic stimuli, known as the time-average state dynamic route, to an accurate physics-based mathematical model, earlier fitted to the nano-device, to determine a strategy for specifying the parameters of an excitation signal, consisting of the sequence of two square pulses of opposite polarity per period so as to induce various forms of monostability or multistability in the non-volatile memristor. In particular, as an absolute novelty in the literature, experimental measurements validate the theoretical prediction on the capability of the device to operate as one of two distinct oscillators, depending upon the initial condition, under a specific pulse train excitation signal. The coexistence of multiple oscillatory operating modes in the periodically forced resistive random access memory cell, an example par excellence of their unique non-linear dynamics, may inspire the development and circuit implementation of novel sensing and mem-computing paradigms.

Measuring Electrical Resistivity at the Nanoscale in Phase-Change Materials.

Electrical resistivity is the key parameter in the active regions of many current nanoscale devices, from memristors to resistive random-access memory and phase-change memories. The local resistivity of the materials is engineered on the nanoscale to fit the performance requirements. Phase-change memories, for example, rely on materials whose electrical resistance increases dramatically with a change from a crystalline to an amorphous phase. Electrical characterization methods have been developed to measure the response of individual devices, but they cannot map the local resistance across the active area. Here, we propose a method based on operando electron holography to determine the local resistance within working devices. Upon switching the device, we show that electrical resistance is inhomogeneous on the scale of only a few nanometers.

Spin-Orbit Torque Vector Quantification in Nanoscale Magnetic Tunnel Junctions.

Spin-orbit torques (SOT) allow ultrafast, energy-efficient toggling of magnetization state by an in-plane charge current for applications such as magnetic random-access memory (SOT-MRAM). Tailoring the SOT vector comprising of antidamping (TAD) and fieldlike (TFL) torques could lead to faster, more reliable, and low-power SOT-MRAM. Here, we establish a method to quantify the longitudinal (TAD) and transverse (TFL) components of the SOT vector and its efficiency χAD and χFL, respectively, in nanoscale three-terminal SOT magnetic tunnel junctions (SOT-MTJ). Modulation of nucleation or switching field (BSF) for magnetization reversal by SOT effective fields (BSOT) leads to the modification of SOT-MTJ hysteresis loop behavior from which χAD and χFL are quantified. Surprisingly, in nanoscale W/CoFeB SOT-MTJ, we find χFL to be (i) twice as large as χAD and (ii) 6 times as large as χFL in micrometer-sized W/CoFeB Hall-bar devices. Our quantification is supported by micromagnetic and macrospin simulations which reproduce experimental SOT-MTJ Stoner-Wohlfarth astroid behavior only for χFL > χAD. Additionally, from the threshold current for current-induced magnetization switching with a transverse magnetic field, we show that in SOT-MTJ, TFL plays a more prominent role in magnetization dynamics than TAD. Due to SOT-MRAM geometry and nanodimensionality, the potential role of nonlocal spin Hall spin current accumulated adjacent to the SOT-MTJ in the mediation of TFL and χFL amplification merits to be explored.

Investigation on self-rectifying properties of Pt/HfO2/Ti with rivet-like structure based on ALD conformal technology

This work explores an architecture for nonvolatile resistive random-access memory (RRAM) systems. The study proposes a self-rectifying RRAM device utilizing a two-terminal 1R selector that harmonizes the gate control efficacy of transistors with the inherent simplicity of diode structures. A rivet-like HfO2-based RRAM array is meticulously constructed through atomic layer deposition (ALD), aiming to enhance device performance and retention stability. The conformal fabrication technique of ALD method is critical in achieving uniform coverage of isolation layers and precise electrode placement, which is instrumental in the fabrication of high-performance memory cells. Empirical analyses indicate significant improvements in rectification and ON/OFF ratios compared to existing RRAM models, bolstered by compatibility with established CMOS processes. It reveals that these advances are conducive to scalable, high-density memory integration, positioning the RRAM as a viable contender for future computational applications that require high efficiency and neuromorphic computing capabilities.

Efficient magnetization switching induced by spin–orbit torque in perpendicularly magnetized Mn1+xCo2−xAl Heusler alloys

Perpendicularly magnetized Co-based Heusler alloys are promising candidates in high-performance spintronic devices. However, there is a contradiction between thermal stability and damping-like spin–orbit torque (SOT) efficiency in Co-based Heusler alloys with interface-induced perpendicular magnetic anisotropy (PMA). Here, we present epitaxially grown perpendicularly magnetized Mn1+xCo2−xAl (MCA) Heusler alloys through tetragonal distortion. Ferrimagnetism and distortion-induced PMA are obtained in MCA Heusler alloys. A large effective spin Hall angle (θeff) up to 0.33 is experimentally demonstrated in Pt/MCA bilayers, markedly surpassing that in conventional Pt/FM bilayers. Consequently, SOT-induced efficient magnetization switching is realized in Pt/MCA bilayers, with a critical switching current density (Jc) as low as 4 × 107 A/cm2. The large θeff and high SOT efficiency would be attributed to the staggered magnetic exchange torques in the ferrimagnetic MCA Heusler alloys. These findings demonstrate that perpendicularly magnetized ferrimagnetic MCA Heusler alloys are highly promising for high-density SOT-magnetic random-access memory with superior thermal stability and low power consumption.