Random Access Memory Array Research Articles

Fabrication of dynamic oxide semiconductor random access memory with 3.9 fF storage capacitance and greater than 1 h retention by using c-axis aligned crystalline oxide semiconductor transistor with L of 60 nm

A dynamic oxide semiconductor random access memory (DOSRAM) array that achieves reduction in storage capacitance (Cs) and decrease in refresh rate has been fabricated by using a c-axis aligned crystalline oxide semiconductor (CAAC-OS) transistor (L = 60 nm) with an extremely low off-state current. We have confirmed that this array, composed of cells that include a CAAC-OS transistor with W/L = 40 nm/60 nm using InGaZnO and a 3.9 fF storage capacitor, operates with write and read times of 5 ns. Therefore, DOSRAM can ensure sufficient Cs while maintaining operation speed comparable to that of dynamic random access memory (DRAM). We have found that the read signal voltage of DOSRAM is changed by approximately 30 mV after 1 h at 85 °C. Thus, DOSRAM is a promising replacement for DRAM.

A Variation-Aware Preferential Design Approach for Memory-Based Reconfigurable Computing

Static random access memory arrays designed in sub-90-nm technologies are highly vulnerable to process variation-induced read/write/access failures. In memory-based reconfigurable computing frameworks, which use large high-density memory array, such failures lead to incorrect execution of mapped applications. It causes loss in quality of service (QoS) for digital signal processing (DSP) applications. In this paper, we analyze the effect of parameter variations on QoS in a memory-based reconfigurable computing framework. Next, we propose a preferential design approach at both application mapping and circuit level, which can significantly improve QoS and yield under large parameter variations. The proposed application mapping process considers the reliability map of a memory array and maps the important components with respect to QoS to more reliable memory blocks under performance constraint. At circuit level, we exploit the read-dominant memory access pattern to skew the memory cells for better read stability leading to improved QoS. Such a architecture/circuit codesign approach can also tolerate increased failure rate at low operating voltage, thus facilitating low-power operation. The effect of the approach is studied for two common DSP applications, namely discrete cosine transform and finite-impulse response (FIR) filter. The simulation results for FIR application show 45% improvement in power at iso-QoS and 47% in yield for a target peak signal to noise ratio at 45-nm technology.

Endurance Enhancement by Soft Forming Algorithm on AlO<sub><italic>x</italic></sub>/WO<sub><italic>y</italic></sub> Resistive Switching Memory Array

A new soft forming algorithm, proposed in this letter, is demonstrated to improve endurance of an AlO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /WO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">y</sub> bilayer resistive random access memory array by two orders of magnitude. Relative to the conventional strong forming algorithm, soft forming creates a thinner conductive filament (CF) by applying voltage pulses that have narrower widths and lower amplitude. The mechanism can be explained by a CF model. soft forming algorithm is beneficial to form a thinner CF, which contains more movable oxygen vacancies (Vo) than that is formed by strong forming method. The rupture of thinner CF requires less movable oxygen ions (O <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2-</sup> ). Consequently, exhaustion of movable Vo/O <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2-</sup> slows down and the number of set/reset cycles is increased, which improves endurance of the array.

Via Diode in Cu Backend Process for 3D Cross-Point RRAM Arrays

In this paper, a fully logic compatible via diode is developed for high-density resistive random access memory (RRAM) array applications. This novel via diode is realized by advanced 28nm CMOS technology with Cu damascene via. The device is stacked between a top Cu via and a bottom Cu metal with a composite layer of TaN/TaON based dielectric film. An asymmetric current-voltage characteristic in this MIM structure provides a forward/reverse current ratio up to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> . In a cross-point RRAM array, the suppression of sneak current path by incorporating this via diode enables array size to be greatly expended. Via diode provides an excellent solution for high-density embedded nonvolatile memory applications in the nano-scale CMOS technology.

Low Temperature Processed Two-Transistor- Two-Capacitor-Based Ferroelectric Random Access Memory

We have demonstrated a low temperature fully integrated process for a ferroelectric random access memory array for potential flexible electronics applications. The memory cell is based on a two-transistor-two-capacitor structure, with cadmium sulfide as the semiconductor material for n-channel thin-film transistors, and poly(vinylidene fluoride-trifluoroethylene) copolymer as the ferroelectric material for capacitors. At VDD = 5 V, a voltage difference of ~1 V between the two states (0 and 1) is achieved at the output of the sense amplifier.

A Low Power Localized 2T1R STT-MRAM Array With Pipelined Quad-Phase Saving Scheme for Zero Sleep Power Systems

The high leakage power due to process nodes scaling down has been one of the critical issues in CMOS circuits, especially the sleep power critical systems. The conventional retention CMOS register based approaches cannot fully address the high standby energy issue in long time standby systems. The recent non-volatile Flip-Flop (nvFF) based approaches may achieve zero sleep power consumption, but still face the challenges of high saving power and area overhead, and low data reliability. This paper presents a new resistive Non-Volatile Memory (NVM) based circuit architecture with zero leakage power dissipation. It stores the states of the registers in the localized spin-torque-transfer magnetic random access memory (STT-MRAM) array through scan chains, which has reduced by more than 20% sleep energy than conventional nvFF schemes, and saved by more than 99.8% sleep energy compared to the retention CMOS register based approaches when the sleep time is longer than 1 s. Moreover, the proposed pipelined quad-phase saving scheme maximizes the saving speed, while reduces the peak saving current.

Design and Optimization of Nonvolatile Multibit 1T1R Resistive RAM

Memristor-based random access memory (RAM) is being explored as a potential replacement for flash memory to sustain the historic trends in the improvement of density, access time, and energy consumption of nonvolatile memory. In this paper, we present the detailed functionality of multibit one-transistor one-memristor (1T1R) cell-based memory arrays, and propose circuit-level performance and energy models for an individual memory cell and the memory array as a whole. We consider titanium dioxide (TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> )and hafnium oxide (HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> )based memristors, and for these technologies, there is a sub-10% difference between energy and performance computed using our models and HSPICE simulations. Using a performance-driven design approach, the energy-optimized TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based resistive RAM (RRAM) array consumes the least write (4.06 pJ/b) and read energy (188 fJ/b) when storing 3 b/cell for 100-ns write and 1-ns read access times. Similarly, HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> -based RRAM array consumes the least write (365 fJ/b) and read energy (173 fJ/b) when storing 3 b/cell for 1-ns write and 200-ns read access times. We also present a detailed analysis of the implications of process, voltage, and temperature variations on the performance and energy consumption of a multibit RRAM cell.

Crossbar RRAM Arrays: Selector Device Requirements During Read Operation

Passive crossbar resistive random access memory (RRAM) arrays require select devices with nonlinear I-V characteristics to address the sneak-path problem. Here, we present a systematical analysis to evaluate the performance requirements of select devices during the read operation of RRAM arrays for the proposed one-selector-one-resistor (1S1R) configuration with serially connected selector/storage element. We found high selector current density is critical and the selector nonlinearity (ON/OFF) requirement can be relaxed at present. Different read schemes were analyzed to achieve high read margin and low power consumption. Design optimizations of the sense resistance and the storage elements are also discussed.

Multiple phase change structure for the scalable phase change random access memory array

A multiple phase change structure with Sb79Te21 for switching and Ge1Cu2Te3 for memory was fabricated and evaluated for cell operation. It was confirmed that Sb79Te21 with smaller contact diameter is successfully operated or used as a switching device with selective current pulses. In addition, it was estimated that this structure provides acceptable on–off ratio and leakage current by structural consideration. From these results, we consider that the structure with multiple phase change materials is suitable as a new device with both switching and memory functions, which gives higher scalability in three-dimensional array architecture by adopting no additional selective devices, such as transistors and diodes. Therefore, we expect that this structure can be one of the candidates for the scalable phase change random access memory (PCRAM).

Nano-Crossbar Memories Comprising Parallel/Serial Complementary Memristive Switches

This work explores anti-serial (anti-parallel) memristive switches—ASMs (APMs)—as potential cross-point elements in nano-crossbar resistive random access memory arrays. The memory operation principles for both device combinations are shown in detail. The effectiveness of these memristive structures to the solution of the parasitic conducting (current sneak paths) problem is presented via an analytical approach which is based on the basic setup of resistive crossbar memories. Simulation results of crossbars of up to 4,096 elements, arranged in quadratic configurations, are conducted. The provided results supplement this comprehensive analysis of APMs and ASMs, outlining their overall performance characteristics and commenting on their applicability to the practical realization of large crossbar memory systems. Finally, a special array topology is applied to an ASM-based crossbar memory. Its performance is compared to the performance of the pure ASM-based memory. The conducted simulations reveal significantly improved read-out voltage margins which further contribute to addressing the parasitic current paths which prevent the reliable operation of memristive crossbar circuit topologies.

50 nm AlxOy resistive random access memory array program bit error reduction and high temperature operation

In order to decrease program bit error rate (BER) of array-level operation in AlxOy resistive random access memory (ReRAM), program BERs are compared by using 4 × 4 basic set and reset with verify methods on multiple 1024-bit-pages in 50 nm, mega-bit class ReRAM arrays. Further, by using an optimized reset method, 8.5% total BER reduction is obtained after 104 write cycles due to avoiding under-reset or weak reset and ameliorating over-reset caused wear-out. Then, under-set and over-set are analyzed by tuning the set word line voltage (VWL) of ±0.1 V. Moderate set current shows the best total BER. Finally, 2000 write cycles are applied at 125 and 25 °C, respectively. Reset BER increases 28.5% at 125 °C whereas set BER has little difference, by using the optimized reset method. By applying write cycles over a 25 to 125 to 25 °C temperature variation, immediate reset BER change can be found after the temperature transition.

Calculation of single event upset based on Monte Carlo and device simulations

An extraction method for single event upset cross section based on Monte Carlo code and device simulation is proposed, which can be used to calculate single event effects and sensitive regions in memories accurately. Single event upset cross sections of domestic static random access memory (SRAM) and field programmatic gate array (FPGA) devices are calculated, and results agree well with these from heavy ion test. Simulation results reveal the physical mechanism of the relationship between single event upset sensitivity and surface area of off-state NMOSFET and PMOSFET. Sensitive regions of single event upset under different linear energy transfer (LET) values are obtained. The radial ionization profiles of heavy ions with different energy, but the same LET, are also calculated using the Monte Carlo method. The track radius of high-energy ion is significantly larger than that of low-energy ion, while the charge density at the track center of low-energy ion is higher by two or three orders of magnitude. With decreasing technology scaling, the impact of these differences on single event effects will be more pronounced, and the threshold LET and saturated cross-section will not be capable of describing the single event response completely.

Reliability Analysis and Comparison of Implication and Reprogrammable Logic Gates in Magnetic Tunnel Junction Logic Circuits

Non-volatile logic is a promising solution to overcome the leakage power issue which has become an important obstacle to scaling of CMOS technology. Magnetic tunnel junction (MTJ)-based logic has a great potential, because of the non-volatility, unlimited endurance, CMOS compatibility, and fast switching speed of the MTJ devices. Recently, by direct communication between spin-transfer-torque-operated MTJs, several realizations of intrinsic logic-in-memory circuits have been demonstrated for which the MTJ devices are used simultaneously as memory and computing elements. Here, we present a reliability analysis of the MTJ-based logic operations and show that the reliability is an essential prerequisite of these MTJ-based logic circuits. It is demonstrated that for given MTJ device characteristics, the implication logic architecture, a new kind of logic based on material implication, significantly improves the reliability of the MTJ-based logic as compared to the reprogrammable logic architecture which is based on the conventional Boolean logic operations AND, OR, etc. Implementing the implication gates in spin-transfer torque magnetic random access memory arrays provides pure electrical read/write and logic operations and also allows fan-out to multiple outputs.

Analyzing the Impact of Nano-Scale Body Biasing Technique on Leakage and Delay of Highly Stable 16-Bit Static Random Access Memory Array

Analyzing the Impact of Nano-Scale Body Biasing Technique on Leakage and Delay of Highly Stable 16-Bit Static Random Access Memory Array

Disturbance Characteristics of Vertical Channel Phase Change Random Access Memory Array

Disturbance Characteristics of Vertical Channel Phase Change Random Access Memory Array

Disturbance Characteristics of Vertical Channel Phase Change Random Access Memory Array

A novel vertical channel phase change random access memory (VPCRAM) was proposed for reducing leakage current and increasing chip density of phase change random access memory (PCRAM). Since VPCRAM cells are integrated into the vertical channel structure, disturbance characteristics between each cell should be important issues for array design. In this work, the dependence of device parameter on electrical disturbance characteristics and thermal disturbance characteristics has been investigated by three-dimensional device simulation and finite element method simulation respectively. Electrical disturbance characteristics are determined by both channel potential coupling and junction leakage current between adjacent cells. The effects of substrate doping concentration and Si wall have been investigated. Thermal distribution has also been investigated with finite element method simulation. The oxide layer on the gate has large effect on thermal transfer within phase change materials due to the small thermal conductivity.

Analysis of Passive Memristive Devices Array: Data-Dependent Statistical Model and Self-Adaptable Sense Resistance for RRAMs

In this paper, a 2 × 2 equivalent statistical circuit model is presented to deal with sneak currents and random data distributions for design and analysis of n x m passive memory arrays of memristive devices. This data-dependent 2 × 2 model enables a broad range of analysis, such as the optimum detection voltage margin, with computational efficiency and no limit on the memory array size. We propose self-adaptable sense resistors that can find their statistical optimum values for reading stored data patterns by composing them with either a replica of a part of resistive random access memory (RRAM) array or a part of RRAM array itself. Self-adaptable resistors can increase the average voltage detection margin by 46%, and reduce the average current consumption by 14% for the case of a 128 × 128 passive array with OFF-to-ON resistance ratio of 103.

Improved reliability of magnetic field programmable gate arrays through the use of memristive tunnel junctions

Since the recent successful implementation of the long-hypothesized memristor, its use in neuronal computing and in the reproduction of biological neural networks has gained increasing attention. In addition to the development of these new applications, the growing number of devices with memristive properties is promising to improve already established technologies. Herein, we use the recently reported memristance in magnesium-oxide-based magnetic tunnel junctions to improve the error tolerance in magnetic random access memory and magnetic field programmable logic arrays.

A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective

In this paper, we analyze the energy dissipation in spin-torque-transfer random access memory array (STTRAM). We present a methodology for exploring the design space to minimize the energy dissipation of the array while maintaining required read and write quality for a given magnetic tunnel junction technology. The proposed method shows the need for proper choice of the silicon transistor width and array operating voltage to minimize the energy dissipation of the STTRAM array. The write energy is found to be 10 × greater than read energy. Hence, read-write ratio becomes a crucial factor that determines energy for STTRAM last level caches (L2). An exploration is performed across several architectural benchmarks including shared and non-shared caches for detailed energy analysis.

High Volume Diagnosis in Memory BIST Based on Compressed Failure Data

Embedded memories are increasingly identified as having potential for introducing new yield loss mechanisms at a rate, magnitude, and complexity large enough to demand major changes in fault diagnosis techniques. In particular, time-related or complex read faults that originate in the highest density areas of semiconductor designs require new methods to diagnose more complex faults affecting large groups of memory cells. This paper presents a built-in self-test (BIST)-based fault diagnosis scheme that can be used to identify a variety of failures in embedded random-access memory arrays. The proposed solution employs flexible test logic to record test responses at the system speed with no interruptions of a BIST session. It offers a simple test flow and enables detection of time-related faults. Furthermore, the way test responses are processed allows accurate and time-efficient reconstruction of error bitmaps. The proposed diagnostic algorithms use a number of techniques, including discrete logarithm-based counting with ring generators acting as very fast event counters and signature analyzers. Experimental results confirm high diagnostic accuracy of the proposed scheme and its time efficiency.