RAM Technology Research Articles

Exploring spin current and dielectric switching characteristics of doped-multiferroic in hexagonal phase for advance RAM technology: A theoretical study

The single-phase bismuth ferrite BiFeO3 (BFO) has garnered significant interest due to its spintronic-based switching properties observed at room temperature. The first-principles calculations were executed to examine the spin-polarized electronic, dielectric, and structural characteristics of co-doped BFO with lanthanum (La) at A-site and cobalt (Co), nickel (Ni) at B-site in its hexagonal phase (Bi1-αLaαFe1-βNiβO3 with α = β = 0.04) with generalized gradient approximation (GGA-PBE). The highest value (1.01 × 10−11 A) of total current observed in La Ni co-doped BFO, featuring a distinct spin current of the same magnitude, attributed to spin polarization at the Fermi level (100 %). Additionally, Co-doped BFO exhibits the highest observed spin current density (1.05 × 109A/m2) and charge current density (1.03 × 10−5A/m2). In case of dielectric switching properties, the Ni-doped BFO displays the lowest values of linear dielectric polarization (6.00 × 10−2 C/m2), polarization charge at its interface (1.27 × 10−17 C), capacitance (4.23 × 10−15 F), and switching energy (3.81 × 10−19 J), which is particularly lower than the reported switching energy (1.92 aJ) of multiferroic capacitor.

Influence of Build Orientation on Surface Roughness and Fatigue Life of the Al2024-RAM2 Alloy Produced by Laser Powder Bed Fusion (L-PBF)

Additive manufacturing of high strength Al alloys brings problems with hot cracking during rapid solidification. One of the ways to solve this challenge is technology developed by the Elementum 3D company. The way consists of inoculation by ceramic nanoparticles using RAM technology. When applying the L-PBF method, a very fine equiaxed microstructure with exceptional properties and without cracks is created. This paper offers the results and discussion of the microstructure, surface roughness and fatigue life of the high-strength Al2024-RAM2 alloy made from a gas atomized powder with an additive of 2 wt.% ceramic nanoparticles on the base of Ti. The specimens for fatigue tests were produced in different orientations relative to the building platform and left in the as-built conditions with different surface quality (roughness). The specimens were T6 heat-treated. The treatment caused a coarsening of a part of the fine grains. After T6 heat treatment, the hardness increased significantly, which occurred by precipitation hardening. Fatigue tests of specimens with different build orientation were performed in plane bending and the experimentally determined fatigue life was discussed in terms of surface roughness and material microstructure.

Dynamic memory tuned by frequency in a homologous thermotropic liquid crystal.

With scaling of dynamic RAM and NAND memory technologies reaching a limit, there is a need for dynamic memory with high density. In this work, an investigation on existence of dynamic memory feature in a frequency tuned homologous series of thermotropic liquid crystals has been carried out. A homologues series of five thermotropic liquid crystalline compounds comprising of 4-butyl benzoic acid and various alkyloxy benzoic acids are prepared, and all these mesogens exhibit only nematic phase. Liquid crystal dynamic memory storage setup consists of a conducting transparent glass cell with two indium tin oxide coated transparent glass plates acting as electrical electrodes in which the selected thermotropic liquid crystal is filled by capillary action. The temperature dependent dielectric relaxation studies enable to elucidate the relaxation frequency of each of these mesogens in nematic phase. The liquid crystal at different temperatures is excited with the relaxation frequency at various chosen fields, and the dielectric hysteresis is recorded. The magnitude of the hysteresis loop is directly proportional to the memory storage capacity. The main objective of this work is observation of dynamic memory storage in liquid crystals exhibiting nematic phase, at different frequencies in a thermotropic liquid crystal as the ingredient in a conducting polyamide buffed glass cell excited by an external electrical dc stimulus. The variation of the hysteresis loop with varying field; temperature and frequency are also studied and reported in this work.

On-Line Fault Protection for ReRAM-Based Neural Networks

The emerging Resistive RAM (ReRAM) technology significantly boosts the performance and the energy efficiency of the deep learning accelerators (DLAs) via the Computing-in-Memory (CiM) architecture. However, ReRAM-based DLA also suffers a high occurrence rate of memory faults. How to detect and protect against the faults in ReRAM devices poses great challenges to ReRAM-based DLA design. In this work, we propose RRAMedy, an in-situ fault detection and network remedy framework for ReRAM-based DLAs. With the proposed Adversarial Example Testing, which is a lifetime on-device and on-line fault detection technique, it achieves high detection coverage of both hard faults and soft faults at a low run-time cost. In addition, it employs an edge-cloud collaborative model retraining method to tolerate the detected faults by leveraging the inherent fault-adaptive capability of DNNs. Meanwhile, to enable in-situ model remedy when the cloud assistance is absent due to security or overhead issues, we propose to accelerate the fault-masking retraining process on edge devices with parallelized Knowledge Transfer. Our experimental results show that the proposed fault detection technique achieves high fault detection accuracy and delivers real-time testing performance. Meanwhile, the proposed retraining approach greatly alleviates the accuracy degradation problem and achieves excellent performance speedups over the baselines.

A MIXED-METHODS, RANDOMIZED, CONTROLLED EVALUATION OF REMOTE ACTIVITY MONITORING FOR PERSONS LIVING WITH DEMENTIA

Abstract Remote activity monitoring (RAM) technology has the potential to allow at-home caregivers to track the behaviors and activities of persons with dementia in real-time, thus facilitating more proactive symptom management. The aim of the present study was to assess whether RAM technology was associated with reductions in negative health transitions and service utilization for persons with Alzheimer’s disease or related dementias (ADRD). An embedded experimental mixed methods design was used that included 179 caregivers who were followed over a 1.5 year study period. Participants were randomly assigned to receive the RAM technology system or usual care. Follow-up surveys were administered on a bi-annual basis over an 18-month period that collected information on dementia caregiver and care recipient characteristics and outcomes. We developed multilevel mixed effects models to estimate odds ratios for binary outcomes (falls, wandering, health care admissions) and categorical outcomes (frequency of falls and wandering). In adjusted models, RAM technology use was statistically and significantly associated with lower odds of emergency department visits (p<.05) and less frequent falls (p=.05) for people living with dementia over the 1.5 year study period. Technologies that prevent or delay the onset of negative health events via improved care management and monitoring may enhance the care of persons with dementia. As dementia continues to pose an array of challenges for someone living with ADRD, RAM or similar technologies may offer a solution to the conundrum of dementia care.

Results of the study of the hydraulic ram technology of water lifting from watercourses

This paper is aimed at studying the hydraulic ram (hydram) technology of water lifting from watercourses for water supply of pastures and irrigation of agricultural land with improving the technological parameters of a hydram pump – increasing energy indicators: hydraulic shock pressure, supply, head, and efficiency, and increasing the reliability of its operation, creating convenience and ease of maintenance. The improved design and technological scheme of a hydram pump unit is substantiated, which has originality and is protected by the patent for the invention KZ No. 34,027, the patent holder is the non-profit joint-stock company “Kazakh National Agrarian University” (NJSC KazNAU). Formulas for substantiating the technological and technical parameters of a hydram pump are proposed, the reliability of which is confirmed experimentally. The purpose of the study is to develop an alternative technology for lifting water from watercourses using a hydraulic ram pump, to substantiate the main technological and technical parameters with improved indicators compared to analogues – increasing hydraulic shock pressure, supply, head, efficiency and improving the reliability of operation, creating convenience and ease of maintenance. The following research methods were used in the study: patent with an operability review, theoretical and experimental approaches. As a result, the obtained theoretical formulas were experimentally confirmed. Based on the results of patent research, operability review, and own research at NJSC KazNAU, an improved design and technological scheme of a hydram pump has been developed. The design and technological scheme of an improved hydram pump unit is given. Based on a comparative analysis of the characteristics of the new hydram pump and its analogue, a clear advantage of the new pumping unit has been established.

Big Data Privacy and Security Using Abundant Data Recovery Techniques and Data Obliviousness Methodologies

The concept of big data security is introduced in this article along with many features. It illustrates the need for security in healthcare systems as the volume of data increases continuously over the period of time. The necessity of big data security as well as several big data analytics phases highlighted. It covers many big data privacy-preserving strategies. Many digital storage solutions being used in today’s world are designed to work only with fixed format of the data. This paper introduces some methods for maintaining metadata obliviousness. The oblivious RAM technology mentioned in the research article address security concerns and it can be handled with the daily increase in data in several industries. Security needs are introduced at many phases of big data creation, such as information extraction, storage systems, and analytics of the information. Additionally, it presents several data recovery methods for recovering original data in the event of a data crash. This paper covers several data categorization methods for sorting data into normal and sensitive categories as well as methods for anomaly detection. It discusses the advantages and disadvantages of various security measures.

홀로그램 텔레프레전스 기술의 체험이 MICE행사 참가자에게 미치는 영향

Purpose - With the advance of the fourth industrial area, the MICE industries try to adopt these technologies. This study intended to find the influence of Hologram Telepresence Tech nologies on MICE participants’s experience absorption, interaction and their satisfaction, using Pine & Gilmore’s experience theory. Design, data, and methodology -Based on the previous studies, this study hypothesized that four experience factors; entertainment, educational, aesthetic and escape experiences will influence experience quality; absorption and interaction each and those will influence the participants’ satisfaction. To verify the hypotheses, multi-regression analysis with SPSS were conducted. Result - The results showed that education and aesthetic experience influenced on both absorption and interaction, additionally entertainment experience had influenced on interaction only. On the other hand, escape experience had no impact on both absorption and interaction. Also, absorption and interaction had impact on the participant’s satisfaction. Conclusions -This study broadened theoretical concept in MICE research by adopting Hologram technology and it provided practical implications on how to effectively operate Holog ram technology in MICE with organizers and hosts.

Performances and Stability Analysis of a Novel 8T1R Non-Volatile SRAM (NVSRAM) versus Variability

Static Random-Access Memories (SRAMs) are an integral part of the chip industry, occupying a noticeable share of the memory market due to their high performance and compatibility with CMOS technology. Traditional SRAMs do not have the capacity to retain data after power-off, preventing their use in non-volatile applications. This paper presents a novel Non-Volatile SRAM (NVSRAM) device based on Resistive RAM (RRAM) technology. A comparison between SRAM and the proposed NVSRAM performances is proposed at both cell and memory array level. The comparison covers several metrics such as energy consumption, area and static noise margin (SNM). Moreover, this work proposes a deep analysis of the impact of RRAM variability as well as the CMOS subsystem variability on the NVSRAM performances. The proposed structure demonstrates robust NVSRAM performances in terms of stability and reliability despite RRAM variability.

Quantitative Evaluation of Hardware Binary Stochastic Neurons

Recently there has been increasing activity to build dedicated Ising Machines to accelerate the solution of combinatorial optimization problems by expressing these problems as a ground-state search of the Ising model. A common theme of such Ising Machines is to tailor the physics of underlying hardware to the mathematics of the Ising model to improve some aspect of performance that is measured in speed to solution, energy consumption per solution or area footprint of the adopted hardware. One such approach to build an Ising spin, or a binary stochastic neuron (BSN), is a compact mixed-signal unit based on a low-barrier nanomagnet based design that uses a single magnetic tunnel junction (MTJ) and three transistors (3T-1MTJ) where the MTJ functions as a stochastic resistor (1SR). Such a compact unit can drastically reduce the area footprint of BSNs while promising massive scalability by leveraging the existing Magnetic RAM (MRAM) technology that has integrated 1T-1MTJ cells in ~Gbit densities. The 3T-1SR design however can be realized using different materials or devices that provide naturally fluctuating resistances. Extending previous work, we evaluate hardware BSNs from this general perspective by classifying necessary and sufficient conditions to design a fast and energy-efficient BSN that can be used in scaled Ising Machine implementations. We connect our device analysis to systems-level metrics by emphasizing hardware-independent figures-of-merit such as flips per second and dissipated energy per random bit that can be used to classify any Ising Machine.

Exploring Applications of STT-RAM in GPU Architectures

Use of modern GPUs has been extended from traditional 3D graphic processing to computing acceleration of many scientific, engineering, and enterprise applications. In modern GPUs, on-chip memory capacity keeps increasing to support thousands of chip-resident threads. For example, a large register file is needed in order to efficiently process highly-parallel threads in single instruction multiple thread (SIMT) fashion, and a large shared memory is often implemented to allow data sharing among the threads on the chip. On-chip memory capacity of GPUs, however, is highly constrained by large memory cell area and high static power consumption of conventional SRAM implementation. In this work, we propose to utilize the emerging multi-level cell (MLC) spin-transfer torque RAM (STT-RAM) technology to implement register file and shared memory in GPUs. Compared to SRAM, MLC STT-RAM (or MLC-STT) has a much smaller cell area as well as ultra-low standby power, thanks to the non-volatility of MLC-STT technology. Hence, the footprint and leakage power of the implemented memory components are substantially reduced. Moreover, in light of asymmetric performance of soft and hard bits of a MLC-STT cell, we propose a dynamic data remapping strategy in register file and shared memory implementations that allows a flexible tradeoff between the memory access time and the available capacity: frequently-accessed data is always mapped to the fast rows built with the soft bits of the MLC-STT cells while the slow rows composed of the hard bits are used only when a larger capacity is critically needed. We also develop a novel rescheduling scheme to minimize the waiting time of the issued warps to access register banks in the register file, which is induced by the long writeback operations through the reordering of the issued warps. Finally, an early termination technology is also applied to save the write energy of the shared memory if the bits of the memory do not flip. Experimental results on benchmarks of ISPASS2009, Rodinia, Parboil, and CUDA show that on average, MLC-STT register file can achieve 3.28% system performance improvement, 9.48% energy reduction, and 38.9% energy efficiency improvement compared to conventional SRAM-based design. Meanwhile, MLC-STT shared memory leads to 3.45% system performance improvement, 49.3% energy reduction, and 116% energy efficiency improvement.

Non-volatile SRAM memory cells based on ReRAM technology

Static Random-Access Memories (SRAMs) are very common in today’s chip industry due to their speed and power consumption but are classified as volatile memories. Non-volatile SRAMs (nvSRAMs) combine SRAM features with non-volatility. This combination has the advantage to retain data after power off or in the case of power failure, enabling energy-efficient and reliable systems under frequent power-off conditions. In this work, several nvSRAMs architectures based on Oxide Random-Access Memory (OxRAM) technology are presented and compared. OxRAMs are non-volatile memories considered as a subset of Resistive RAM (ReRAM) technology.

Programmable FFT Processor using Dual RAM and ROM Technologies for Future 5G Communications

The high-throughput programmable Fast Fourier transform processor supports the usage of 2-stream 1024/2048/4096-point Fast Fourier Transforms and 1-to 4-stream 64/128-point Fast Fourier Transform for 4G,wireless local networks and for 5G.The proposed architecture which was designed is a well-intentionedfour-bank single-port SRAM which is being working in four-word data width, the design which is proposed gives us sixteen memory pathways . where the data is accessed up to this extent where it can be used in upcoming 5G. The radix-16 butterfly process element comprises of 2 cascaded parallel, pipelined radix-4 butterfly units which is specified. The projected memory-addressing methodology will effectively wear down single-port, merged-bank memory with high-radix process components. Comparing with typical memory based Fast Fourier Transform styles, the derived design has higher performance in expressions of area and power consumption. The architecture which is projected occupies the tiniest area of around1.21mm2.The processor supports 1966MS/s 4096-point FFT and frequency of 1GHz.The Electronic design automation synthesis results show the power consumption is 32.16mW.The SQNR performance analysis is 42.14 dB.

CAST: Content-Aware STT-MRAM Cache Write Management for Different Levels of Approximation

Spin transfer torque magnetic RAM (STT-MRAM) technology is one of the most promising alternative for static RAM (SRAM) for implementing on-chip memories. Compared with SRAMs, STT-MRAMs benefit from higher density and near-zero leakage power, nonetheless they impose high energy consumption for reliable write operations. However, in many applications, absolute data integrity is not required; thus, acting on the current applied in the write operations may represent a novel knob for disciplined approximate computing to obtain energy saving with a minimal quality loss in applications’ outputs. This article proposes CAST, a hardware/software approach to adjust the energy/quality of write operations in STT-MRAM caches in multicore systems based on the content of requested write operations. CAST utilizes fine-grained cache-line-level actuation knobs with different levels of quality for individual write operations. This unique feature of STT-MRAMs allows to avoid interapplication actuation interference suffered by SRAMs, and makes the approach particularly suitable for systems running multiple applications with mixed accuracy sensitivity. Moreover, CAST exploits another peculiarity of STT-MRAMs represented by the asymmetry and transition-dependency of the write error rate, to further tune in a fine-grained manner the write current to achieve an additional energy saving, even in full-accurate applications. Our evaluations on workloads of full-approximate, mixed-criticality, and full-accurate applications demonstrate up to 57%, 34%, and 21% energy savings over a baseline STT-MRAM cache, respectively, with an acceptable quality of the generated outputs.

A tunable ferroelectric based unreleased RF resonator

This paper introduces the first tunable ferroelectric capacitor (FeCAP)-based unreleased RF MEMS resonator, integrated seamlessly in Texas Instruments’ 130 nm Ferroelectric RAM (FeRAM) technology. The designs presented here are monolithically integrated in solid-state CMOS technology, with no post-processing or release step typical of other MEMS devices. An array of FeCAPs in this complementary metal-oxide-semiconductor (CMOS) technology’s back-end-of-line (BEOL) process were used to define the acoustic resonance cavity as well as the electromechanical transducers. To achieve high quality factor (Q) of the resonator, acoustic waveguiding for vertical confinement within the CMOS stack is studied and optimized. Additional design considerations are discussed to obtain lateral confinement and suppression of spurious modes. An FeCAP resonator is demonstrated with fundamental resonance at 703 MHz and Q of 1012. This gives a frequency-quality factor product f cdot Q = 7.11 times 10^{11} which is 1.6× higher than the most state-of-the-art Pb(Zr,Ti)O3 (PZT) resonators. Due to the ferroelectric characteristics of the FeCAPs, transduction of the resonator can be switched on and off by adjusting the electric polarization. In this case, the resonance can be turned off completely at ±0.3 V corresponding to the coercive voltage of the constituent FeCAP transducers. These novel switchable resonators may have promising applications in on-chip timing, ad-hoc radio front ends, and chip-scale sensors.

Incorporating Variability of Resistive RAM in Circuit Simulations Using the Stanford–PKU Model

Intrinsic variability observed in resistive-switching devices (cycle-to-cycle and device-to-device) is widely recognised as a major hurdle for widespread adoption of Resistive RAM technology. While physics-based models have been developed to accurately reproduce the resistive-switching behaviour, reproducing the observed variability behavior of a specific RRAM has not been studied. Without a properly fitted variability in the model, the simulation error introduced at the device-level propagates through circuit-level to system-level simulations in an unpredictable manner. In this work, we propose an algorithm to fit a certain amount of variability to an existing physics-based analytical model (Stanford-PKU model). The extent of variability exhibited by the device is fitted to the model in a manner agnostic to the cause of variability. Further, the model is modified to better reproduce the variations observed in a device. The model, fitted with variability can well reproduce cycle-to-cycle, as well as device-to-device variations. The significance of integrating variability into RRAM models is underscored using a sensing example.

Scalable Emulation of Sign-Problem–Free Hamiltonians with Room-Temperature p -bits

A special class of many-body quantum systems can be simulated by probabilistic algorithms running on digital computers, but generating correlated random numbers is computationally expensive. The authors propose an asynchronous probabilistic coprocessor that uses a slightly modified cell structure in the emerging magnetoresistive RAM technology, which should accelerate such probabilistic algorithms by several orders of magnitude, in terms of sampling speed and energy. This approach complement existing efforts to simulate quantum systems by using scalable, room-temperature building blocks.

SPARE: Spiking Neural Network Acceleration Using ROM-Embedded RAMs as In-Memory-Computation Primitives

Despite huge success of artificial intelligence, hardware systems running these algorithms consume orders of magnitude higher energy compared to the human brain, mainly due to heavy data movements between the memory unit and the computation cores. Spiking neural networks (SNNs) built using bio-plausible neuron and synaptic models have emerged as the power-efficient choice for designing cognitive applications. These algorithms involve several lookup-table (LUT) based function evaluations such as high-order polynomials and transcendental functions for solving complex neuro-synaptic models, that typically require additional storage. To that effect, we propose `SPARE' - an in-memory, distributed processing architecture built on ROM-embedded RAM technology, for accelerating SNNs. ROM-embedded RAMs allow storage of LUTs, embedded within a typical memory array, without additional area overhead. Our proposed architecture consists of a 2-D array of Processing Elements (PEs). Since most of the computations are done locally within each PE, unnecessary data transfers are restricted, thereby alleviating the von-Neumann bottleneck. We evaluate SPARE for two different ROM-Embedded RAM structures - CMOS based ROM-Embedded SRAMs (R-SRAMs) and STT-MRAM based ROM-Embedded MRAMs (R-MRAMs). Moreover, we analyze trade-offs in terms of energy, area and performance, for using the two technologies on a range of image classification benchmarks. Furthermore, we leverage the additional storage density to implement complex neuro-synaptic functionalities. This enhances the utility of the proposed architecture by provisioning implementation of any neuron/synaptic behavior as necessitated by the application. Our results show up-to 1.75x, 1.95x and 1.95x improvement in energy, iso-storage area, and iso-area performance, respectively, by using neural network accelerators built on ROM-embedded RAM primitives.

Impact of the precursor chemistry and process conditions on the cell-to-cell variability in 1T-1R based HfO2 RRAM devices

The Resistive RAM (RRAM) technology is currently in a level of maturity that calls for its integration into CMOS compatible memory arrays. This CMOS integration requires a perfect understanding of the cells performance and reliability in relation to the deposition processes used for their manufacturing. In this paper, the impact of the precursor chemistries and process conditions on the performance of HfO2 based memristive cells is studied. An extensive characterization of HfO2 based 1T1R cells, a comparison of the cell-to-cell variability, and reliability study is performed. The cells’ behaviors during forming, set, and reset operations are monitored in order to relate their features to conductive filament properties and process-induced variability of the switching parameters. The modeling of the high resistance state (HRS) is performed by applying the Quantum-Point Contact model to assess the link between the deposition condition and the precursor chemistry with the resulting physical cells characteristics.

Design and analysis of 2T2M hybrid CMOS-Memristor based RRAM

In this paper, a Static Noise Margin (SNM) analysis for 2T2M RRAM cell is investigated. The proposed analysis is done using mathematical formulation and verified by SPICE simulations. The analysis is tested for both, write and read modes. Moreover, the analysis is applied to diverse types of RRAM cells, and a comparison between the performance of such cells is discussed. Additionally, the effect of the exponential memristor model on the memristor behaviour in terms of switching speed and the range of the memristor resistance are discussed in detail. The circuits design and simulations were carried out using TSMC 130 nm CMOS technology and Cadence Virtuoso tool. Finally, comparison between different RAM technologies is briefly presented.