RAM Resources Research Articles

Comparative analysis of the performance of Unity and Unreal Engine game engines in 3D games

The article compared the performance of the Unity and Unreal Engine game engines based on tests conducted on two nearly identical games. The research focused on frames per second, CPU usage, RAM, and GPU memory. The results showed that Unity achieved a better average frame rate. Unreal Engine required more RAM and GPU resources. Analyzing CPU load values revealed that on the first system, Unity demanded less CPU usage. However, on the second system, Unreal Engine used over 10 percentage points less CPU. The conclusions from the research partially confirm the hypothesis that Unity requires fewer computer resources, although in some cases, Unreal Engine may demand fewer CPU resources.

Development and Implementation of an FPGA-Embedded Multimedia Remote Monitoring System for Information Technology Server Room Management

Conventional data acquisition systems face challenges in achieving high acquisition speeds and rapid storage of large data volumes using microcontrollers. In contrast, field-programmable gate arrays (FPGAs) offer numerous advantages, including high clock frequencies, minimal internal delays, fast operational speeds, abundant internal RAM resources, and simplified control of complex peripheral circuits. This study presents the design of an FPGA-based multimedia remote monitoring system for information technology server rooms. The proposed system utilizes an FPGA as the primary controller and incorporates environmental sensors, electrical energy sensors, carbon monoxide sensors, smoke sensors, and A/D converter modules to monitor multiple locations within the server room. Simultaneously, the FPGA transmits the collected data from each monitoring point via a serial port to an LCD serial screen for display. An alarm is triggered if any environmental anomalies are detected, indicating abnormal statuses. Additionally, the system employs the fast Fourier transform algorithm and butterfly operations to derive voltage and current AC quantities, while utilizing relative temperature differences to identify equipment faults within the server room. The system is evaluated in terms of functionality, user-friendliness, and reliability. Experimental results demonstrate that all performance measures align with expectations, fulfilling the initial design objectives and highlighting the potential applicability and relevance of FPGA technology in the monitoring field. In addition, a comparison between FPGA and traditional microcontroller systems is performed, showcasing the superior processing speed and performance of the FPGA-based system. This comparative analysis further validates the advantages of using FPGA technology in high-speed data acquisition and monitoring applications.

Evaluation of classical correlation functions from 2/3D images on CPU and GPU architectures: Introducing CorrelationFunctions.jl

Correlation functions are becoming one of the major tools for quantification of structural information that is usually represented as 2D or 3D images. In this paper we introduce ▪ open-source package developed in Julia and capable of computing all classical correlation functions based on imaging input data. Images include both binary and multi-phase representations. Our code is capable of evaluating two-point probability S2, phase cross-correlation ρij, cluster C2, lineal-path L2, surface-surface Fss, surface-void Fsv, pore-size P and chord-length p distribution functions on both CPU and GPU architectures. Where possible, we presented two types of computations: full correlation map (correlations of each point with other points on the image, that also allows obtaining ensemble averaged CF) and directional correlation functions (currently in major orthogonal and diagonal directions). Such an implementation allowed for the first time to assemble a completely free solution to evaluate correlation functions under any operating system with well documented application programming interface (API). Our package includes automatic tests against analytical solutions that are described in the paper. We measured execution times for all CPU and GPU implementations and as a rule of thumb full correlation maps on GPU are faster than other methods. However, full maps require more RAM and, thus, are limited to available RAM resources. On the other hand, directional CFs are memory efficient and can be evaluated for huge datasets – this way they are the first candidates for structural data compression of feature extraction. The package itself is available through Julia package ecosystem and on GitHub, the latter source also contains documentation and additional helpful resources such as tutorials. We believe that a single powerful computational tool such as ▪ presented in this paper will significantly facilitate the usage of correlation functions in numerous areas of structural description and research of porous materials, as well as in machine learning applications. We also present some examples as applied to ceramic, soil composite and oil-bearing rock samples based on their 3D X-ray tomography and 2D scanning electron microscope images. Finally, we conclude our paper with discussion of possible ways to further improve presented computational framework. Program summaryProgram Title: CorrelationFunctions.jlCPC Library link to program files:https://doi.org/10.17632/6gb9gfm3dw.1Developer's repository link:https://github.com/fatimp/CorrelationFunctions.jlLicensing provisions: MITProgramming language: JuliaSupplementary material: Numerous Jupiter notebooks with examples are available on the GitHub pageNature of problem: Correlation functions are invaluable universal statistical descriptors of structures used in numerous scientific fields such as astronomy, material science, rock and soil physics, hydrology and biology, to name just a handful of examples. While computational approaches are available in the literature for some functions, they are fragmented and are usually implemented in proprietary interpreted languages for CPU architecture alone.Solution method: We contribute an open source and cross-platform solution with well documented API for computation of all classical correlation functions from both 2D and 3D images on CPU and GPU architectures. The package computes correlation functions using two approaches: computation of correlation maps and computation along predefined directions. These two approaches can be thought of as an execution time - memory trade-off, but the choice may also depend on the application. The computations are based on a) fast Fourier transform with preprocessing steps such as cluster labeling or edge detection, and b) linear scan approach to evaluate correlation functions along predefined directions. Where justified, the algorithms can be executed on both CPU and GPU which results in high execution speed on modern hardware.

Methods and means of conflict-free data exchange in the group of mobile robotic platforms

When using groups of mobile robotic platforms (MRP), problems arise related to the management of individual platforms, the organization of cooperation in the group, and the management of the group as a whole. Management of the MRP group involves managing the actions of individual platforms to achieve the group's overall goal. To ensure the management of the MRP group in such a case, it is advisable to choose a hybrid method that requires solving the problem of conflict-free data exchange and control commands between the MRPs in the group. To solve this problem, it is proposed to improve the relevant methods and tools. The scientific novelty of the obtained research results is that a method of multi-channel conflict-free data exchange has been developed, which provides a real-time mode due to the coordination of the intensity of data arrival with the intensity of access. The method of controlling the movement of a group of mobile robotic platforms has been improved, which, by taking into account the changing parameters of the platforms and the changing state of the surrounding environment, provides effective management of the MRP group in real time. The practical significance of the research results is that it is proposed to use the CSMA/CA slotted mechanism for non-time-critical traffic to improve performance, and for time-critical traffic, coordinator-controlled access using guaranteed time slots. The hybrid method of management takes into account the advantages of centralized and distributed depending on specific tasks and conditions of use. It is proposed to use a multi-channel device for conflict-free exchange using the method of time allocation of RAM resources for data exchange in hybrid control. It is shown that global low-power networks LPWANs (Low-Power Wide Area Networks) can be used to transmit small blocks of data at a low speed when exchanging with MRP. It is proposed to use the slotted CSMA/CA mechanism for the transmission of non-time-critical traffic, and for time-critical traffic, coordinator-controlled access using guaranteed time slots. It is shown that the performance of the network during the conflict-free access period CFP depends on the results of the distribution of guaranteed GTS time slots among active users. LoRa technology was selected for long-distance data exchange between MRPs, which at the MAC (Media Access Control) sublayer allows for transmission planning and communication management between end devices and gateways, avoiding collisions and optimizing network performance.

Migration Route Selection for a Microservice in a Fog Computing Network

Purpose. The new generation of communication networks has provided the basis for the realization of new classes of services, one of which are URLLC services. These services include concepts such as Tactile Internet. The transmission medium for URLLC requires high bandwidth and reliability of communication channels as well as ultra-low latency in the network. To cover these requirements, various technologies, such as fog computing and microservice architecture, are introduced into the architecture of networks. The latter is more often recommended to be used together with support for microservice migration between devices. A related goal is to determine the efficient route to the destination server. Methods. Conducting research on a model network with the collection of real load statistics from the network nodes and their analysis to determine the most efficient migration route for microservice according to the proposed algorithm based on these data. Novelty. The novelty of the presented method consists in adapting the classical algorithm of route selection in a graph to solve the actual problem of microservice migration route selection. Results. The parameters that need to be considered for efficient routing during microservice migration and the level of network architecture that should control the migration were defined. The results have shown that the proposed method is preferred over the AODV protocol. Practical relevance. It is quantitatively shown that using the proposed method the CPU resources consumption on the network nodes during microservice migration can be reduced total by 77 %, the RAM resources usage by 14 %, the percentage of lost packets on the used communication channels can be reduced total by 7 %, which would provide higher network reliability and increase its performance.

Vector-switched digital predistortion for concurrent dual-band transmitters with hybrid time-division multiplexing scheme

In a concurrent dual-band digital predistortion (DPD) system, due to the large number of two-dimensional (2D) polynomial-based model coefficients and the existence of cross-modulation terms, the hardware realization usually requires a lot of resources. To alleviate this problem, this paper proposes a hardware-efficient field programmable gate array (FPGA)-based piecewise vector-switched (PVS) DPD method. With the PVS method, a 2D memory polynomial (MP) model with fewer coefficients can be used as a sub predistorter model for each region. Furthermore, a new hybrid time-division multiplexing (HTDM) scheme is proposed for the 2D-MP predistorter architecture, which enables sharing of cross-modulated lookup tables (LUTs) and complex multipliers in a hybrid way. Experimental results show that the proposed method improves the adjacent channel power ratio (ACPR) and normalized mean square error (NMSE) by 18.74 dB and 13.23 dB, respectively, and saves about 30% and 80% of RAM and DSP resources, respectively.

Variational mode decomposition and sample entropy optimization based transformer framework for cloud resource load prediction

The efficient prediction of cloud resource demand plays a crucial role in resource allocation and scheduling in cloud data centers, helping to optimize resource utilization and improve service quality. However, accurately predicting cloud resource demand poses challenges due to the failure of prediction models in real-world scenarios, such as extreme load peaks, and the limitation of computation burden on the global characterization capability. To effectively handle single-variable cloud resource load time series with multidimensional hidden factors, we propose a sample entropy-optimized variational model decomposition transformer (VMDSE-Tformer) for cloud resource scheduling. Hereby, we decompose the time series through variational model decomposition, and then reconstruct the subsequence collection using sample entropy calculation. Then, we use a class Transformer framework with a multi-head self-attention mechanism to learn deep features and obtain encoding representations of each component sequence. We conduct sufficient experiments on three benchmark datasets by comparing them with five state-of-the-art models. Notably, the MAPE of VMDSE-Tformer is improved by about 60% compared to LSTNet. The results demonstrate the superior performance of our VMDSE-Tformer in terms of predicting task sequence intensity, CPU, and RAM resource demand. Therefore, VMDSE-Tformer can serve as a powerful and efficient tool to predict resource demand in cloud data centers, with implications for more effective resource management and service delivery.

FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Networks With Efficient DSP and Memory Optimization

Spiking neural networks (SNNs) have been widely used due to their strong biological interpretability and high energy efficiency. With the introduction of the backpropagation algorithm and surrogate gradient, the structure of spiking neural networks has become more complex, and the performance gap with artificial neural networks has gradually decreased. However, most SNN hardware implementations for field-programmable gate arrays (FPGAs) cannot meet arithmetic or memory efficiency requirements, which significantly restricts the development of SNNs. They do not delve into the arithmetic operations between the binary spikes and synaptic weights or assume unlimited on-chip RAM resources by using overly expensive devices on small tasks. To improve arithmetic efficiency, we analyze the neural dynamics of spiking neurons, generalize the SNN arithmetic operation to the multiplex-accumulate operation, and propose a high-performance implementation of such operation by utilizing the DSP48E2 hard block in Xilinx Ultrascale FPGAs. To improve memory efficiency, we design a memory system to enable efficient synaptic weights and membrane voltage memory access with reasonable on-chip RAM consumption. Combining the above two improvements, we propose an FPGA accelerator that can process spikes generated by the firing neuron on-the-fly (FireFly). FireFly is the first SNN accelerator that incorporates DSP optimization techniques into SNN synaptic operations. FireFly is implemented on several FPGA edge devices with limited resources but still guarantees a peak performance of 5.53TOP/s at 300MHz. As a lightweight accelerator, FireFly achieves the highest computational density efficiency compared with existing research using large FPGA devices.

Oracles Integration in Blockchain-Based Platform for Smart Crop Production Data Exchange

Blockchain oracles are an intermediary designed to connect external non-deterministic information and real-world data to the blockchain digital infrastructure. The variety of proposed solutions and purposes are of great variety and suggest that it is necessary to take into account different features of the process and specifically define the required functionalities. The purpose of this paper is to present the integration of oracles into an EOSIO blockchain-based platform for smart crop production data exchange by smart contracts. The functions of two oracles are presented. Their integration is described at the design level and at the implementation of the smart contracts. The design level is illustrated by workflow diagrams of internal processes between oracle applications and the blockchain smart contract and by external processes in the oracles’ smart contracts. The implementation level is illustrated by oracle application configuration files and elements of C++ smart contracts, such as constant and variable declarations, multi-index tables, internal contract functions, and actions called by other contracts and external programs. As results of the oracles’ operation, a report on the detected emergency failures and an estimate of the cost of ram resource are presented.

An effective self-adaptive bi-directional multi-layer genetic algorithm for resource and user allocations in networks

Transportation, telecommunication, electricity supply, and production–distribution systems all involve the construction and management of highly sophisticated networks. Without properly designing such networks, none of these systems work effectively. Network design problems, as the core of network-based decision making systems, can be used to model the technological design of networks. They are widespread and have many industrial applications. In telecommunication, usually an infrastructure is sought, as a combination of possible links and switches, which can best maintain a given level of data traffic between a number of servers and devices. This paper presents a solution to a problem in which in every period of time, the specification of some of the nodes in network may need to be altered. In the current procedure, all arcs and nodes are fixed and only the node parameters need to change. However, the presented solution strategy, because of its multi-layered characteristic, can be easily extended to the cases where arcs and nodes are also subject to change.The solution procedure has been tested on the cloud-based Internet Café problem. In this problem, different types of video games can use different amount of RAM, CPU, GPU, and video-RAM resources, with demand for each type of game varying dynamically in a specified period, e.g., over a day. Different servers provide these resources to dumb-terminals which act essentially as input–output devices, including display monitors, for games running on the servers. Each server needs to provide the necessary resources for the games currently played on all terminals served. In this way, depending on the demand of each terminal, at each period, the terminal’s capability can change dynamically, and it will act as a different virtual machine in different periods. Hence, the requirements of the Internet Café infrastructure change dynamically over time. The solution procedure has been tested on a series of generated large instances, and the results are very promising. For a total of 9 cases tested, the optimal solution is obtained, in a matter of minutes, for 3 cases. For an additional 2 cases, the solution obtained is within less than 2% of the optimal solution. The results are also reported for 3 additional test cases for a problem with over 13,000 users and 4,000 seats, demonstrating the procedure capability in handling extra-large problems.

Networking in next generation disaggregated datacenters

SummaryNowadays, datacenters lean on a computer‐centric approach based on monolithic servers which include all necessary hardware resources (mainly CPU, RAM, network, and disks) to run applications. Such an architecture comes with two main limitations: (1) difficulty to achieve full resource utilization and (2) coarse granularity for hardware maintenance. Recently, many works investigated a resource‐centric approach called disaggregated architecture where the datacenter is composed of self‐content resource boards interconnected using fast interconnection technologies, each resource board including instances of one resource type. The resource‐centric architecture allows each resource to be managed (maintenance, allocation) independently. LegoOS is the first work which studied the implications of disaggregation on the operating system, proposing to disaggregate the operating system itself. They demonstrated the suitability of this approach, considering mainly CPU and RAM resources. However, they did not study the implication of disaggregation on network resources. We reproduced a LegoOS infrastructure and extended it to support disaggregated networking. We show that networking can be disaggregated following the same principles, and that classical networking optimizations such as DMA, DDIO, or loopback can be reproduced in such an environment. Our evaluations show the viability of the approach and the potential of future disaggregated infrastructures.

Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems

Partially dynamic reconfiguration (PDR) technology can accelerate the reconfiguration process and overcome hardware resource constraints when facing the challenge of high performance with respect to applications and resources constraints on field-programmable gate arrays (FPGAs). On FPGAs with PDR technology, the available on-chip Block RAM (BRAM) resources may not satisfy the memory requirements for all data. If we reserve more BRAM resources, then the total area of the dynamically reconfigurable region (DRR) that is used for calculation will decrease, with a reduction in system performance. We propose a memory-aware optimization framework to search for the optimal solution considering partitioning, scheduling, and floorplanning, where we make a tradeoff between performance and on-chip memory resources utilization. We then propose methods for memory allocation: An ILP model and a heuristic algorithm are provided to determine the minimum memory requirements and the number of corresponding memory blocks for data, as well as to determine whether the memory block with its stored data is assigned on-chip or off-chip by formulating the problem into a 0-1 knapsack problem and solving it using dynamic programming. Experimental results show that the memory-aware optimization framework and methods of memory allocation can increase the amount of on-chip data access to 29.65% of the total data volume with guaranteed performance.

Proactive Auto-Scaling Approach of Production Applications Using an Ensemble Model

The resource usage behaviors of application workloads are currently the primary concern of cloud providers offering hosting services. These services should be able to adapt to workload changes by automatically provisioning and de-provisioning resources so that, at all times, the existing resources in a system match the current service demand. Such behavior can be achieved manually by hiring a DevOps team to manage the application’s resources. Another option would be automating the resource provisioning processing using automated rules. Once such rules are met, the hosting environment will scale the resources accordingly. However, managing a DevOps team or creating flaky rules can lead to over-scaling application resources. This work proposes a new approach: a proactive auto-scaling framework built on an ensemble model. Such a model utilizes several machine learning techniques to scale application resources to match resource demand before the need arises. We evaluated our solution against three real production applications hosted on Cegedim Cloud Hosting Environment, an industrial environment serving several cloud applications from various domains, and against other machine learning models used in similar proactive auto-scaling experiments mentioned in past work. The experimentation results show that predicting application resources like CPU or RAM is feasible. Moreover, even in production environments, our ensemble model performs optimally in the CPU case and is near the optimal model when predicting RAM resources.

High-Level Design Optimizations for Implementing Data Stream Sketch Frequency Estimators on FPGAs

This paper presents simple yet effective optimizations for implementing data stream frequency estimation sketch kernels using High-Level Synthesis (HLS). The paper addresses design issues common to sketches utilizing large portions of the embedded RAM resources in a Field Programmable Gate Array (FPGA). First, a solution based on Load-Store Queue (LSQ) architecture is proposed for resolving the memory dependencies associated with the hash tables in a frequency estimation sketch. Second, performance fine-tuning through high-level pragmas is explored to achieve the best possible throughput. Finally, a technique based on pre-processing the data stream in a small cache memory prior to updating the sketch is evaluated to reduce the dynamic power consumption. Using an Intel HLS compiler, a proposed optimized hardware version of the popular Count-Min sketch utilizing 80% of the embedded RAM in an Intel Arria 10 FPGA, achieved more than 3x the throughput of an unoptimized baseline implementation. Furthermore, the sketch update rate is significantly reduced when the input stream is skewed. This, in turn, minimizes the effect of high throughput on dynamic power consumption. Compared to FPGA sketches in the published literature, the presented sketch is the most well-rounded sketch in terms of features and versatility. In terms of throughput, the presented sketch is on a par with the fastest sketches fine-tuned at the Register Transfer Level (RTL).

Calculation of Lipophilicity of Organophosphate Pesticides Using Density Functional Theory.

Higher lipophilicity facilitates the passage of a substance across lipid cell membranes, the blood–brain barrier and protein binding, and may also indicate its toxicity. We proposed eight methods for predicting the lipophilicity of the 22 most commonly used organophosphate pesticides. In this work, to determine the lipophilicity and thermodynamic parameters of the solvation of pesticides, we used methods of density functional theory with various basis sets, as well as modern Grimm methods. The prediction models were evaluated and compared against eight performance statistics, as well as time and RAM used in the calculation. The results show that the PBE-SVP method provided the best of the proposed predictive capabilities. In addition, this method consumes relatively less CPU and RAM resources. These methods make it possible to reliably predict the ability of pesticide molecules to penetrate cell membranes and have a negative effect on cells and the organism as a whole.

A New Multichannel Parallel Real-time FFT Algorithm for a Solar Radio Observation System Based on FPGA

The real-time fast Fourier transform (FFT) is the essential algorithm for signal processing in a solar radio receiver. However, field-programmable gate array (FPGA) computation resources have become the limitation of real-time processing of signals with increasing time and spectral resolutions. It is necessary to design a real-time parallel FFT algorithm with reduced resource occupation in the development of future receiving systems. In this paper, we developed a multichannel parallel FFT algorithm named the multichannel parallel real-time fast Fourier transform (MPR-FFT), which can greatly reduce FPGA resource occupation while increasing the real-time processing speed. In this algorithm, the 4L simultaneous N-point FFTs are first converted into L simultaneous 4N-point FFTs. Fusion processing is then performed to obtain the 4 ∗ L ∗ N-point spectrum. This method has been used in developing a solar radio spectrometer, which works in the frequency range of 0.5–15 GHz in the Chashan Observatory. In this spectrometer, 16 channel MPR-FFT with 8k-point data is realized in a Xilinx UltraScale KU115 FPGA. The MPR-FFT algorithm reduced the computational resources to a large extent compared to the Cooley-Tukey-based parallel FFT method; for instance, the Look-Up-Table, Look-Up-Table RAM, Flip-Flop, and Digital Signal Process slices were reduced by 37%, 50%, 17%, and 2.48%, respectively. Although the MPR-FFT consumes 14 block RAM resources more than the Cooley-Tukey-based parallel FFT, the MPR-FFT algorithm presents an overall reduction in resource usage.

Comparison of capabilities of the Unity environment and LibGDX in terms of computer game development

As part of the work on the article, two 2D games were created – one based on the Unity environment and the other based on LibGDX. Main focus in the work was to compare the performance of both games. For this purpose, research was carried out to determine which game has a better impact on the usage of CPU and RAM resources. Attention was also paid to community support for both tools and the programmer’s comfort during the work in both of these tools. The results of the performance studies suggest that LibGDX may be a better choice for creating small projects where performance is a priority. However, the support of the community and the comfort of working with the environment and the lack of need to use external programs speak in favor of Unity.

Pelatihan Troubleshooting Instalasi Linux Debian Dengan Text Mode Dan Graphic Mode Di SMK Negeri 5 Palembang

Community service activities are carried out at SMK N 5Palembang. This training activity aims to improve the competence ofstakeholders in SMK N 5 Palembang, consisting of productive teachers,students and student councils. This activity is carried out by the pratikummethod and question and answer procession about troubleshooting andinstallation both in text mode and graphic mode. The benefits obtained ininstallation training using text mode are very light in operation and quite fastin the installation procession while by using graphic mode is using enoughprocessor and ram resources, thus reducing acceleration and installationspeed.

THE NEW MODIFICATION OF THE APPROXIMATING FUNCTIONS METHOD FOR CLOUD COMPUTING

The approach for building cloud-ready fault-tolerant calculations by approximating functions method, which is an analytical-numerical part of Volterra integral equation method for solving 1D+T nonlinear electromagnetic problems, is presented. The solving process of the original algorithm of the method is modified: it is broken down into the sequential chain of stages with a fixed number of sequential or parallel steps, each of which is built in a fault-tolerant manner and saves execution results in fault-tolerant storage for high availability. This economizes RAM and other computer resources and does not damage the calculated results in the case of a failure, and allows stopping and starting the calculations easily after manual or accidental shutdown. Also, the proposed algorithm has self-healing and data deduplication for cases of corrupted saved results. The presented approach is universal and does not depend on the type of medium or the initial signal. Also, it does not violate the natural description of non-stationary and nonlinear features, the unified definition of the inner and outer problems, as well as the inclusion of the initial and boundary conditions in the same equation as the original approximating functions method. The developed approach stress-tested on the known problems, stability checked and errors compared.

The New Modification of the Approximating Functions Method for Cloud Computing

Abstract The approach for building cloud-ready fault-tolerant calculations by approximating functions method, which is an analytical-numerical part of Volterra integral equation method for solving 1D+T nonlinear electromagnetic problems, is presented. The solving process of the original algorithm of the method is modified: it is broken down into the sequential chain of stages with a fixed number of sequential or parallel steps, each of which is built in a fault-tolerant manner and saves execution results in fault-tolerant storage for high availability. This economizes RAM and other computer resources and does not damage the calculated results in the case of a failure, and allows stopping and starting the calculations easily after manual or accidental shutdown. Also, the proposed algorithm has self-healing and data deduplication for cases of corrupted saved results. The presented approach is universal and does not depend on the type of medium or the initial signal. Also, it does not violate the natural description of non-stationary and nonlinear features, the unified definition of the inner and outer problems, as well as the inclusion of the initial and boundary conditions in the same equation as the original approximating functions method. The developed approach stress-tested on the known problems, stability checked and errors compared.