RAM Buffer Research Articles

High Throughput CORDIC Architecture Based 3D-DCT/IDCT Processor

In this paper, 8x8x8 3D-DCT/IDCT processor based on CORDIC architecture for high data rate of image processing and video coding with reduced hardware has been presented. It uses two stages of CORDIC DCT processor i.e. one is 1D-DCT and another one is 2D-DCT processor based on fully pipelined unfolded CORDIC architecture with RAM buffer. The one-dimensional DCT is useful in processing of speech waveforms. For images and video signal processing, we need a 3D version of the DCT/IDCT data, especially in coding for compression and decompression, for its best performance. This processor performs both the DCT and IDCT simultaneously with the help of CORDIC algorithm of both 3D-DCT and IDCT which has boost the speed of the processor. Ease the use of less computation based unfolded CORDIC architecture in the processor reduces complexity and power consumption. With the working frequency approximately 414 MHz less power dissipation, low latency and high throughput can be obtained. The processor has been implemented on Xilinx ISE 14.7 and design is simulated in DE-2 board. This processor has not only reduces the complication but also increases the speed which lead to broad use in image and video processing.

TreeFTL: An Efficient Workload-Adaptive Algorithm for RAM Buffer Management of NAND Flash-Based Devices

NAND flash memory is widely used for the secondary storage of computer systems. The flash translation layer (FTL) is the firmware that manages and operates a flash-based storage device. One of the FTL's modules manages the RAM buffer of the flash device. Now this RAM buffer is sufficient to be used for both address mapping and data buffering. As the fastest component of the flash layer interface, effective management of this buffer has a significant impact on the performance of data storage and access. This paper proposes a novel scheme called TreeFTL for this purpose. TreeFTL organizes address translation pages and data storage pages in a tree-like structure in the RAM buffer. The tree enables TreeFTL to adapt to the access behaviors of workloads by dynamically adjusting the partitions for address mapping and data buffering. Furthermore, TreeFTL employs a lightweight mechanism to evict the least-recently-used victim pages when the need arises. Our experiments show that TreeFTL is able to spend 46.6 and 49.0 percent less service time over various workloads than two state-of-the-art algorithms, respectively, for a 64 MB RAM buffer.

Low-Power MCU With Embedded ReRAM Buffers as Sensor Hub for IoT Applications

This paper proposes embedding 256 Kb resistive random-access memory (ReRAM) in a microcontroller unit as a data buffer for communicating with a stand-alone flash memory. In this study, the chip was manufactured using a combination of the TSMC 0.18 $ \mu{\rm m}$ process and the Industrial Technology Research Institute ReRAM back-end-of-line process. The ReRAM was equipped with a novel sense amplifier that had three magnification times for the reference cell current for increasing the read yield by 32%. Furthermore, the ReRAM controller included built-in self-test, built-in self-repair, a shortened Bose–Chaudhuri–Hocquenghem (99, 64, 5) error-correlating code, and asymmetric coding can yield ReRAM up to approximately 100%. When compared with the conventional dynamic random-access memory (DRAM) buffer, the proposed architecture reduces the system execution time by 25% and the power consumption by 15% at 25 MHz. Simulations also showed that the ReRAM buffering runs at least 51% faster when compared with the use of other nonvolatile memories such as ferroelectric RAM, phase change RAM, and conduct-bridge RAM. Although ReRAM buffering is just competitive in speed and power consumption of spin-transfer torque magnetorresistive RAM buffering, ReRAM has clear advantages in area, cost, and reliability.

Flash as cache extension for online transactional workloads

Considering the current price gap between hard disk and flash memory SSD storages, for applications dealing with large-scale data, it will be economically more sensible to use flash memory drives to supplement disk drives rather than to replace them. This paper presents FaCE, which is a new low-overhead caching strategy that uses flash memory as an extension to the RAM buffer of database systems. FaCE aims at improving the transaction throughput as well as shortening the recovery time from a system failure. To achieve the goals, we propose two novel algorithms for flash cache management, namely multi-version FIFO replacement and group second chance. This was possible due to flash write optimization as well as disk access reduction obtained by the FaCE caching methods. In addition, FaCE takes advantage of the nonvolatility of flash memory to fully support database recovery by extending the scope of a persistent database to include the data pages stored in the flash cache. We have implemented FaCE in the PostgreSQL open-source database server and demonstrated its effectiveness for TPC-C benchmarks in comparison with existing caching methods such as Lazy Cleaning and Linux Bcache.

Queueing analysis of optical and electronic combined buffer for optical packet switches

Optical packet switching provides high-speed and energy-efficient packet forwarding. Fiber delay line (FDL)-based buffer is one practical solution to avoid packet contention in optical packet switches. However, the FDL buffer suffers from scalability problems, and thus, cannot accommodate a large volume of network traffic at a time. An optical and electronic combined (OE) buffer architecture alleviates the scalability issues. This architecture uses supplementary electronic RAM buffers when the traffic volume increases. We then propose an analytical model of the OE buffer to estimate the blocking probability and the average delay. We find that complex OE combined model can be simply modeled by combination of an existing analytic model of the FDL buffer and an M/M/1/K queueing system. Comparing analytical results with packet-level simulation results, we demonstrate that our analytical results display characteristics similar to the simulation results. This analysis enables to determine appropriate setting of the OE buffer such as the buffer size and use policy.

High Speed Data Transfer System Based on the USB3.0 Technology

A data acquisition system is introduced based on FPGA and USB3.0 to achieved high transfer rate. FPGA control AD and manage the DDR RAM buffer. The USB connect model is synchronous Slave FIFO. The multi data buffer queue structure is selected as the data structure. The testing results show that the average storage rate is 229.1MByte/s.When using two hard disk, the rate can reach to 289.8MByte/s.Some key factors affect the transfer rate is also discussed.

An index-based management scheme with adaptive caching for huge-scale low-cost embedded flash storages

Due to its remarkable access performance, shock resistance, and costs, NAND flash memory is now widely adopted in a variety of computing environments, especially in mobile devices such as smart phones, media players and electronic book readers. For the consideration of costs, low-cost embedded flash storages such as flash memory cards are often employed on such devices. Different from solid-state disks, the RAM buffer equipped on low-cost embedded flash storages are very small, for example, limited under several dozens of kilobytes, despite of the rapidly growing capacity of the storages. The significance of effectively utilizing the very limited on-device RAM buffers of embedded flash storages is therefore highlighted, and a novel design of scalable flash management schemes is needed to tackle the new access constraints of MLC NAND flash memory. In this work, a highly scalable design of the flash translation layer is presented with the considerations of the on-device RAM size, user access patterns, address-mapping-information caching and MLC access constraints. Through a series of experiments, it is verified that, with appropriate settings of cache sizes, the proposed management scheme provides comparable performance results to prior arts with much lower requirements on the on-device RAM. In other words, the proposed scheme suggests a strategy to make better use of the on-device RAM, and is suitable for embedded flash storages.

SeTPR*-tree: Efficient Buffering for Spatiotemporal Indexes Via Shared Execution

In this paper, we study the problem of efficient spatiotemporal indexing of moving objects. In order to reduce the frequency of object location updates, a linear motion model is used to model the near future location of moving objects. A number of existing spatiotemporal indexes have already been proposed for indexing these models. However, these indexes are either designed to offer high query performance or high update performance. Therefore, they are all ill suited to handle situations where both queries and updates arrive at a high rate. In this paper, we propose the SeTPR*-tree which extends the TPR*-tree to more efficiently use a limited-sized RAM buffer for processing queries in batches and rapidly arriving updates. We provide both theoretical and empirical evidence of the effectiveness of the SeTPR*-tree in improving query and update performance. We have conducted extensive experiments using a recognized spatiotemporal benchmark on a solid state drive. The SeTPR*-tree simultaneously outperforms the best tested index optimized for queries by up to a factor of 5.6 for query I/O and outperforms the best tested index for updates by up to a factor of 11.5 for update I/O.

Multi-channel pre-beamformed data acquisition system for research on advanced ultrasound imaging methods

The lack of open access to the pre-beamformed data of an ultrasound scanner has limited the research of novel imaging methods to a few privileged laboratories. To address this need, we have developed a pre-beamformed data acquisition (DAQ) system that can collect data over 128 array elements in parallel from the Ultrasonix series of research-purpose ultrasound scanners. Our DAQ system comprises three system-level blocks: 1) a connector board that interfaces with the array probe and the scanner through a probe connector port; 2) a main board that triggers DAQ and controls data transfer to a computer; and 3) four receiver boards that are each responsible for acquiring 32 channels of digitized raw data and storing them to the on-board memory. This system can acquire pre-beamformed data with 12-bit resolution when using a 40-MHz sampling rate. It houses a 16 GB RAM buffer that is sufficient to store 128 channels of pre-beamformed data for 8000 to 25 000 transmit firings, depending on imaging depth; corresponding to nearly a 2-s period in typical imaging setups. Following the acquisition, the data can be transferred through a USB 2.0 link to a computer for offline processing and analysis. To evaluate the feasibility of using the DAQ system for advanced imaging research, two proof-of-concept investigations have been conducted on beamforming and plane-wave B-flow imaging. Results show that adaptive beamforming algorithms such as the minimum variance approach can generate sharper images of a wire cross-section whose diameter is equal to the imaging wavelength (150 μm in our example). Also, planewave B-flow imaging can provide more consistent visualization of blood speckle movement given the higher temporal resolution of this imaging approach (2500 fps in our example).

An Efficient Buffer Scheme for Flash-based Databases

Most embedded database systems are built on a two-level memory hierarchy, a RAM buffer on top of flash memory. Both kinds of memories have limited capacity, thus, how to efficiently utilize them is critical for embedded systems with resource restrictions. Different from magnetic hard disk, flash memory has speed asymmetry in reads and writes, i.e., random reads are over an order of magnitude faster than random writes. μ-tree is the state-of-theart index supporting efficient random updates on the flash memory. However, we found that the traditional page based buffer scheme(LRU-P for short) under-utilized the RAM space. To improve the utilization on the memory resources and the query performance, we propose a novel buffer scheme called LRU-N – a node-based LRU policy for the RAM buffer. In addition, to increase the utilization of the flash memory, we also present a k-partitioning strategy for μ-tree. LRU-N uses a page address swizzling scheme to exploit the co-related locality of accessing multiple tree nodes in the μ-tree. The k-partitioning strategy determines an optimal k value for space efficiency by allocating more flash memory to the leaf nodes and guarantees sufficient space for tree growth. Our experiments conducted on both simulated data sets of various distributions and real-world data sets show that LRU-N can significantly improve buffer hit rate up to 65% for the best cases over the page-based scheme LRU-P; even with small buffer size, LRU-N can also achieve rather good performance. And our proposed k-partitioning strategy can effectively reduce the index size up to 33% over μ-tree.

Copyright Infringement in the Ether: RAM Buffering and the Copyright Act’s Duration Requirement

Copyright Infringement in the Ether: RAM Buffering and the Copyright Act’s Duration Requirement

A latency-aware scheduling algorithm for all-optical packet switching networks with FDL buffers

Optical buffers implemented by fiber delay lines (FDLs) have a volatile nature due to signal loss and noise accumulation. Packets suffer from excessive recirculation through FDLs, and they may be dropped eventually in their routing paths. Because of this, packet scheduling becomes more difficult in FDL buffers than in RAM buffers, and requires additional design considerations for reducing packet loss. We propose a latency-aware scheduling scheme and an analytical model for all-optical packet switching networks with FDL buffers. The latency-aware scheduling scheme is intended to minimize the packet loss rate of the networks by ranking packets in the optimal balance between latency and residual distance. The analytical model is based on non-homogeneous Markovian analysis to study the effect of the proposed scheduling scheme on packet loss rate and average delay. Furthermore, our numerical results show how various network parameters affect the optimal balance. We demonstrate quantitatively how to achieve the proper balance between latency and residual distance so that the network performance can be improved significantly. For instance, we find that under a given latency limit and light traffic load our scheduling scheme achieves a packet loss rate 71% lower than a scheduling scheme that ranks packets simply based on latency.

Performance analysis of a packet prioritisation algorithm for optical-packet-switching networks

Because of the explosive growth of network traffic, backbone networks move towards all-optical-packet-switching networks. However, optical buffers implemented by Fibre Delay Lines (FDLs) have a volatile nature because of signal loss and noise accumulation problems from optical components of the FDL buffer. Because of this, scheduling packets becomes more difficult in the FDL buffer than in the RAM buffer, and requires additional design considerations for reducing packet loss. Therefore, we propose a packet prioritisation algorithm for all-optical-packet-switching networks with FDL buffers. The point of the packet prioritisation algorithm is to rank packets in optimal balance between latency and residual distance. We optimise a relative-distance factor to minimise packet loss probability. Our simulation results show how various network parameters affect the optimal relative-latency factor.

The impact of synchronization on the performance of FDL buffers

Circumventing the speed bottleneck of electronic switching, novel switching approaches like optical burst switching (OBS) and optical packet switching (OPS) handle the switching of bursts (or packets) in backbone nodes optically, and include a set of fiber delay lines (FDLs) for optical buffering. While previous work acknowledges the performance difference between optical FDL buffers and electronic RAM buffers, the important role of synchronization herein has received little attention to date. Addressing this, we developed a single-wavelength FDL model that allows to capture the interplay between FDL buffer performance, burst size distribution and synchronization. Relying on generating functions, we constructed a discrete-time queueing model with batch arrivals that is valid for general burst and batch size distribution, and allows to quantify how synchronization impacts performance. This paper presents our model and compares its output for different synchronization levels. Whether or not buffer performance benefits from synchronization, turns out to depend strongly on the burst size distribution.

Memory Subsystems in High-End Routers

As Internet routers scale to support next-generation networks, their memory subsystems must also scale. Several solutions combine static RAM and dynamic RAM buffering but still have major scaling limitations. Using a parallel architecture and distributed memory-management algorithms with hybrid SRAM/DRAM improves buffering performance. The parallel hybrid SRAM/DRAM memory system is also work conserving, which is particularly important under light traffic conditions.

A Hybrid Flash File System Based on NOR and NAND Flash Memories for Embedded Devices

This paper presents a hybrid flash file system (HFFS) based on both NOR flash and NAND flash memory. In a conventional NAND flash-based flash file system, there is a trade-off between life span and durability in the frequent writing of small amounts of data. Because NAND flash supports only a page-level I/O, at least one page is wasted in the synchronous writing of small amounts of data. The wasting of pages reduces the utilization and life span of the NAND flash. To alleviate the utilization problem, some NAND flash-based flash file systems write small amounts of data asynchronously with RAM buffers, though buffering in RAM decreases the durability of the system. Our HFFS eliminates the trade-off between life span and durability. It synchronously stores data as a log in the NOR flash, whenever we append small amounts of data to a file. The merged logs are then flushed to the NAND flash in a page-aligned fashion. The implementation of our HFFS is based on our previous NAND flash-based file system, called CFFS, The experimental results reveal that our HFFS provides a longer life span than a conventional NAND flash-based synchronous flash file system with a similar level of durability.

Applications of algebraic soft-decision decoding of Reed-Solomon codes

Efficient soft-decision decoding of Reed-Solomon (RS) codes is made possible by the Koetter-Vardy (KV) algorithm which consists of a front-end to the interpolation-based Guruswami-Sudan (GS) list decoding algorithm. This paper approaches the soft-decision KV algorithm from the point of view of a communications systems designer who wants to know what benefits the algorithm can give, and how the extra complexity introduced by soft decoding can be managed at the systems level. We show how to reduce the computational complexity and memory requirements of the soft-decision front-end. Applications to wireless communications over Rayleigh fading channels and magnetic recording channels are proposed. For a high-rate RS(255,239) code, 2-3 dB of soft-decision gain is possible over a Rayleigh fading channel using 16-quadrature amplitude modulation. For shorter codes and at lower rates, the gain can be as large as 9 dB. To lower the complexity of decoding on the systems level, the redecoding architecture is explored, which uses only the appropriate amount of complexity to decode each packet. An error-detection criterion based on the properties of the KV decoder is proposed for the redecoding architecture. Queueing analysis verifies the practicality of the redecoding architecture by showing that only a modestly sized RAM buffer is required

Applications of Algebraic Soft-Decision Decoding of Reed–Solomon Codes

Efficient soft-decision decoding of Reed–Solomon codes is made possible by the Koetter–Vardy (KV) algorithm which consists of a front-end to the interpolation-based Guruswami–Sudan list decoding algorithm. This paper approaches the soft-decision KV algorithm from the point of view of a communications systems designer who wants to know what benefits the algorithm can give, and how the extra complexity introduced by soft decoding can be managed at the systems level. We show how to reduce the computational complexity and memory requirements of the soft-decision front-end. Applications to wireless communications over Rayleigh fading channels and magnetic recording channels are proposed. For a high-rate (RS 9225,239) Reed–Solomon code, 2–3 dB of soft-decision gain is possible over a Rayleigh fading channel using 16-quadrature amplitude modulation. For shorter codes and at lower rates, the gain can be as large as 9 dB. To lower the complexity of decoding on the systems level, the redecoding architecture is explored which uses only the appropriate amount of complexity to decode each packet. An error-detection criterion based on the properties of the KV decoder is proposed for the redecoding architecture. Queuing analysis verifies the practicality of the redecoding architecture by showing that only a modestly sized RAM buffer is required.

An experimental analysis of digital video library servers

Much work on video servers has concentrated on movies on demand, in which a relatively small number of titles are viewed and users are given basic VCR-style controls. This paper concentrates on analyzing video server performance for non-linear access applications. In particular, we study two non-linear video applications: video libraries, in which users select from a large collection of videos and may be interested in viewing only a small part of the title; and video walk-throughs, in which users can move through an image-mapped representation of a space. We present a characterization of the workloads of these applications. Our simulation studies show that video server architectures developed for movies on demand can be adapted to video library usage, though caching is less effective and the server can support a smaller user population for non-linear video applications. We also show that video walk-throughs require extremely large amounts of RAM buffering to provide adequate performance for even a small number of users.

A new fast cell resequence mechanism for multipath ATM switches

A new cell resequence mechanism is proposed to restore the cell sequence in multipath ATM switches. Since the proposed mechanism uses per-VC logical queues which store only the cells belonging to the same VC, the mechanism can reduce processing time compared to conventional resequence mechanisms. The mechanism also has no limitation on the peak rate of the VCs and needs no arbitration function to select an output cell. The mechanism can be implemented using a RAM buffer, a content addressable memory/random access memory (CAM/RAM) table, a controller, etc.