Radix-2 Fast Fourier Transform Research Articles

순환형-하다마드 코드로 직교 변조된 위성항법 보강 신호의 FFT 기반 심볼 복조 기법

In this paper, a fast Fourier transform (FFT)-based symbol demodulation method is proposed for a satellite navigation augmentation signal orthogonally modulated using Cyclic-Hadamard code. The proposed method rearranges the code and performs zero-padding interpolation to enable discrete Fourier transform computation by using the radix-2 FFT algorithm. The proposed method was compared with a correlation receiver in terms of symbol demodulation performance and receiver implementation complexity. Simulation results revealed that the proposed method achieves the same symbol error rate as the correlation receiver while reducing the computational complexity required at higher data rates.

A novel parallel prefix adder for optimized Radix-2 FFT processor

The Fast Fourier Transform (FFT) is the basic building block for DSP applications where high processing speed is the critical requirement. Resource utilization and the number of computational stages in Radix-2 FFT structure implementation can be minimized by improving the performance of utilized multiplier and adder blocks. This work proposes a hardware design of an efficient Radix-2 FFT architecture using optimized multiplier and novel Parallel prefix (PP) adder. The designed FFT architecture results in low power and area with an increase in operation speed in comparison to the existing architectures. Our proposed Radix 2 FFT implementation results in 18.218 ns (6.030 ns logic delay and 12.118 ns router delay) in comparison with 24.003 ns delay for Wallace multiplier using Kogge Stone PP adder (M1P1), 24.162 ns delay for Wallace multiplier using Brent Kung PP adder (M2P2), 24.889 ns delay for Wallace multiplier using Landner Fischer PP adder (M3P3) and 22.827 ns delay for Wallace multiplier using Han Carlson PP adder (M4P4) algorithm. The proposed adder and hence the FFT processor can be used in different applications where high speed, low power, and less area is required. The novel PP architecture results in a 20.19% improvement in comparison with other state-of-art techniques.

A novel addressing algorithm of radix-2 FFT using single-bank dual-port memory

PurposeThis paper aims to present a single-block memory-based FFT processor design with a conflict-free addressing scheme for field-programmable gate arrays FPGAs with dual-port block memories. This study aims for a single-block dual-port memory-based N-point radix-2 FFT design that uses memory locations and spending minimum clock cycle.Design/methodology/approachA new memory-based Fast Fourier Transform (FFT) design that uses a dual-port memory block is proposed. Dual-port memory allows the design to perform two memory reads and writes in a single clock cycle. This approach achieves low operational clock and smallest memory simultaneously, excluding some small overhead for exceptional address changes. The methodology is to read from while writing to a memory location, eliminating the need for excess memory and additional clock cycles.FindingsWith the minimum memory size and the simplest architecture, radix-2 FFT and single-memory block are used. The number of clock pulses spent for all FFT operations does not provide much advantage for low-point FFT operations but is important for high-point FFT operations. With the developed algorithm, N memory is used, and the number of clock pulses spent for all FFT stages is (N/2 +1)log2N for all FFT operations.Originality/valueThis is an original paper, which has simultaneously in whole or in part been submitted anywhere else.

Reconfigurable Superconducting FFT Processor Using Bit-Slice Block Share Processing Unit

We have proposed a reconfigurable high speed and very economical Rapid Single Flux Quantum (RSFQ) superconducting logic design based on the Fast Fourier Transform (FFT) Processor. We have designed a 256 – point FFT processor with the help of a bit-slicing block sharing unit. RSFQ is one of the superconducting device logics comprises of Josephson Junction. The computation complexity of this superconducting FFT is less when the number of points increased. We have proposed three different designs depending on the split radix FFT, the bit-serial radix 2 FFT, and the mixed radix FFT algorithms. The proposed design will slice the 256 – point FFT into eight 32 – point FFT each and each 32 – point FFT is divided into eight 4 – point FFT each for the reduction in hardware cost. For complex multiplication, the computation complexity of our design will be less than N/2 Log2 N for the radix 2 algorithm based on the Block share processing Unit (BSPU) and further, it is reduced for split radix & mixed radix algorithms based on BSPU based RSFQ logic. Due to this, the speed of the processor is improvised compared to general FFT algorithm based semiconductor technology. we have computed and calculated the latency at 10 GHz for our designs. The main aim of this proposed design is to reduce the complex computation time and better performance of the processor with less hardware cost. This proposed design can furthermore continue to several N2 – point by using synchronous clock tree.

An Improved Distributed Multiplier-Less Approach for Radix-2 FFT

Complex numbers play a vital role in the implementation of a wide number of Digital Signal Processing (DSP) algorithms. Since they are represented as two separate components (real and imaginary), the algorithms increased the number of computations. In this letter, we present an improved approach that reduces the number of computations by integrating the computation of the radix-2 Fast Fourier Transform (FFT) with the Distributed Arithmetic (DA) and Complex Binary Number System (CBNS). Further, the proposed architecture replaces multipliers with the use of adders and shifters, which considerably decrease the design area. Although more adders are needed to implement the new DA-CBNS proposed architecture, when compared to the traditional radix-2 FFT and DA or CBNS -based FFT algorithms, results show that the proposed design yields an increase in operating frequency, and a reduction in size, memory usage, and power consumption.

A Low-Overhead FFT Design With Higher SEU Resilience Implemented in FPGA

For area and power constraint applications in mission critical systems, the traditional fast Fourier transform (FFT) design requires huge hardware resources for data processing. In this article, we, therefore, present a low-overhead radix-2 FFT design that reduces hardware resources by simplifying the first two stages of the butterfly computations. Both the proposed design and the traditional design have been implemented in the MicroZus-20 (XC7Z020) platform. Their single-event performances have been compared through both fault injections and neutron exposure, and the experimental results demonstrate that the proposed design reduces the soft error rate by 53.8%. Also, the proposed FFT reduces the hardware resource consumption and circuit area by 64.8% when compared with the traditional design.

Design of an Area-Efficient Various N-point Support radix-2/22 FFT using Modified Butterfly Units

Fast Fourier Transform (FFT) acts as an element in the high-speed signal processing application, which involves the following subsequent operations, namely complex addition, complex subtraction and complex multiplication. Due to the complex multiplication operation, the FFT structures lead to more hardware demand. Hence, this work introduces an area-efficient various N-point support radix-2 and radix-22 FFT structure by using proposed modified butterfly units and radix-2/22 butterfly unit. The proposed modified butterfly units are used to reduce the number of complex multipliers effectively. For this reason, it is using for certain conditions in FFT design instead of existing radix-2/22 butterfly unit. Further, the proposed design supported to perform various size of FFT in a single architecture without increasing the extra element demand. Moreover, the proposed FFT structure designed and implemented using a Xilinx Virtex-6 Field-Programmable Gate Array (FPGA) device (6vcx75tff484-2) and Cadence tool with 45nm CMOS technology. The implementation results demonstrate that the proposed N-point (N=16, 32 and 64) DIF-FFT design attains the less hardware complexity when compared with existing multi-mode FFT design. Then the proposed area-efficient 16-point, 32-point and 64-point radix-2 FFT architectures reduce the total area by 20.99%, 11% and 4.9% respectively. As well, the proposed area-efficient 16-point, 32-point and 64-point radix-22 FFT architectures reduce the total area by 32%, 19% and 11% respectively.

Highly Parallel Vector Radix FFT for High Throughput Video Applications

The Vector Radix Fast Fourier Transform, with the inherent amenity for parallel implementation is very favourable for high throughput video processing applications. The conventional implementation of two-dimensional Fast Fourier Transform as one dimensional transforms of rows and columns can be replaced with this approach. This brief presents a novel Single Instruction Multiple Data architecture for the 8 × 8 vector radix Fast Fourier Transform implemented in Field-Programmable Gate Array with Digital Signal Processing Slice as the processing element. The performance metrics of the design is compared to the two dimensional Fast Fourier Transform implemented using one dimensional Fast Fourier Transform Intellectual Property from Xilinx. The analysis demonstrates the dominance of the design for high throughput low latency video applications.

ASIC design of 4K-point RADIX-2 FFT in 0.18 µm CMOS technology

Discrete Fourier transform (DFT) and inverse DFT are the key elements in the orthogonal frequency division multiplexing (OFDM) transmitter and receiver blocks, to represent changing signals in time and frequency domain. Fast Fourier transform (FFT), due to its high efficiency of computation over DFT, is currently used for many high-speed and real-time applications in both wireless and communication fields. In this paper, an application specific integrated circuit (ASIC) of 4k-point decimation in time (DIT) radix-2 FFT using fixed-point arithmetic has been designed. Finally, ASIC design results of various stages involved regarding area, timing and power consumption are presented.

Design and performance analysis of reconfigurable modified Vedic multiplier with 3-1-1-2 compressor

The Fast Fourier Transform (FFT) is a digital signal processing (DSP) function most commonly used one in many applications such as imaging, wireless communication, and multimedia. The FFT processors are consists of butterfly structure operations, which includes multiplication, addition and subtraction of complex value data. In this paper, an FFT butterfly structure is designed using the Vedic multiplier for high speed applications. In this Vedic multiplier, Urdhava Triyakbhyam algorithm is utilized to improve its efficiency. Then, detector block is introduced to identify the unwanted portion of the input data to be processed in the data processing unit. Therefore, data computation time is reduced in the detector based Vedic multiplier that supports full range and half range input data. The detector is developed based on Boolean function, to detect the valid ranges of two input operands during input data computation. The detector result is used to select the operand with half range input data for Vedic multiplication and it is disabled the surplus computation. So, it reduces the switching activities in the logic gates and proportionally reduces the power consumption. The proposed design-I is consists of Vedic algorithm and the detection unit. Then, the 3-1-1-2 compressor is designed and it is utilized in the multiplier. The proposed design-II is developed with modified Vedic algorithm, detection unit and proposed 3-1-1-2 compressor. Finally, the radix-2, radix-4, and radix-8 FFT butterflies are implemented using the detection unit based Vedic multiplier, the 3-1-1-2 compressor based multiplier and various existing multiplier. The proposed design-I and proposed design-II is designed and implemented in Spartan-6, Virtex-4 and Virtex-5 FPGA family devices. The proposed reconfigurable Vedic multiplier is simulated and synthesized using Synopsys tools using the 90 nm standard cell library.

A Modified Signal Flow Graph and Corresponding Conflict-Free Strategy for Memory-Based FFT Processor Design

This brief presents a modified radix-4 fast Fourier transform (FFT) signal flow graph, whose input and output both are in natural order. Compared with the conventional radix-4 signal flow graph, it does not buffer the result of the last stage or execute the bit-reverse operation to generate the result, but generates the result directly in the last stage. Thus, the number of iterations is reduced by one. In order to realize the proposed memory-based FFT processor by using the modified radix-4 FFT signal flow graph, a conflict-free strategy and corresponding memory-addressing scheme is proposed. At last, the hardware implementation for the proposed FFT processor is proposed. Through the adoption of this method, FFT processor of arbitrary point conforming to the radix-4 algorithm can be implemented. Compared with the previous memory-based FFT processors, the proposed FFT processor has less processing time under similar or lower resource consumption.

Design and implementation of an ultra-low energy FFT ASIC for processing ECG in Cardiac Pacemakers.

In embedded biomedical applications, spectrum analysis algorithms such as Fast Fourier Transform (FFT) are crucial for pattern detection and has been the focus of continued research. In deeply embedded systems such as cardiac pacemakers, FFT based signal processing is typically computed by Application Specific Integrated Circuits (ASIC) to achieve low power operation. This research proposes a data driven design approach for an FFT ASIC solution which exploits the limited range of data encountered by these embedded systems. The optimizations proposed in this paper uses the simple concept of Hashing and Look-Up Tables (LUT) to effectively reduce the number of arithmetic operations required to perform the FFT of an electrocardiogram (ECG) signal. By reducing the dynamic power consumption and overall energy footprint of FFT computation, the proposed design aims to achieve longer battery life for a Cardiac Pacemaker. The design is synthesized using a 90nm standard cell library, and gate level switching activity is simulated to obtain accurate power consumption results. The proposed optimizations achieved a low energy consumption of 27.72nJ per FFT, which is 14.22% lower than a standard 128-point radix-2 FFT when tested with actual ECG data collected from PhysioNet.

Signal-to-noise Ratio Study on Pipelined Fast Fourier Transform Processor

Fast Fourier transform (FFT) processor is a prevailing tool in converting signal in time domain to frequency domain. This paper provides signal-to-noise ratio (SNR) study on 16-point pipelined FFT processor implemented on field-programable gate array (FPGA). This processor can be used in vast digital signal applications such as wireless sensor network, digital video broadcasting and many more. These applications require accuracy in their data communication part, that is why SNR is an important analysis. SNR is a measure of signal strength relative to noise. The measurement is usually in decibles (dB). Previously, SNR studies have been carried out in software simulation, for example in Matlab. However, in this paper, pipelined FFT and SNR modules are developed in hardware form. SNR module is designed in Modelsim using Verilog code before implemented on FPGA board. The SNR module is connected directly to the output of the pipelined FFT module. Three different pipelined FFT with different architectures were studied. The result shows that SNR for radix-8 and R4SDC FFT architecture design are above 40dB, which represent a very excellent signal. SNR module on the FPGA and the SNR results of different pipelined FFT architecture can be consider as the novelty of this paper.

Automated Scalable Address Generation Patterns for 2-Dimensional Folding Schemes in Radix-2 FFT Implementations

Hardware-based implementations of the Fast Fourier Transform (FFT) are highly regarded as they provide improved performance characteristics with respect to software-based sequential solutions. Due to the high number of operations involved in calculations, most hardware-based FFT approaches completely or partially fold their structure to achieve an efficient use of resources. A folding operation requires a permutation block, which is typically implemented using either permutation logic or address generation. Addressing schemes offer resource-efficient advantages when compared to permutation logic. We propose a systematic and scalable procedure for generating permutation-based address patterns for any power-of-2 transform size algorithm and any folding factor in FFT cores. To support this procedure, we develop a mathematical formulation based on Kronecker products algebra for address sequence generation and data flow pattern in FFT core computations, a well-defined procedure for scaling address generation schemes, and an improved approach in the overall automated generation of FFT cores. We have also performed an analysis and comparison of the proposed hardware design performance with respect to a similar strategy reported in the recent literature in terms of clock latency, performance, and hardware resources. Evaluations were carried on a Xilinx Virtex-7 FPGA (Field Programmable Gate Array) used as implementation target.

An all-optical soliton FFT computational arrangement in the 3NLSE-domain

In this paper an all-optical soliton method for calculating the Fast Fourier Transform (FFT) algorithm is presented. The method comes as an extension of the calculation methods (soliton gates) as they become possible in the cubic non-linear Schrödinger equation (3NLSE) domain, and provides a further proof of the computational abilities of the scheme. The method involves collisions entirely between first order solitons in optical fibers whose propagation evolution is described by the 3NLSE. The main building block of the arrangement is the half-adder processor. Expanding around the half-adder processor, the “butterfly” calculation process is demonstrated using first order solitons, leading eventually to the realisation of an equivalent to a full Radix-2 FFT calculation algorithm.

8-Point RADIX-8 Pipelined FFT Using SDF

Fast Fourier Transform (FFT) operation is one of the most important fundamental operations in the digital signal processing systems. A new pipelined Radix-8 based Fast Fourier Transformation (FFT) architecture is designed for performing frequency transformation techniques. The objective of this design is to improve the speed and to reduce the area, delay and power. Radix-8 FFT, which is used to improve the speed of functioning by reducing the computational path. In the proposed new architecture named as ―Radix-8 SDF FFT‖. In this architecture, the numbers of stages are reduced to 75%. The SDF FFT is to increasing the processing speed of architecture. The performance evaluation of Radix-8 SDF FFT architecture is determined through Very Large Scale Integration (VLSI) system design environment. In the VLSI system design, less area utilization, low power consumption and high speed are the main parameters. Hence, the main goal of proposed architecture is to reduce hardware complexity, power consumption and increasing both speed and throughput of the system. Applications: Mobile Ad-hoc Network (MANET), Orthogonal Frequency Division Multiplexing (OFDM) System.

A Novel Vision-Based Classification System for Explosion Phenomena

The need for a proper design and implementation of adequate surveillance system for detecting and categorizing explosion phenomena is nowadays rising as a part of the development planning for risk reduction processes including mitigation and preparedness. In this context, we introduce state-of-the-art explosions classification using pattern recognition techniques. Consequently, we define seven patterns for some of explosion and non-explosion phenomena including: pyroclastic density currents, lava fountains, lava and tephra fallout, nuclear explosions, wildfires, fireworks, and sky clouds. Towards the classification goal, we collected a new dataset of 5327 2D RGB images that are used for training the classifier. Furthermore, in order to achieve high reliability in the proposed explosion classification system and to provide multiple analysis for the monitored phenomena, we propose employing multiple approaches for feature extraction on images including texture features, features in the spatial domain, and features in the transform domain. Texture features are measured on intensity levels using the Principal Component Analysis (PCA) algorithm to obtain the highest 100 eigenvectors and eigenvalues. Moreover, features in the spatial domain are calculated using amplitude features such as the YCbCr color model; then, PCA is used to reduce vectors’ dimensionality to 100 features. Lastly, features in the transform domain are calculated using Radix-2 Fast Fourier Transform (Radix-2 FFT), and PCA is then employed to extract the highest 100 eigenvectors. In addition, these textures, amplitude and frequency features are combined in an input vector of length 300 which provides a valuable insight into the images under consideration. Accordingly, these features are fed into a combiner to map the input frames to the desired outputs and divide the space into regions or categories. Thus, we propose to employ one-against-one multi-class degree-3 polynomial kernel Support Vector Machine (SVM). The efficiency of the proposed research methodology was evaluated on a totality of 980 frames that were retrieved from multiple YouTube videos. These videos were taken in real outdoor environments for the seven scenarios of the respective defined classes. As a result, we obtained an accuracy of 94.08%, and the total time for categorizing one frame was approximately 0.12 s.

Implementation of parallel FFT algorithm on a ternary optical computer

The Fast Fourier Transform (FFT) is widely used in modern digital signal processing systems. In order to improve the efficiency of FFT, parallel methods are often used to speed up FFT in high-speed real-time application environments. However, due to the restrictions of size, energy consumption, heat dissipation etc., traditional electronic methods are becoming unsuitable for FFT applications in certain areas, such as aviation, aerospace, etc. Due to its characteristics of a massive number of data bits and low energy consumption, the Ternary Optical Computer (TOC) is a potential solution for these special cases. To verify this possibility, we studied the design and implementation of a high-speed parallel FFT on a TOC. Through analysis of the traditional radix-2, radix-4, and radix-8 DIT FFT operation processes, several FFT algorithms with higher parallelism, implemented on TOC, are designed by taking advantage of the characteristics of TOC. The implementation processes of these algorithms and the differences between them are presented. Meanwhile, the clock cycles and hardware resources required for each algorithm are also discussed. Simulation results reveal that the FFT implementation method is accurate. The algorithms require less power and fewer clock cycles when implemented on a TOC compared to the traditional methods implemented on an FPGA. This provides a new possible solution for high-speed low-power FFT implementation.

Comparison Study of DIT and DIF Radix-2 FFT Algorithm

The fast fourier transform (FFT) is an important technique for image compression, digital signal processing and communication especially for application in multiple input multiple output OFDM system. The fast fourier transform are good algorithm and computed discrete fourier transform (DFT). In this paper, the comparison study of various FFT algorithm and compare all them. FFT algorithm is divided into two part i.e. decimation in time (DIT) and decimation in frequency (DIF). In DIT algorithm firstly computed multiplier then adder but in DIF firstly computed adder then multiplier. In this paper we study of different types of multiplier i.e. array multiplier; sing multiplier (Baugh Wooley) and complex multiplier. In proposed complex multiplier is consuming three multipliers. In further work in my dissertation in design to 8point, 16-point, 32-point, 64-point and 128-point radix FFT algorithm in different multiplier.

Simulation of 32-Point Split-Radix Multipath Delay Commutator (SRMDC) based FFT Architecture

Background: Fast Fourier Transform (FFT) processor is the important method in Orthogonal Frequency Division Multiplexing (OFDM) communication systems. Split-Radix Fast Fourier Transform (SRFFT) estimates the least number of multiplications compared to other FFT algorithm; hence SRFFT is the best for the implementation of low power FFT processor. Methods: In this paper, the proposed “pipelined 32-point Split-Radix Multi-path Delay Commutator (SFMDC) FFT” architecture is designed. The MDC architecture has advantages in reducing the low chip area and lower power consumption. The SR-FFT algorithm has changing the numbers of butterfly elements in successive stages. The 32-point SR-MDC FFT architecture is to determine the frequency transformation techniques. The Split-Radix FFT algorithm is based on radix-2 and radix-4 algorithm and it is related to mixed radix FFT. Findings: The performance evaluation of proposed architecture is determined through VLSI System. Less area, low power consumption and high speed are the main parameters in this design. The proposed structure provides high throughput rate and low hardware complexity. Improvements: The goal of this proposed work is to reduce the slices and LUTs and power consumption and also to enhance the performances of the FFT processor than the existing method. The proposed method has been evaluated by using ModelSim 6.3C and synthesis results has been validated by using Xilinx Plan ahead 12.4.