Radio Frequency Identification Tag Chip Research Articles

A bonding-less 5 GHz RFID module using inductive coupling between IC and antenna

This paper presents a bonding-less 5 GHz radio frequency identification (RFID) tag module using an 85% downsized RFID tag chip and a 97% downsized antenna. Inductive (or magnetic) coupling between the antenna and the chip realizes low cost bonding-less implementation. Compared with a conventional module operating in the UHF band, the proposed module operating in the 5 GHz range is downsized in terms of both the chip and the antenna sizes. The experimental results confirmed that the proposed RFID tag module successfully works at 20 cm away from a reader whose output power is 15 dBm, achieving the same figure of merit as a conventionally bonded module. Moreover, this paper confirmed that the misalignment tolerance of the inductive coupling can be up to 50 μm.

Compact Crossed Dipole Antenna With Meandered Series Power Divider for UHF RFID Tag and Handheld Reader Devices

A low-profile and meandered crossed dipole antenna design for ultrahigh-frequency (UHF) radio-frequency identification (RFID) circularly polarized (CP) tag or handheld reader application is described in this communication. The crossed dipole CP condition is obtained by employing a series power divider meandered at the center of the dielectric substrate, and a surrounding ring which acts as a T-match network guarantees impedance matching. The series power divider alleviates the problem of using a balun when the crossed dipole is fed with a 50 $\Omega $ coaxial cable. A prototype has been manufactured on a $56\times 56\times0.4\,\,\text {mm}^{3}$ FR4 dielectric substrate, and the measurement results show a $S_{11}\le -10$ dB bandwidth of more than 14.4% (865.6–1000 MHz), an axial ratio (AR) ≤ 3 dB bandwidth of 2.8% (906–932 MHz) which can essentially cover the Federal communications commission (FCC) UHF RFID band, and a broadside RHCP peak gain of 1.4 dBic at 919 MHz. When the antenna is connected to an RFID tag chip, excellent read range performance within the whole 902–928 MHz bandwidth has been demonstrated (with maximum values of 7 and 9.9 m when interrogated with a linearly polarized and a CP reader antenna, respectively).

A Fully Integrated HF RFID Tag Chip With LFSR-based Light-weight Tripling Mutual Authentication Protocol

Radio frequency identification (RFID) is widely used in various areas such as logistics, supply-chain management, and access control. The new challenge for designing an RFID tag is how to embed a low-cost and low-power consumption algorithm into a compact RFID tag chip. This paper presents a passive HF-band tag chip supporting ISO/IEC 14443 type A/B protocol with low-cost and low-power consumption. In the Analog Front End, a bridge rectifier with 73.76% power conversion efficiency is presented to accomplish RF-dc conversion. A robust demodulator with both 10% and 100% ASK demodulation capabilities and a subcarrier-based modulator are designed to complete the data transfer process. Moreover, a burr-eliminating power ON/OFF reset circuit is proposed to provide a reset signal for the system. In the digital baseband controller, a linear feedback shift register-based light-weight authentication protocol is presented to ensure data security while reducing resource overhead. The embedded 8-Kb EEPROM contains eight independent keys for eight different application fields. The tag chip is fabricated in HJ025 2P4M CMOS process with an area of 1.1mm $\times $ 1.18mm and total static power consumption of $116.45~\mu \text{W}$ . The low cost and low-power consumption ensure the tag chip, especially suitable for smart cards.

Self-Tuning RFID Tag: A New Approach for Temperature Sensing

This paper aims to present a further exploration on a new concept regarding the operation of an ultrahigh frequency (UHF) radio frequency identification (RFID) sensor tag. Exploiting the antenna of a UHF RFID tag as a temperature transducer and a UHF RFID chip with self-tuning capabilities as the means of communication, a UHF RFID tag can operate as a very low-power sensor with high read range and small size. The antenna of the tag is taking advantage of the intrinsic characteristics of the used substrate to vary its overall complex impedance according to temperature. These changes of the impedance of the antenna are leading the self-tuning circuit of the used RFID chip to self-tune and based on the value it acquires an estimation of the sensed temperature can be made. This paper also reports a design and a set of measurements of a UHF RFID tag transformed to act as a temperature sensor. This concept is further explored for the assessment of the contribution of each of the constituents of the UHF RFID tag, i.e., antenna and UHF RFID chip, to the sensing procedure. This paper is accompanied by the simulation of a designed 3-D model of the UHF RFID sensor tag and by sets of measurement of the impedances of the UHF RFID chip and of the antenna.

CDTA

The Internet of Things (IoT) is transforming the way we live and work by increasing the connectedness of people and things on a scale that was once unimaginable. However, the vulnerabilities in the IoT supply chain have raised serious concerns about the security and trustworthiness of IoT devices and components within them. Testing for device provenance, detection of counterfeit integrated circuits (ICs) and systems, and traceability of IoT devices are challenging issues to address. In this article, we develop a novel radio-frequency identification (RFID)-based system suitable for counterfeit detection, traceability, and authentication in the IoT supply chain called CDTA . CDTA is composed of different types of on-chip sensors and in-system structures that collect necessary information to detect multiple counterfeit IC types (recycled, cloned, etc.), track and trace IoT devices, and verify the overall system authenticity. Central to CDTA is an RFID tag employed as storage and a channel to read the information from different types of chips on the printed circuit board (PCB) in both power-on and power-off scenarios. CDTA sensor data can also be sent to the remote server for authentication via an encrypted Ethernet channel when the IoT device is deployed in the field. A novel board ID generator is implemented by combining outputs of physical unclonable functions (PUFs) embedded in the RFID tag and different chips on the PCB. A light-weight RFID protocol is proposed to enable mutual authentication between RFID readers and tags. We also implement a secure interchip communication on the PCB. Simulations and experimental results using Spartan 3E FPGAs demonstrate the effectiveness of this system. The efficiency of the radio-frequency (RF) communication has also been verified via a PCB prototype with a printed slot antenna.

Construction material mountable UHF RFID tag antenna

ABSTRACTThis article presents a tag antenna for radio frequency identification (RFID)‐based wireless structural health monitoring systems. An ultra‐high frequency (UHF) microstrip patch tag antenna is designed with a new generation RFID tag chip for the Australian UHF RFID frequency band. Simulation studies with optimized slits demonstrate the ability of the antenna to tolerate the influence of construction materials such as concrete and metal on its resonant frequency, maximum gain, and read range. Noncontact measurement of the resonant frequency and experimental verification of the maximum gain of the fabricated tag antenna show good agreement with simulated performance. Read range measurements are conducted to verify the performance of the tag antenna on metal structures. It is also shown that the proposed tag antenna can be easily modified to operate in other UHF RFID frequency bands. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:2231–2237, 2016

Design and Implementation of An ECC-Based Digital Baseband Controller for RFID Tag Chip

The extremely constrained resource has hindered the efforts to implement the elliptic curve cryptography (ECC) into a radio-frequency identification (RFID) tag chip. In this paper, an ECC-based RFID digital baseband controller (DBC), which is compatible with ISO/IEC 14443 and Schnorr authentication protocol, is presented. In order to achieve low resources consumption and fast ECC computation speed, some techniques, such as the register reuse, clock multiplexer, and asynchronous counter, are adopted in this design. In addition, a linear feedback shift register-based stream encryption scenario is proposed for the data security. According to the synthesis result, the gate area and power consumption of DBC are 25.7 K and 14.7 $\mu\hbox{W}$ , respectively, in UMC 0.13 $\mu\hbox{m}$ CMOS technology. All of those characteristics make the realization of ECC-based DBC for RFID tag chip promising.

An Advanced Verification Platform Based on UVM

An advanced verification platfrom based on UVM architecture is implemented in this paper. This paper presents a hierarchical verification environment that is portable, reusable, and easy to extend, which is constructed based on an object oriented language named System Verilog. The verification platform is applied to verify a RFID (Radio Frequency Identification) tag chip which is compliant with the ISO/IEC15693 standard, communicates with a reader outside through a RF analog circuitry, completes anti-collision flow, selects card, authenticates based on SM7 algorithm and controls the writing and reading of EEPROM inside. According to the instruction supported by the tag chip is wide and variety, and further more it’s very rich in the command frame contents, the advanced verification platform which achieves the constraint-random stimulus generation, functional coverage and self-check mechanism, reduces the verification cycle, improves verification efficiency and ensures verification adequacy.

Design of an Elliptic Curve Cryptography processor for RFID tag chips.

Radio Frequency Identification (RFID) is an important technique for wireless sensor networks and the Internet of Things. Recently, considerable research has been performed in the combination of public key cryptography and RFID. In this paper, an efficient architecture of Elliptic Curve Cryptography (ECC) Processor for RFID tag chip is presented. We adopt a new inversion algorithm which requires fewer registers to store variables than the traditional schemes. A new method for coordinate swapping is proposed, which can reduce the complexity of the controller and shorten the time of iterative calculation effectively. A modified circular shift register architecture is presented in this paper, which is an effective way to reduce the area of register files. Clock gating and asynchronous counter are exploited to reduce the power consumption. The simulation and synthesis results show that the time needed for one elliptic curve scalar point multiplication over GF(2163) is 176.7 K clock cycles and the gate area is 13.8 K with UMC 0.13 μm Complementary Metal Oxide Semiconductor (CMOS) technology. Moreover, the low power and low cost consumption make the Elliptic Curve Cryptography Processor (ECP) a prospective candidate for application in the RFID tag chip.

Design and implementation of a RF powering circuit for RFID tags or other batteryless embedded devices.

A RF powering circuit used in radio-frequency identification (RFID) tags and other batteryless embedded devices is presented in this paper. The RF powering circuit harvests energy from electromagnetic waves and converts the RF energy to a stable voltage source. Analysis of a NMOS gate-cross connected bridge rectifier is conducted to demonstrate relationship between device sizes and power conversion efficiency (PCE) of the rectifier. A rectifier with 38.54% PCE under normal working conditions is designed. Moreover, a stable voltage regulator with a temperature and voltage optimizing strategy including adoption of a combination resistor is developed, which is able to accommodate a large input range of 4 V to 12 V and be immune to temperature variations. Latch-up prevention and noise isolation methods in layout design are also presented. Designed with the HJTC 0.25 μm process, this regulator achieves 0.04 mV/°C temperature rejection ratio (TRR) and 2.5 mV/V voltage rejection ratio (VRR). The RF powering circuit is also fabricated in the HJTC 0.25 μm process. The area of the RF powering circuit is 0.23 × 0.24 mm2. The RF powering circuit is successfully integrated with ISO/IEC 15693-compatible and ISO/IEC 14443-compatible RFID tag chips.

A Novel Design of PIE Decoding with Multiple CRC Circuit for RFID Tag

This paper proposes a new synchronized serial-parallel CRC(Cycle Redundancy Check) with PIE(Pulse Interval Encoding) decoding circuit for the UHF(Ultra-High Frequency) RFID(Radio Frequency Identification), which is based on the ISO/IEC 18000-6C standards protocol. The parallel algorithm of CRC circuit is derived, and the serial or parallel CRC circuit on RFID tag chip is evaluated in this paper. Finally, the designed circuit is simulated and analyzed on the FPGA platform. Simulation results show that the proposed circuit meets the communication requirement of the protocol and addresses the problem of low data processing rate of conventional serial CRC circuit, as well as implements 1 to 8 degree of parallelism of the parallel CRC circuit for UHF RFID.

A low‐cost UHF RFID tag chip with AES cryptography engine

ABSTRACTIn this paper, the design of a low‐cost ultra‐high‐frequency (UHF) Radio Frequency IDentification (RFID) tag chip with an advanced encryption standard (AES) cryptographic engine is presented. The design of digital baseband is verified on a Field‐Programmable Gate Array (FPGA) platform. The whole chip, including a radio frequency frontend, an analog frontend, an Electrically Erasable Programmable Read‐Only Memory (EEPROM), and a baseband with AES engine, is taped out on Semiconductor Manufacturing International Corporation (SMIC) 0.13μm process. The chip area is 1 × 1 mm2, in which 0.6 × 0.3 mm2 is covered by the digital baseband. The power consumption of the entire tag chip is 20.9 μW. The design can work on both two modes of the standard ISO 18000‐6C mode and the security enhanced ISO 18000‐6C mode. To the best of our knowledge, it is the first UHF passive RFID tag chip with AES algorithm in the baseband.

Simple high-sensitivity voltage multiplier for UHF-band semi-passive radio frequency identification tags using a standard CMOS process

The authors present a new, simple approach for creating a high-sensitivity voltage multiplier for ultra high frequency (UHF)-band (900 MHz) semi-passive radio frequency identification (RFID) tag chips. The multiplier was implemented in standard digital complementary metal-oxide semiconductor (CMOS) process without using optional processes such as low-threshold transistors, Schottky diodes and metal insulator-metal capacitors. Instead, a new threshold cancellation circuit effectively reduced the threshold voltage of the transistors in a 0.18 m standard CMOS process. The multiplier, including the new threshold cancellation circuit, is also very compact (0.14 mm 2 ). Thus, the current result provides a cost-effective solution for semi-passive RFID tag chips. Measurement of the multiplier showed that it can generate a 1.2 V output voltage for an input power as low as 14 dBm at 900 MHz. The measured sensitivity of the multiplier is one of the best among the multipliers fabricated using low-threshold transistors and Schottky diodes. The result shows that a high sensitivity RFID tag chip is achievable using a standard CMOS process without optional processes.

Metal-ferroelectric-metal capacitor based persistent memory for electronic product code class-1 generation-2 uhf passive radio-frequency identification tag

With the circuits using metal-ferroelectric-metal (MFM) capacitor, rf operational signal properties are almost the same or superior to those of polysilicon-insulator-polysilicon, metal-insulator-metal, and metal-oxide-semiconductor (MOS) capacitors. In electronic product code global class-1 generation-2 uhf radio-frequency identification (RFID) protocols, the MFM can play a crucial role in satisfying the specifications of the inventoried flag’s persistence times (Tpt) for each session (S0–S3, SL). In this paper, we propose and design a new MFM capacitor based memory scheme of which persistence time for S1 flag is measured at 2.2 s as well as indefinite for S2, S3, and SL flags during the period of power-on. A ferroelectric random access memory embedded RFID tag chip is fabricated with an industry-standard complementary MOS process. The chip size is around 500×500 μm2 and the measured power consumption is about 10 μW.

A High Sensitivity, CoSi$_{2}$–Si Schottky Diode Voltage Multiplier for UHF-Band Passive RFID Tag Chips

A ultra high frequency (UHF)-band high sensitivity voltage multiplier was designed based on Cobalt-Salicide (CoSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> )-Silicon Schottky diodes fabricated in scaled-down 0.18 mum CMOS technology. With low sheet resistance of optimized CoSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -Si Schottky diode, the voltage multiplier using the diode resulted in superior power sensitivity compared to low-threshold (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ) metal oxide semiconductor field effect transistors. Various multipliers with different diode sizes were fabricated and their sensitivities were compared. Under the operating current level of radio frequency identification (RFID) tag chips ( ~ muA), the voltage multipliers possessing smaller diodes showed better sensitivity due to higher <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i> -factor. An optimized five-stage voltage multiplier required an input power of - 19.5 dBm for a 1.2 V output voltage at 900 MHz. The measured sensitivity is the lowest for any UHF-band multiplier for passive RFID tag chips. This result based on scaled-down CMOS technology provides increased RFID operation range as well as higher processing power at lower power consumption.

A small OCA on a 1/spl times/0.5-mm/sup 2/ 2.45-GHz RFID Tag-design and integration based on a CMOS-compatible manufacturing technology

This letter reports, for the first time, on the design strategy and process integration for a small on-chip-antenna (OCA) with a radio-frequency identification (RFID) tag chip-area /spl sim/1/spl times/0.5 mm/sup 2/. It is designed based on a 2.45-GHz RFID tag circuit with an inductive-coupling model. A patterned Al shielding layer is used to improve the consistency of the actual performance obtained from fabricated devices and those predicated from the design. The antenna's inductor coils were fabricated based on a conventional Cu-Damascene process. To achieve the required antenna performance (e.g., Q-factor), a set of thick USG and deep-via etch processes were specifically developed. Our results demonstrate that the dc power converted by the OCA is sufficient to enable the RFID tag chip to communicate with a corresponding 2.45-GHz RFID reader with a 1-mm distance.