Radiation-induced Leakage Current Research Articles

Dummy Gate-Assisted n-MOSFET Layout for a Radiation-Tolerant Integrated Circuit

A dummy gate-assisted n-type metal oxide semiconductor field effect transistor (DGA n-MOSFET) layout was evaluated to demonstrate its effectiveness at mitigating radiation-induced leakage currents in a conventional n-MOSFET. In the proposed DGA n-MOSFET layout, radiation-induced leakage currents are settled by isolating both the source and drain from the sidewall oxides using a p+ layer and dummy gates. Moreover, the dummy gates and dummy Metal-1 layers are expected to suppress the charge trapping in the sidewall oxides. The inherent structure of the DGA n-MOSFET supplements the drawbacks of the enclosed layout transistor, which is also proposed in order to improve radiation tolerance characteristics. The V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> -I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> simulation results of the DGA n-MOSFET layout demonstrated the effectiveness of eliminating such radiation-induced leakage current paths. Furthermore, the radiation exposure experimental results obtained with the fabricated DGA n-MOSFET layout also exhibited good performance with regard to the total ionizing dose tolerance.

A Low-Power, Radiation-Resistant ASIC for SDD-Based X-Ray Spectrometers

We present an Application Specific Integrated Circuit (ASIC) for high resolution X-ray spectrometers (XRS) in radiation harsh environment (such as Jovian system). The ASIC was designed to read out signals from low resistivity pixelated Silicon-Drift-Detectors (SDD) to ensure radiation hardness. The readout is done by wire-bonding the anodes to the inputs of the ASIC. The ASIC dissipates 32 mW and provides 16 channels of low-noise charge amplification, high-order shaping with baseline stabilization, discrimination, pile-up rejection, and peak detection with analog memory. The readout is sparse and based on a custom low-power tri-stable low-voltage differential signaling digital interface. A unit of 64 SDD pixels, read out by four ASICs, covers an area of 12.8 cm2, and dissipates less than 20 mW/cm2. The ASICs were powered on and irradiated using a beam line with 203 MeV protons, to total doses ranging from 0.25 Mrad to 12 Mrad. Performance degradation due to radiation-induced leakage current was observed to peak around 2 Mrad dose. Critical contributors to the degradation were identified through simulation and measurements, and corresponding circuitry was thus modified to address the issues. Measurements on the radiation-resistant design have shown excellent radiation resistance at total doses ranging from 1 to 8 Mrad.

Radiation-hardened gate-around n-MOSFET structure for radiation-tolerant application-specific integrated circuits

To overcome the total ionizing dose effect on an n-type metal-oxide-semiconductor field-effect transistor (n-MOSFET), we designed a radiation-hardened gate-around n-MOSFET structure and evaluated it through a radiation-exposure experiment. Each test device was fabricated in a commercial 0.35-micron complementary metal-oxide-semiconductor (CMOS) process. The fabricated devices were evaluated under a total dose of 1 Mrad (Si) at a dose rate of 250 krad/h to obtain very high reliability for space electronics. The experimental results showed that the gate-around n-MOSFET structure had very good performance against 1 Mrad (Si) of gamma radiation, while the conventional n-MOSFET experienced a considerable amount of radiation-induced leakage current. Furthermore, a source follower designed with the gate-around transistor worked properly at 1 Mrad (Si) of gamma radiation while a source follower designed with the conventional n-MOSFET lost its functionality.

The impact of device width on the variability of post-irradiation leakage currents in 90 and 65 nm CMOS technologies

The impact of device width on the variability of radiation-induced leakage currents in 90nm and 65nm CMOS technologies is investigated. The off-state leakage current variability increases with decreasing channel width for both technologies, and with increasing total ionizing dose for three different process variants from the 90nm technology. More variability is observed for narrow width devices compared to wider devices before and after irradiation. Device-to-device variability is compared for two technologies (65 and 90nm) and three process variants (low, standard, and high threshold voltage). These results illustrate the importance of process-induced variability on the radiation response of MOS devices and integrated circuits.

Study of radiation-induced leakage current between adjacent devices in a CMOS integrated circuit

Radiation-induced inter-device leakage is studied using an analytical model and TCAD simulation. There were some different opinions in understanding the process of defect build-up in trench oxide and parasitic leakage path turning on from earlier studies. To reanalyze this problem and make it beyond argument, every possible variable is considered using theoretical analysis, not just the change of electric field or oxide thickness independently. Among all possible inter-device leakage paths, parasitic structures with N-well as both drain and source are comparatively more sensitive to the total dose effect when a voltage discrepancy exists between the drain and source region. Since N-well regions are commonly connected to the same power supply, these kinds of structures will not be a problem in a real CMOS integrated circuit. Generally speaking, conduction paths of inter-device leakage existing in a real integrated circuit and under real electrical circumstances are not very sensitive to the total ionizing dose effect.

Layout-Related Stress Effects on Radiation-Induced Leakage Current

The effects of shallow-trench-isolation-induced mechanical stress on radiation-induced off-state leakage current are reported in 90-nm NMOS devices. The radiation-induced leakage current increases with increasing active device-to-isolation spacing. The leakage current also depends on channel width; narrow devices exhibit less leakage before irradiation, but more after irradiation. These geometrical factors affect the mechanical stress in the device, which impact the dopant diffusion and activation and the charge trapping in the STI oxide. The combined effects of these layout-related phenomena affect the sensitivity to radiation-induced charge.

Impact of Radiation on the Operation and Reliability of Deep Submicron CMOS Technologies

CMOS scaling has a beneficial impact on the radiation hardness of the technologies and often only requires a further optimization of either the Shallow Trench Isolation (STI) or the Buried Oxide (BOX) in case of a SOI technology. From a reliability viewpoint, heavy-ion induced ionization damage in the gate dielectric may lead to Radiation-Induced Leakage Current (RILC), Radiation-induced Soft Breakdown (RSB), Single Event Gate Rupture (SEGR) or the creation of latent damage. This paper discusses the present knowledge of the radiation impact on the operation and the reliability of deep submicron CMOS technologies.

TID and Displacement Damage Effects in Vertical and Lateral Power MOSFETs for Integrated DC-DC Converters

TID and displacement damage effects are studied for vertical and lateral power MOSFETs in five different technologies in view of the development of radiation-tolerant fully integrated DC-DC converters. Investigation is pushed to the very high level of radiation expected for an upgrade to the LHC experiments. TID induces threshold voltage shifts and, in n-channel transistors, source-drain leakage currents. Wide variability in the magnitude of these effects is observed. Displacement damage increases the on-resistance of both vertical and lateral high-voltage transistors. In the latter case, degradation at high particle fluence might lead to a distortion of the output characteristics curve. HBD techniques to limit or eliminate the radiation-induced leakage currents are successfully applied to these high-voltage transistors, but have to be used carefully to avoid consequences on the breakdown voltage.

Modeling Ionizing Radiation Effects in Solid State Materials and CMOS Devices

A comprehensive model is presented which enables the effects of ionizing radiation on bulk CMOS devices and integrated circuits to be simulated with closed form functions. The model adapts general equations for defect formation in uniform SiO2 films to facilitate analytical calculations of trapped charge and interface trap buildup in structurally irregular and radiation sensitive shallow trench isolation (STI) oxides. A new approach whereby non-uniform defect distributions along the STI sidewall are calculated, integrated into implicit surface potential equations, and ultimately used to model radiation-induced ldquoedgerdquo leakage currents in n-channel MOSFETs is described. The results of the modeling approach are compared to experimental data obtained on 130 nm and 90 nm devices. The features having the greatest impact on the increased radiation tolerance of advanced deep-submicron bulk CMOS technologies are also discussed. These features include increased doping levels along the STI sidewall.

Contribution of Latent Defects Induced by High-Energy Heavy Ion Irradiation on the Gate Oxide Breakdown

From annealing and electrical stress experiments performed on irradiated MOS devices, swift energetic ions-induced morphological oxide defects are shown to act as a contributing part of the oxide breakdown occurring during post gate stress, without being possibly electrically detected before the onset of breakdown itself. A reduction of the charge to breakdown and an increase of the radiation-induced leakage current were first observed after irradiation. Then, leakage current has been shown to be fully removable using isochronal annealing while charge to breakdown was not increased back to its initial value.

Effects of Moisture and Hydrogen Exposure on Radiation-Induced MOS Device Degradation and Its Implications for Long-Term Aging

Transistors and ICs built in several different captive and commercial facilities were exposed to moisture, irradiated, and annealed. The moisture exposures were performed using highly accelerated stress test (HAST) at 130degC and 85% relative humidity. Irradiation of n-channel transistors exposed to HAST followed by a long-term anneal resulted in some increase in interface-trap and oxide-trapped charge buildup. However, exposing p-channel transistors to HAST preirradiation resulted in extremely large and unexpected voltage shifts immediately following irradiation. They were observed for devices with either doped oxide or nitride final chip passivation. Because of this, nitride passivation may not be sufficient to prevent H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O from causing enhanced radiation-induced degradation over long time periods in some devices (e.g., commercial devices with nitride final chip passivation packaged in plastic packages). The smaller voltage shifts for the n-channel transistors may be related to the formation of phosphosilicate glass (PSG) overlying the sources and drains of the n-channel transistors impeding the diffusion of moisture to the gate oxides. It is shown that, the large radiation-induced voltage shifts for the p-channel transistors can lead to enhanced IC parametric degradation and functional failure at lower radiation levels. Large increases in radiation-induced field oxide leakage current were also observed for transistors exposed to HAST preirradiation. Transistors were also annealed (prior to irradiation) and irradiated in H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> . Approximately the same level of radiation-induced degradation was observed for n- and p-channel transistors suggesting that the diffusion kinetics for H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> diffusion are considerably different than for H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O diffusion. These results raise the concern that exposure of devices to moisture or hydrogen can lead to long-term radiation-induced aging effects.

The Effects of Proton Irradiation on the Performance of High-Voltage n-MOSFETs Implemented in a Low-Voltage SiGe BiCMOS Platform

This paper presents the first comprehensive investigation of the impact of proton irradiation on the performance of high-voltage (HV) nMOS transistors implemented in a low-voltage (LV) SiGe BiCMOS technology. The effects of irradiation gate bias, irradiation substrate bias, and operating substrate bias on the radiation response of these transistors are examined. Experimental results show that the radiation-induced subthreshold leakage current under different irradiation biasing conditions remains negligible after exposure to a total dose of 600 krad(Si). We find that there are differences in the radiation response of LV and HV MOSFETs, suggesting that the mechanisms involved in causing degradation in LV and HV transistors could be of fundamentally different origins.

Soft Error Trends and New Physical Model for Ionizing Dose Effects in Double Gate Z-RAM Cell

We model the soft error trends and total ionizing dose (TID) effects in floating body capacitorless DRAM (Z-RAM) cell. We find that soft error rates (SER) in Z-RAM scales strongly with cell body thickness. We propose a new physical model for TID effects in thin (les 10 nm) oxides. This model is based on injection of hot carriers into the oxide which are generated by particle strikes and is relevant for thin oxides in any MOS device. We utilize hydrodynamic approach and Monte Carlo method to implement our model. The primary radiation interaction is simulated by using Geant4-a toolkit for the simulation of particle interaction and transport through matter. The preliminary results of our model match well with radiation-induced leakage current (RILC) vs. dose data.

The Application of RHBD to n-MOSFETs Intended for Use in Cryogenic-Temperature Radiation Environments

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Proton and X-ray irradiation effects are investigated in 0.35 <formula formulatype="inline"><tex>$\mu$</tex></formula>m conventional, annular, and ringed-source radiation-hardening-by-design (RHBD) CMOS devices. Transistors were irradiated with protons at both 300 K and 77 K. Radiation-induced oxide trapped charges in the shallow trench isolation (STI) oxide deplete the p-substrate and effectively shunt the source and drain, inducing off-state leakage. Without the STI, RHBD nFETs exhibit no radiation-induced off-state shunt leakage currents for devices irradiated at both 300 K and 77 K . Conventional 0.35 <formula formulatype="inline"><tex>$\mu$</tex></formula>m pFETs were not degraded by proton irradiation, since the leakage path cannot be formed in the n-well. A simple CMOS logic inverter shows no degradation in output voltage after proton irradiation for all tested temperature and bias conditions. More advanced 130 nm node nFETs show less TID sensitivity to STI leakage due possibly to the smaller physical STI volume and/or additional doping located on the STI sidewall. </para>

Total Ionizing Dose Hardness Assurance Issues for High Dose Rate Environments

Transistors and ICs were irradiated at dose rates from 0.2 to 2times10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> rad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> )/s using a wide range of radiation sources. The mechanisms causing parametric IC failure varied with dose rate. At low dose rates from 0.2 to 100 rad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> )/s, parametric IC failure in these devices was dominated by radiation-induced degradation of the gate oxide transistors. At dose rates from 1.8times10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> rad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> )/s, parametric IC degradation was dominated by large increases in radiation-induced parasitic field oxide leakage current. At very high dose rates of 2times10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> rad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> )/s, no parametric failure was observed due to debiasing effects caused by rail-span collapse. These differences in dose rate response can make hardness assurance testing for high dose rate environments very challenging. Simple ldquoovertestsrdquo at dose rates from 50 to 300 rad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> )/s may greatly underestimate the radiation hardness of ICs in high dose rate environments. Because the failure mechanism may vary with dose rate, circuit design, and/or device technology, the best procedure for ensuring IC radiation hardness in greater than 300 rad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> )/s environments is to use radiation sources that mimic the system environment.

Variability in FG Memories Performance After Irradiation

Every time a heavy ion crosses a programmed Floating Gate (FG) in a nonvolatile memory array, it quickly discharges the FG and it produces a number of defects in the tunnel oxide, depending on its linear energy transfer (LET). These defects can build up a multitrap assisted tunneling path which allows electrons stored in the FG to escape it, every time the FG is programmed after irradiation [this phenomenon is called radiation-induced leakage current (RILC)]. We are showing by using retention and gate stress experiments that RILC has peculiar erratic characteristics, similar to those found for stress-induced leakage current (SILC). The erratic behavior is due to changes in the occupation states on defects, resulting in orders-of-magnitude changes in the tiny (Lt1 fA) current responsible for the FG discharge

Secondary Effects of Single Ions on Floating Gate Memory Cells

A programmed Floating Gate (FG) hit by a heavy ion experiences a large charge loss, which degrades the stored information. However, as a result of irradiation, even FGs not directly hit by ions can experience a shift in the programmed threshold voltage. These latter FGs can be found only in novel technologies with very small floating gates. Further, they have particular characteristics when compared to the cells directly hit by an ion: are characterized by a tendency to cluster, feature a peculiar threshold voltage distribution after irradiation, and do not experience radiation induced leakage current. These FGs are probably generated by ions crossing the device close enough to the floating gate, without directly hitting it

Effects of Total Dose Irradiation on Single-Event Upset Hardness

The effect of total dose on SEU hardness is investigated as a function of temperature and power supply voltage to determine worst-case hardness assurance test conditions for space environments. SRAMs from six different vendors were characterized for single-event upset (SEU) hardness at proton energies from 20 to 500 MeV and at temperatures of 25 and 80degC after total dose irradiating the SRAMs with either protons, Co-60 gamma rays, or low-energy x-rays. It is shown that total dose irradiation and the memory pattern written to the memory array during total dose irradiation and SEU characterization can substantially affect SEU hardness for some SRAMs. For one SRAM, the memory pattern made more than two orders of magnitude difference in SEU cross section at the highest total dose level examined. For all SRAMs investigated, the memory pattern that led to the largest increase in SEU cross section was the same memory pattern that led to the maximum increase in total-dose induced power supply leakage current. In addition, it is shown that increasing the temperature during SEU characterization can also increase the effect of total dose on SEU hardness. As a result, worst-case SEU hardness assurance test conditions are the maximum total dose and temperature of the system environment, and the minimum operating voltage of the SRAM. Possible screens for determining whether or not the SEU cross section of an SRAM will vary with total dose, based on the magnitude of the increase in power supply leakage current with total dose or the variation in SEU cross section with power supply voltage, have been suggested. In contrast to previous works, our results using selective area x-ray irradiations show that the source of the effect of total dose on SEU hardness is radiation-induced leakage currents in the memory cells. The increase in SEU cross section with total dose appears to be consistent with radiation-induced currents originating in the memory cells affecting the output bias levels of bias level shift circuitry used to control the voltage levels to the memory cells and/or due to the lowering of the noise margin of individual memory cells caused by radiation-induced leakage currents

Radiation induced leakage current in floating gate memory cells

Single ions impacting on SiO/sub 2/ layers generate tracks of defects which may result in a Radiation Induced Leakage Current (RILC). This current is usually studied as the cumulative effect of ion-induced defects in capacitors with ultra-thin oxides. We are demonstrating and modeling this phenomenon in 10 nm oxides by using Floating Gate memories. The impact of a single, high-LET ion can result in severe retention problems, due to several electrically active defects, which cooperate to slowly discharge the FG. We are also proposing innovative simulation tools to reproduce this phenomenon. Results from simulations fully explain our results, and also agree with existing data on thinner (4 nm) oxides.

IONIZING RADIATION EFFECTS ON ULTRA-THIN OXIDE MOS STRUCTURES

We have briefly reviewed the most important degradation mechanisms affecting ultra-thin gate oxides after exposure to ionizing irradiation. The increase of the gate leakage current seems the most crucial issue for device lifetime, especially for non-volatile memory and dynamic logic. The build-up of positive charge in the oxide and the subsequent threshold voltage shift, which was the major concern for thicker oxide, are no longer appreciable in today's devices due to the reduced oxide thickness permitting a fast recombination of trapped holes with electrons from interfaces. Among the leakage currents affecting thin oxides we have considered here the Radiation Induced Leakage Current (RILC) and the Radiation Soft Breakdown (RSB). RILC is observed after irradiation with a low Linear Energy Transfer (LET) radiation source and comes from a trap-assisted tunneling of electrons mediated by the neutral traps produced by irradiation. RILC depends on the applied bias during irradiation and the maximum is measured when devices are biased in flat band. Contrarily to RILC, RSB is observed after irradiation with high LET ions and derives from the formation of several conductive paths across the oxide corresponding to the ion hits. RSB conduction is explained by the theory of the Quantum Point Contact as also proposed for the electrically induced Soft breakdown. Finally, we present some preliminary results, which indicate that although the direct effects of irradiation (in terms of gate leakage current increase) are small for oxide thinner than 3nm, it is possible that these devices may experience an accelerated wear-out and/or breakdown after subsequent electrical stress relative to a fresh (not irradiated) device.