Radiation-induced Charge Buildup Research Articles

Investigation of Radiation Hardening by Back-Channel Adjustment in PDSOI MOSFETs

Total ionizing dose (TID) degradation is caused by radiation-induced charge buildup in oxides. Radiation hardening of silicon-on-insulator (SOI) devices with deep submicrometer nodes or nanonodes is mainly concerned with the field oxide and buried oxide. In this article, a back-channel adjustment technique for TID hardening is proposed. The technique is compatible with the 130-nm partially depleted silicon on an insulator (PDSOI) commercial process with no extra effort applied to the design. After testing the key electrical parameters and characterizing the radiation tolerance of the typical T-gate I/O nMOS devices, the results show that the radiation tolerance of the devices can reach more than 1 Mrad(Si) with the back-channel adjustment technique, and electrical performance is comparable to that of commercial process devices.

Low Dose Rate Effects in Silicon-Based Devices and Integrated Circuits: A Review

The total ionizing dose effects in silicon-based semiconductor devices (SDs) and integrated circuits (ICs) under conditions of low dose rate irradiation typical of space applications are surveyed. The mechanism of radiation-induced charge buildup in the dielectric of MOS structures and at the semiconductor/dielectric interface is considered. In addition, the nature of defects in the Si/SiO2 structure responsible for these processes is analyzed. The specific features of annealing the charge trapped in a dielectric during irradiation and also of interface traps (surface states, SSs) are shown. The peculiarities of the degradation of MOS and bipolar devices are considered for low dose rate irradiation conditions typical of space applications. It is shown that under low dose rate irradiation, MOS devices are prone to time-dependent effects which are determined by the kinetics of charge buildup and annealing in the Si/SiO2 structure, whereas bipolar devices may be susceptible to true dose rate effects. The main experimental methods of modeling low dose rate effects during accelerated tests of silicon devices and integrated circuits are surveyed. The necessity of using fundamentally different experimental approaches in modeling the time-dependent effects in MOS devices and the true dose rate effects in bipolar devices and integrated circuits is demonstrated.

10 μ m-thick four-quadrant transmissive silicon photodiodes for beam position monitor application: electrical characterization and gamma irradiation effects

Silicon photodiodes are very useful devices as X-ray beam monitors in synchrotron radiation beamlines. Owing to Si absorption, devices thinner than 10 μ m are needed to achieve transmission over 90% for energies above 10 keV . In this work, new segmented four-quadrant diodes for beam alignment purposes are fabricated on both ultrathin (10 μ m-thick) and bulk silicon substrates. Four-quadrant diodes implementing different design parameters as well as auxiliary test structures (single diodes and MOS capacitors) are studied. An extensive electrical characterization, including current-voltage (I-V) and capacitance-voltage (C-V) techniques, is carried out on non-irradiated and gamma-irradiated devices up to 100 Mrad doses. Special attention is devoted to the study of radiation-induced charge build-up in diode interquadrant isolation dielectric, as well as its impact on device interquadrant resistance. Finally, the devices have been characterized with an 8 keV laboratory X-ray source at 108 ph/s and in BL13-XALOC ALBA Synchroton beamline with 1011 ph/s and energies from 6 to 16 keV . Sensitivity, spatial resolution and uniformity of the devices have been evaluated.

Total ionizing dose radiation effects on NMOS parasitic transistors in advanced bulk CMOS technology devices**Project supported by the National Natural Science Foundation of China (No. 11305126).

In this paper, total ionizing dose effect of NMOS transistors in advanced CMOS technology are examined. The radiation tests are performed at 60Co sources at the dose rate of 50 rad (Si)/s. The investigation's results show that the radiation-induced charge buildup in the gate oxide can be ignored, and the field oxide isolation structure is the main total dose problem. The total ionizing dose (TID) radiation effects of field oxide parasitic transistors are studied in detail. An analytical model of radiation defect charge induced by TID damage in field oxide is established. The I – V characteristics of the NMOS parasitic transistors at different doses are modeled by using a surface potential method. The modeling method is verified by the experimental I – V characteristics of 180 nm commercial NMOS device induced by TID radiation at different doses. The model results are in good agreement with the radiation experimental results, which shows the analytical model can accurately predict the radiation response characteristics of advanced bulk CMOS technology device.

Effects of Moisture on Radiation-Induced Degradation in CMOS SOI Transistors

The effects of moisture on radiation-induced charge buildup in the oxides of a 0.35 μm SOI technology are explored. Data show no observable effects of moisture-related aging on radiation hardness. These results are in contrast to those of previous work performed on bulk MOS technologies fabricated in the 1980s. The cause of these differences do not appear to be due to differences in final chip passivation layers. Instead, other processing variables (including the use of different implant materials and thicker overlayers) may account for these differences. In any case, the SOI technology results indicate that not all advanced technologies exposed to moisture are necessarily susceptible to significant long-term radiation-induced aging effects.

An Embeddable SOI Radiation Sensor

The feasibility of developing an embeddable silicon-on-insulator (SOI) buried oxide MOS dosimeter (RadFET) has been demonstrated. This dosimeter takes advantage of the inherent properties for radiation-induced charge buildup in the buried oxides of commercial SOI wafers. Discrete SOI buried oxide RadFETs and fully-functional read-out circuitry have been fabricated in Sandia's CMOS7 radiation-hardened SOI technology. Discrete RadFETs have been irradiated under various radiation conditions and subjected to post-irradiation anneals. Data show only a small dose rate dependence and less than a 10% annealing or fade of the dosimeters output characteristics when irradiated with all pins shorted. These results show less fade than dual-dielectric RadFETs irradiated under the same bias conditions and support the use of SOI buried oxide RadFETs for low dose rate applications. Read-out circuitry has also been designed and fabricated to monitor changes in the ?off? state leakage current induced by radiation-induced charge buildup in the buried oxide dosimeter. The analog-to-digital output from the read-out circuit changes linearly with the ?off? state leakage current. Preliminary radiation characterizations of the read-out circuitry show no spurious effects of radiation-induced charge buildup in the read-out circuitry on the dosimeter output. These results indicate it is feasible to develop an embeddable SOI buried oxide RadFET as an attractive choice for many low power, low dose rate applications requiring real-time knowledge of total ionizing dose radiation levels.

Radiation Effects in MOS Oxides

Electronic devices in space environments can contain numerous types of oxides and insulators. Ionizing radiation can induce significant charge buildup in these oxides and insulators leading to device degradation and failure. Electrons and protons in space can lead to radiation-induced total-dose effects. The two primary types of radiation-induced charge are oxide-trapped charge and interface-trap charge. These charges can cause large radiation-induced threshold voltage shifts and increases in leakage currents. Two alternate dielectrics that have been investigated for replacing silicon dioxide are hafnium oxides and reoxidized nitrided oxides (RNO). For advanced technologies, which may employ alternate dielectrics, radiation-induced voltage shifts in these insulators may be negligible. Radiation-induced charge buildup in parasitic field oxides and in SOI buried oxides can also lead to device degradation and failure. Indeed, for advanced commercial technologies, the total-dose hardness of ICs is normally dominated by radiation-induced charge buildup in either parasitic field oxides and/or SOI buried oxides. Heavy ions in space can also degrade the oxides in electronic devices through several different mechanisms including single-event gate rupture, reduction in device lifetime, and large voltage shifts in power MOSFETs.

Radiation effects and hardening of MOS technology: devices and circuits

Total ionizing dose radiation effects on the electrical properties of metal-oxide-semiconductor devices and integrated circuits are complex in nature and have changed much during decades of device evolution. These effects are caused by radiation-induced charge buildup in oxide and interfacial regions. This paper presents an overview of these radiation-induced effects, their dependencies, and the many different approaches to their mitigation.

Correlation between Co-60 and X-ray radiation-induced charge buildup in silicon-on-insulator buried oxides

Large differences in charge buildup in SOI buried oxides are observed for X-ray and Co-60 irradiations of SIMOX and Unibond transistors. The Co-60 response is typically worse than the X-ray response. These results are consistent with expectations derived from previous work on the relative charge yield versus field in thick oxides. The effects of bias configuration and substrate type on charge buildup and hardness assurance issues are explored via experiments and simulation. The worst-case bias condition is found to be either the off-state or transmission gate configuration. Simulations of the buried oxide electric field in the various bias configurations are used to illustrate the factors that affect charge transport and trapping in the buried oxides. Hardness assurance implications are discussed.

Effects of reliability screens on MOS charge trapping

The effects of pre-irradiation elevated-temperature bias stresses on the radiation hardness of field-oxide transistors have been investigated as a function of stress temperature, time, and bias. Both the stress temperature and time are found to have a significant impact on radiation-induced charge buildup in these transistors. Specifically, an increase in either the stress temperature or time causes a much larger negative shift (towards depletion) in the I-V characteristics of the n-channel field-oxide transistors. This increased shift in the transistor I-V characteristics with stress temperature and time suggests that the mechanisms responsible for the stress effects are thermally activated. An activation energy of /spl sim/0.38 eV was measured. The stress bias was found to have no impact on radiation-induced charge buildup in these transistors. The observed stress temperature, time, and bias dependencies appears to be consistent with the diffusion of molecular hydrogen during a given stress period. These results have important implications for the development of hardness assurance test methods.

Comparison of 1/f noise in irradiated power MOSFETs measured in the linear and saturation regions

1/f noise in n-channel and p-channel power MOSFETs is investigated as a function of total dose and annealing. All the devices used in this study are nonhardened commercial parts. The preirradiation noise dependence on the gate and drain biases is analyzed. A different evolution of the noise measured in the linear and saturation regions through irradiation and annealing is reported. The build-up of interface traps was found to correlate well with the increase of noise during annealing for the p-channel devices. Measurements taken in the saturation region do not correlate as well with radiation-induced charge build-up, even though the overall noise increases slightly during irradiation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Numerical analysis of silicon-on-lnsulator short channel effects in a radiation environment

Radiation-induced charge build-up in the buried oxide (BOX) of SOI MOSFETs affects device performance through threshold voltage shifts of the back channel. This charge build-up is related to the electric field in the BOX during irradiation. In this paper, we report on the application of a numerical model for the potential distribution in a semiconductor device to the task of determining the electric field in the BOX. This electric field distribution is then combined with a model for charge accumulation as a function of electric field during irradiation to predict the threshold voltage shifts in the back channel of SOI MOSFET devices as a function of channel length. For the device design analyzed here, this model agrees with available experimental data and predicts an increase in back channel threshold shift as the channel length enters the sub-micron regime.

Charge Yield and Dose Effects in MOS Capacitors at 80 K

MOS devices, such as charge-coupled devices and MOSFET's, are being investigated for use in imaging, signal processing and detector preamplifier applications in which the detector and its immediately associated electronics are operated at low temperatures (less than or equal to 80 K). Recent experiments on MOS capacitors and devices at approximately 80 K have established that when hole-electron pairs are generated in the SiO/sub 2/ insulating layer by ionizing radiation the electrons are rapidly swept out of the oxide while the holes remain essentially immobile at or near their point of creation. As a result, the holes cause large flatband or threshold voltage shifts per unit dose in MOS structures. In contrast to the highly process-dependent ''permanent'' trapping of a small fraction of the radiation-generated holes observed at room temperature, the retention of the holes in SiO/sub 2/ at approximately 80 K is largely process-independent and is a consequence of a strongly temperature-dependent hole transport mechanism. The present paper discusses two related investigations of radiation-induced charge buildup in SiO/sub 2/ at approximately 80 K. In the first study, the retention of holes at low temperature is exploited to provide a direct measure of hole-electron pair yield per unit radiation dosemore » as a function of electric field for high-energy ionizing radiation. In the second study the response of MOS capacitors to short pulse high dose irradiation at approximately 80 K is investigated, and mechanisms which impose limits on the oxide charge buildup are examined.« less

Radiation Hardening of Thermal Oxides on Silicon via Ion Implantation

Implantation of thermal oxide on silicon with 1016 N2+ cm-2 at an energy of 50 keV reduces the space charge buildup observed in the oxide when exposed subsequently to ionizing radiation. The component of radiation-induced charge buildup in the oxide attributable to the increase in fast surface states at the oxide-silicon interface is largely unaffected.