Low Dose Rate Effects in Silicon-Based Devices and Integrated Circuits: A Review

Abstract

The total ionizing dose effects in silicon-based semiconductor devices (SDs) and integrated circuits (ICs) under conditions of low dose rate irradiation typical of space applications are surveyed. The mechanism of radiation-induced charge buildup in the dielectric of MOS structures and at the semiconductor/dielectric interface is considered. In addition, the nature of defects in the Si/SiO2 structure responsible for these processes is analyzed. The specific features of annealing the charge trapped in a dielectric during irradiation and also of interface traps (surface states, SSs) are shown. The peculiarities of the degradation of MOS and bipolar devices are considered for low dose rate irradiation conditions typical of space applications. It is shown that under low dose rate irradiation, MOS devices are prone to time-dependent effects which are determined by the kinetics of charge buildup and annealing in the Si/SiO2 structure, whereas bipolar devices may be susceptible to true dose rate effects. The main experimental methods of modeling low dose rate effects during accelerated tests of silicon devices and integrated circuits are surveyed. The necessity of using fundamentally different experimental approaches in modeling the time-dependent effects in MOS devices and the true dose rate effects in bipolar devices and integrated circuits is demonstrated.