LOW DOSE RATE EFFECTS IN SILICON BASED DEVICES AND INTEGRATED CIRCUITS: A REVIEW

Abstract

This paper is a review on total ionizing dose effects in silicon semiconductor devices and integrated circuits under low dose rate irradiation that is typical of space applications. We consider the mechanism of radiation induced charge buildup in the dielectric of MOS structures and at the semiconductor/dielectric interface; in addition, the paper reports an analysis of the nature of defects in Si/ SiO2 structure which are responsible for these processes. Also, the paper describes specific features of annealing of the charge trapped in dielectric and interface traps. The degradation of MOS and bipolar devices is considered for low dose rate irradiation conditions inherent to space application. We show that under low dose rate irradiation MOS devices are susceptible to time−dependent effects which are determined by the kinetics of charge buildup and annealing in the Si/SiO2 structure, while bipolar devices may be susceptible to true dose rate effects. The paper considers basic experimental modeling methods for low dose rate effects during accelerated testing of silicon devices and integrated circuits. We show that it is necessary to use essentially different experimental approaches for the modeling of time−dependent effects in MOS devices and true dose rate effects in bipolar devices and integrated circuits.