Radiation Hardened Memory Cell Research Articles

Radiation hardened 11T memory cell for space applications

Continuous nanometer technology scaling, along with rapid growth in the field of artificial intelligence (AI), internet-of-things (IoT), and other high-performance computing applications increases the need for low power and soft error immune VLSI circuits. Conventional radiation hardened bit cell such as QUATRO10T with partial single event upset (SEU) immunity and bit cells such as DICE12T, WE-QUATRO12T, and RHD13T needs large area and power consumption. To address these problems, a soft error immune radiation hardened memory cell 11T (RHMC11T) static random-access memory (SRAM) bit cell is proposed which is immune to both SEU and single event multiple node upsets (SEMNU) along with good read and write stability. The enhancement in the key parameters of the proposed cell is confirmed by comparing the proposed bit cell with the conventional bit cells such as 6T, NS10T, PS10T, QUATRO10T, RHMD10T, RHBD10T, 11T, and 12T. The critical charge of the proposed RHMC11T is improved by 43%, 27%, 19%, 2%, 2%, and 4% while comparing with 6T, NS10T, PS10T, QUATRO10T, RHBD10T, and 11T. The proposed bit cell has higher SVNM of 49%, 19%, 11%, 8%, and 5% and smaller WTV of 50%, 33%, 23%, 18%, and 21% compared to 6T, PS10T, RHMD10T, RHBD10T, and 12T respectively. The proposed RHMC11T has lesser read access time of 63%, 50%, 46%, 6%, and 6% compared to NS10T, PS10T, QUATRO10T, RHMD10T, and 11T. The proposed RHMC11T bit cell with dedicated write and read word lines makes it applicable for bit interleaving architecture and also it satisfies reliability requirements making it a good choice for highly radiative terrestrial environment applications such as in aerospace and satellites.

Design of High-Reliability Memory Cell to Mitigate Single Event Multiple Node Upsets

As technology scaling down, the sensitivity of SRAM cells to radiation-induced Single Event Upsets (SEUs) increases, and Single Event Multiple Node Upsets (SEMNUs) due to charge sharing has also become one of the major concerns in memory cell designs. In this paper, a high-reliability radiation hardened memory cell (RH-14T) is proposed to mitigate SEMNUs. SPICE simulations and 3D technology computer aided design mixed-mode simulations were performed to verify the high robustness of the RH-14T cell to SEUs. Compared with previous radiation hardened memory cells, the proposed RH-14T cell has similar read access time, smaller write access time, and the read access time and write access time are less sensitive to process variations. The Read Static Noise Margin (RSNM) and Write Margin (WM) of the RH-14T cell are larger than those of the unhardened conventional 6T SRAM cell. The improvement of reliability is often a trade-off with area, power consumption and performance. In order to achieve high reliability, the RH-14T cell employs more transistors, so it has 1.5 times the power consumption overhead of 6T and a larger area penalty.

Novel Low-Power and Highly Reliable Radiation Hardened Memory Cell for 65 nm CMOS Technology

In this paper, a novel low-power and highly reliable radiation hardened memory cell (RHM-12T) using 12 transistors is proposed to provide enough immunity against single event upset in TSMC 65 nm CMOS technology. The obtained results show that the proposed cell can not only tolerate upset at its any sensitive node regardless of upset polarity and strength, but also recover from multiple-node upset induced by charge sharing on the fixed nodes independent of the stored value. Moreover, the proposed cell has comparable or lower overheads in terms of static power, area and access time compared with previous radiation hardened memory cells.