Radiation-hardened Flip-flops Research Articles

Design of soft error correction flip-flop cells for highly reliable applications

With the development of technology, the vulnerability of integrated circuits to Single Event Effect (SEE) increases, and the sensitivity of flip-flops to soft errors induced by Single Event Transient (SET) and Single Event Upset (SEU) increases. Fault tolerant design is necessary for high reliability applications. In this work, a Soft Error Correction Flip-Flop 1(SEC FF1) is proposed, which can correct soft errors induced by SET and SEU at low clock phase without additional clock cycle. It has the lowest area and power consumption overhead and the lowest Power-Delay Product (PDP) compared with other radiation hardened flip-flops. In order to correct soft errors earlier, a variant of SEC FF1, SECFF2, is proposed at the cost of power consumption and switching delay. As the feature size of transistors shrinks, Double Node Upset (DNU) induced by single-event charge sharing is becoming an emerging reliability challenge. In order tolerate DNU, variant of SEC FFs, DNU Correction (DNUC) FFs, are proposed. In addition, the delay element used in the radiation-hardened flip-flops is also introduced.

A Highly Robust and Low-Power Flip-Flop Cell With Complete Double-Node-Upset Tolerance for Aerospace Applications

This paper proposes a highly robust and low power flip-flop cell with complete double-node-upset (DNU) tolerance for aerospace applications. The proposed cell is constructed from a master latch and a slave latch. The master latch comprises two C-elements as well as one clock-controlled C-element; the slave latch is similar to the master but has an extra keeper to avoid high-impedance state of the output-level C-element. Simulation results demonstrate that the proposed cell can provide complete DNU-tolerance and also demonstrate that the proposed cell can reduce power dissipation by roughly 65% on average when compared with existing radiation-hardened flip-flop cells.

Radiation-hardened flip-flop for single event upset tolerance

PurposeThe purpose of this paper is to present a transition detector (TD)-based radiation hardened flip-flop (TDRH-FF) for single event upset (SEU).Design/methodology/approachWith SEU recovery and single event transient (SET) detector mechanism, the TDRH-FF can tolerate SEU during hold mode and generate a warning signal for architecture-level recovery during transport mode when input signal contains SET. Evaluation results show that the TDRH-FF outperforms comparable comprehensive performance.FindingsSimulation results show that 1) the mean pulse width of the correction glitches (at full width half maximum) of TDRH-FF is less than 10 ps; 2) the area overhead of TDRH-FF is similar to the EVFERST-FF, BISER-FF and DNURHL-FF; 3) TDRH-FF has the same average power consumption as SETTOF, and moderate PDP and Ps values among these compared FFs.Originality/valueIn this paper, a TD-based TDRH-FF is proposed to solve the problems in the previous design. And the main contributions of the proposed TDRH-FF are summarized: Minimum size transistors are used in the proposed TD which leads to a considerable decrease in area overheads and propagation delay (resulting in an ignorable correction glitch); and compared with other radiation hardened flip-flop, TDRH-FF outperforms comparable comprehensive performance.

A Delay-Adjustable, Self-Testable Flip-Flop for Soft-Error Tolerability and Delay-Fault Testability

As the demand of safety-critical applications (e.g., automobile electronics) increases, various radiation-hardened flip-flops are proposed for enhancing design reliability. Among all flip-flops, Delay-Adjustable D-Flip-Flop (DAD-FF) is specialized in arbitrarily adjusting delay in the design to tolerate soft errors induced by different energy levels. However, due to a lack of testability on DAD-FF, its soft-error tolerability is not yet verified, leading to uncertain design reliability. Therefore, this work proposes Delay-Adjustable, Self-Testable Flip-Flop (DAST-FF), built on top of DAD-FF with two extra MUXs (one for scan test and the other for latching-delay verification) to achieve both soft-error tolerability and testability. Meanwhile, a built-in self-test method is also developed on DAST-FFs to verify the cumulative latching delay before operation. The experimental result shows that for a design with 8,802 DAST-FFs, the built-in self-test method only takes 946 ns to ensure the soft-error tolerability. As to the testability, the enhanced scan capability can be enabled by inserting one extra transmission gate into DAST-FF with only 4.5 area overhead.

New Power-efficient Flip-flop based on a True Single-phase Clock and Robust to Single-node Upsets

As the size of technology shrinks, its immunity to the space radiation environment decreases. A single-event transient (SET) induced by radiation can cause permanent damage to devices. Therefore, engineers have been researching radiation-hardened flip-flops or latches that are robust to soft errors. This paper proposes a true-single-phase-clock (TSPC)-based single-node-upset (SNU)-tolerant flip-flop, which is robust to SNUs and even faster than conventional DFFs. This flip-flop consists of two modules of TSPC flip-flops, except for inverters, and a Muller C-element. It has only 22 transistors, which makes it area-efficient. Moreover, the proposed flip-flop uses a TSPC; hence, the clock-to-Q delay is 10% less than the conventional DFF.

MSIFF: A radiation-hardened flip-flop via interleaving master-slave stage layout topology

MSIFF: A radiation-hardened flip-flop via interleaving master-slave stage layout topology

Radiation-Hardened Flip-Flops With Low-Delay Overhead Using pMOS Pass-Transistors to Suppress SET Pulses in a 65-nm FDSOI Process

In this paper, we propose radiation-hardened flip-flops (FFs) based on the adaptive coupling FF with low dynamic power and short delay overhead in a 65-nm fully depleted silicon on insulator process. We designed four FFs composed of a master latch with pMOS pass-transistors to reduce a delay time overhead and a slave latch with stacked transistors for high soft-error tolerance. We evaluated the radiation hardness of the newly designed FFs using TCAD simulations, $\alpha$ particle test, and neutron irradiation test. TCAD simulations show that the proposed structure has enough radiation hardness against secondary particles generated by neutrons. The $\alpha$ irradiation results show that error probabilities of the proposed FFs are 1/400–1/130 smaller than conventional radiation-hardened stacked FF. Neutron irradiation results show that soft-error rates of the proposed FFs are 1/16–1/7 lower than stacked FF. No significant differences in soft-error tolerance were observed in any of the proposed FFs under all static conditions. The experimental results suggest that the pMOS pass-transistors can effectively suppress soft errors in terrestrial regions with a low-delay overhead.

A Low-Power Radiation-Hardened Flip-Flop with Stacked Transistors in a 65 nm FDSOI Process

A Low-Power Radiation-Hardened Flip-Flop with Stacked Transistors in a 65 nm FDSOI Process

Design and Comparison of High-Reliable Radiation-Hardened Flip-Flops Under SMIC 40nm Process

With the need for fast and low-power radiation-hardened processors, advanced technology process is applied to obtain both high performance as well as high reliability. However, scaling down of the size of the transistor makes the transistor sensitive to outside disturbances, such as soft error introduced by the strikes of the cosmic neutron beams. Besides aerospace applications, such reliability should also be taken into consideration for the sub-100[Formula: see text]nm CMOS designs to ensure the robustness of the circuit. In such circumstances, several radiation-hardened flip-flops are designed and simulated under SMIC 40[Formula: see text]nm process. Simulation results show that with five aspects (performance, power, area, PVT variation and reliability) taken into consideration, TSPC-based DICE and TMR combined architecture has the best soft-error robustness in comparison with other radiation-hardened flip-flops, and the critical charge of such architecture is 490[Formula: see text]fC, which is 12.5X higher than the traditional unhardened flip-flop.

Analyzing and mitigating the internal single-event transient in radiation hardened flip-flops at circuit-level

Internal SET has become a great concern in normal radiation-hardened flip-flops with increases in frequency. We investigate the internal SET problem in the traditional hardened flip-flops in this article. We also propose a novel structure to eliminate the internal SET problem. Three-dimensional technology computer-aided design (TCAD) was adopted to verify the hardened performance of this proposed novel structure. Besides, the power and setup time were compared with the traditional hardened flip-flops.

A dual redundancy radiation-hardened flip—flop based on a C-element in a 65 nm process

A radiation-hardened flip—flop is proposed to mitigate the single event upset (SEU) effect. Immunity was achieved through the use of C-elements and redundant storage elements. It takes advantage of the property of a C-element in which it enters a high impedance mode when its inputs are of different logic values. Redundant storage nodes are then used to drive the C-elements so that a single upset pulse in any storage will be prevented from altering the state of the output of the flip—flop. The flip—flop was implemented using 48 transistors and occupied an area of 30.78 μm2, using 65 nm CMOS process. It consumed 22.6% fewer transistors as compared to the traditional SEU resilient TMR flip—flop.

Comparison of Dual-Rail and TMR Logic Cost Effectiveness and Suitability for FPGAs With Reconfigurable SEU Tolerance

We compare four circuit methods for single event (SE) mitigation: single string with radiation-hardened flip flops, delay-guarded logic, dual-rail logic, and triple modular redundancy (TMR). Test results of the circuit methods at 180 nm are presented. We then describe a novel reprogrammable FPGA architecture which can be configured based on SE mitigation and performance needs, and we evaluate the candidate SE mitigation methods as to suitability for such architecture.