Digital Signal Processing Research Articles

FPGA hardware kit for remote training platforms

This paper outlines the development of a Hardware Development Kit (HDK) for a remote training platform on FPGA Devices designed to provide university students pursuing degrees in electronic and informatics engineering (at the bachelor’s, master’s, and PhD levels) with the tools they need to learn and develop systems related to artificial intelligence, digital signal processing, image processing, digital systems, integrated and embedded systems using an FPGA chip. Through the internet or a local network, students can engage with the platform to conduct engineering experiments. The HDK is equipped with a Raspberry Pi, a screen, a camera, and LEDs to facilitate the transfer of experiment results and to aid in assessing the validity of lab experiment execution. The Raspberry Pi plays a crucial role in the HDK, providing control and monitoring, remote access, data processing, user interface, and integration with other possible systems.

Wavelet Cross-Correlation Signal Processing for Two-Phase Flow Control System in Oil Well Production

An algorithm based on continuous measurement of multiphase flows of oil well production has been designed to improve the efficiency of the technical control of oil production processes in the field. Separation-free, non-contact measurement of multiphase flows of oil well products allows increasing the efficiency of managing oil production processes in the field. Monitoring the current density using radioisotope measuring transducers (RMTs) allows obtaining information about the structure of the flow in the form of the distribution of gas inclusions and the speed of movement of liquid and gas in a two-phase flow. Fluid velocity measurement is based on digital processing of RMT signals, applying a continuous or discrete undecimated wavelet transform to them, and assessing the cross-correlation of wavelet coefficients in individual subspaces of the wavelet decomposition. The cross-correlation coefficients of two RMT signals located at a base distance, calculated in the subspaces of the wavelet decomposition, characterize the speed of movement of gas bubbles of different sizes in a vertical pipe. The measurement assumes that the velocity of the liquid phase of the oil flow in a vertical pipe mainly corresponds to the velocity of small bubbles. This speed should be determined by the maximum cross-correlation of wavelet coefficients in the corresponding decomposition subspace. Computer modeling made it possible to evaluate the characteristics of the algorithm for controlling the speed of liquid movement in the gas–liquid flow of oil well products and determine the mass flow rate of the liquid and the relative value of the gas content. The implementation of the algorithm in a multi-channel version of the device allows monitoring an entire cluster of wells in the field.

Hybrid PVP/Battery/Fuel Cell Wireless Charging Stations Using High-Frequency Optimized Inverter Technology for Electric Vehicles

The design and integration of intelligent energy management systems in hybrid electric vehicle (EV) charging stations, leveraging industry 4.0 and renewable energy sources, is crucial for advancing sustainability, efficiency, and technological development. The innovative hybrid EV charging station described in this study uses a combination of fuel cells, batteries, and solar panels that run at 14 amps a piece at 240 volts. The system consists of five essential components that work together to transfer power wirelessly: an EV battery bank, a boost converter, an HF inverter, transfer coils, and a power supply. Two crucial phases make up the optimization process. In phase 1, the boost converter’s maximum power point is tracked and optimized to generate the most power possible by varying the duty cycle between 10% and 90%. In phase 2, the HF uses a class ϕ2 inverter at 30 MHz to synchronize with the resonant frequency of wireless power transfer coils. Zero-voltage switching is used by a digital signal processor card to carry out control for effective operations. By utilizing hybrid sources to optimize power transmission, this design improves the sustainability of EV charging options.

Development of Digital Signal Processing Techniques with BPM

In order to ensure the continuity of operation of the VEPP-2000 collider, accurate measurement of the betatron frequency is necessary. To do this, this work proposes to use methods that refine the Fourier transform, such as parabola interpolation (Gassior method), NAFF and window functions. The refined frequency is subsequently used in construction of phase portraits of the beam to control the interference of high-order magnetic fields. In addition, the work discusses methods for extracting a signal from a mixture for subsequent analysis – PCA and ICA. Finally, to improve the accuracy of frequency determination, the paper considers the simplest implementation of a Kalman filter to improve the accuracy of subsequent harmonic analysis. In addition to all of the above, the paper briefly discusses a method for monitoring the operation of the beam position monitors themselves.

EDGE AI BASED OBJECT DETECTION SYSTEM USING TFLITE

Edge computing has gained prominence in recent years due to its ability to process data closer to the source, reducing latency and bandwidth requirements. In this paper, we propose an Edge AI Based Object Detection System using TensorFlow Lite (TFLite), designed to perform real-time object detection on resource-constrained edge devices. The system leverages the efficiency and portability of TFLite, a lightweight framework for deploying machine learning models on edge devices, to enable efficient inference without relying on cloud connectivity. Our proposed system integrates state-of-the-art object detection models, such as SSD (Single Shot Multibox Detector) and YOLO (You Only Look Once), into the TFLite runtime environment. Through optimization techniques such as model quantization, pruning, and architecture modifications, we tailor these models to meet the computational and memory constraints of edge devices while maintaining high detection accuracy. Furthermore, we explore hardware acceleration options, including GPU and DSP (Digital Signal Processor), to further enhance inference speed and energy efficiency. We evaluate the performance of the Edge AI Based Object Detection System on various edge devices, including smartphones, IoT (Internet of Things) devices, and embedded systems. Real-world deployment scenarios are considered, encompassing applications such as smart surveillance, industrial automation, and autonomous vehicles. The results demonstrate the system's ability to achieve real-time object detection with low latency and minimal resource consumption, making it well-suited for edge computing environments where real-time responsiveness and privacy are paramount concerns. Keywords: object Detection, Machine Learning, Tensor Flow lite, deep learning.

Design Efficient Vedic-Multiplier for Floating-Point MAC Module

Multiplication-accumulation (MAC) operation plays a crucial role in digital signal processing (DSP) applications, such as image convolution and filters, especially when performed on floating-point numbers to achieve high-level of accuracy. The performance of MAC module highly relies upon the performance of the multiplier utilized. This work offers a distinctive and efficient floating-point Vedic multiplier (VM) called adjusted-VM (AVM) to be utilized in MAC module to meet modern DSP demands. The proposed AVM is based on Urdhva-Tiryakbhyam-Sutra (UT-Sutra) approach and utilizes an enhanced design for the Brent-Kung carry-select adder (EBK-CSLA) to generate the final product. A (6*6)-bit AVM is designed first, then, it is extended to design (12*12)-bit AVM which in turns, utilized to design (24*24)-bit AVM. Moreover, the pipelining concept is used to optimize the speed of the offered (24*24)-bit AVM design. The proposed (24*24)-bit AVM can be used to achieve efficient multiplication for mantissa part in binary single-precision (BSP) floating-point MAC module. The proposed AVM architectures are modeled in VHDL, simulated, and synthesized by Xilinx-ISE14.7 tool using several FPGA families. The implementation results demonstrated a noticeable reduction in delay and area occupation by 33.16% and 42.42%, respectively compared with the most recent existing unpipelined design, and a reduction in delay of 44.78% compared with the existing pipelined design.

Specific Investigations Concerning the Improveable Multiplier Architecture of High-Speed and Area-Efficient Adders

Over the past few decades, the growth of portable devices such as laptops, mobile phone and personal digital assistant has resulted in increasing demand for complex functionality with effective computation. The present day technology is known for digital systems with very high computing capabilities. The demand for high speed, low power integrated circuits for portable devices has become crucial. The never ending growing complexities of integrated circuit for future devices pose a challenging task for integrated circuit designer. Cost effective integrated circuits requires the design meeting out the challenging task to optimize power, area with high performance. Hence this research focuses on the optimization of area, power and speed of Arithmetic circuits, Very Large Scale Integrated circuits (VLSI) are widely used in Arithmetic circuits, Digital Signal Processing (DSP), Image and Video Processing applications

W-band photonics-aided OFDM system integrating sensing and communication with phase noise suppression scheme

Photonic-aided technology offers many advantages in millimeter-wave (MMW) communication and sensing, such as low equipment cost and wide bandwidth. The combination of photonics-aided systems with orthogonal frequency division multiplexing (OFDM) waveforms enables high-performance integration of sensing and communication. In this paper, we propose and experimentally demonstrate a W-band photonic-aided OFDM system integrating sensing and communication (ISAC). To address the destruction of signal coherence by phase noise of the system, this paper proposes an OFDM sensing scheme combined with frequency-domain filtering to reduce the sidelobe interference caused by phase noise. Combined with offline digital signal processing algorithms, the system achieves high-precision ranging-Doppler imaging with a ranging resolution of 0.96 cm at a detection distance of 2 m. In terms of communication, after 10 m of wireless transmission, the net rate reaches 47.06 Gbit/s. The proposed system makes full use of the system's resources by using OFDM signals as both the sensing and communication signals. This may be beneficial for some potential applications of 6G in the future.

Automation of the process of testing on-board systems of unmanned aerial vehicles

The article describes the experience of applying the methodology of Model-Based Systems Engineering (MBSE) in the organization of ground tests of the on-board equipment complex of unmanned aerial vehicles at Kronshtadt JSC. This methodology was successfully used in the development of various complex control systems such as embedded control systems, digital signal processing, computer vision, radar and communications. The analysis of the on-board equipment testing process using an existing ground test bench was performed, and a method for automating its operation has been proposed. The calculation of economic efficiency was performed.

Implementation of Shunt Active Power Filter Using DSP Controller Based on Synchronous Reference Frame for Harmonic Mitigation

This research paper introduces the concept of a shunt active power filter (SAPF) that leverages synchronous-reference-frame (SRF) theory to mitigate harmonics in the power system. The SAPF works by injecting a compensating current at the point of common coupling (PCC) to counteract the harmonics in the line and restore sinusoidal current waveforms. It employs a three-phase current-controlled voltage source inverter (VSI) with a DC link capacitor for active filtering. An SRF algorithm is designed for a low-voltage laboratory prototype utilizing the TMS320F28335 Digital Signal Processor (DSP). The experimental findings affirm that the control strategy effectively aligns with the recommended harmonic standard limits of IEEE 519-1992.

Data-Driven Method for Robust Recovery in 1-Bit Compressive Sensing with the Minimax Concave Penalty

With the advent of large-scale data, the demand for information is increasing, which makes signal sampling technology and digital processing methods particularly important. The utilization of 1-bit compressive sensing in sparse recovery has garnered significant attention due to its cost-effectiveness in hardware implementation and storage. In this paper, we first leverage the minimax concave penalty equipped with the least squares to recover a high-dimensional true signal x∈Rp with k-sparse from n-dimensional 1-bit measurements and discuss the regularization by combing the nonconvex sparsity-inducing penalties. Moreover, we give an analysis of the complexity of the method with minimax concave penalty in certain conditions and derive the general theory for the model equipped with the family of sparsity-inducing nonconvex functions. Then, our approach employs a data-driven Newton-type method with stagewise steps to solve the proposed method. Numerical experiments on the synthesized and real data verify the competitiveness of the proposed method.

A high sensitivity digital giant magneto-impedance (GMI) sensor for magnetic communication

Abstract A high sensitivity Magneto-Impedance (GMI) sensor for magnetic communication systems in harsh environments is presented. In this system, the receiving coil of a conventional magnetic communication system is replaced by a high sensitivity GMI sensor and its digital electronic conditioning as well as digital signal processing. The whole architecture of the sensor is described in detail. It achieves two digital amplitude demodulations to recover, in real time, the binary sequence of the message sent by the transmitter. The demonstration and the validation of the reliable functioning of the system are illustrated through the transmission of messages using On-Off-Keying modulation method. The measured equivalent magnetic noise of the sensor was about noise 2 p T / Hz at 60 kHz, which is largely lower than the noise of other potential types of magnetic sensors such as Anisotropic Magneto-Resistive sensors for this application. This noise level suggests a potential higher communication range. When compared with an inductive coil, the developed sensor also presented an almost flat and sufficiently wide bandwidth compatible with magnetic communication. This bandwidth could potentially be extended according to the application.

Low complexity equalization in coherent optical communication based on Fermat number transform.

In order to reduce the power consumption of digital signal processing (DSP) in a coherent optical communication system, a low complexity equalization scheme in DSP flow of a 400 Gb/s DP-16QAM system has been proposed. This scheme is based on Fermat number transform (FNT), which sequentially performs static equalization (SE) and dynamic equalization (DE) in the transform domain. For different distances, the proposed scheme finds the optimal solution under the condition that transform length and data bit width are mutually restricted under different transmission distances while achieving low complexity and optimal performance. The experimental results show that the adopted transform-domain equalization (TrDE) scheme has much lower computational complexity than the traditional frequency-domain equalization (FDE) and time-domain equalization (TDE) nearly without any performance loss. In the 80, 160, and 240 km scenarios, the number of multiplier is reduced by more than 72%, and the advantage becomes more obvious as the transmission capacity increases.

Development and research of filter models communication and control systems configured for the required set of parameters

Problem statement. A digital filter refers to a hardware or software implementation of a mathematical algorithm that converts a digital signal in a certain way. The classification of digital filters is usually based on the functional characteristics of digital filtering algorithms. Digital filters may have parameters that cannot be implemented in analog filters, do not require periodic monitoring and calibration, and one filter can process several input channels or signals, while the accuracy is limited only by the bit depth used. The implementation of digital signal processing units using programmable logic integrated circuits (FPGAs) will significantly simplify hardware costs and make the most effective use of these digital filter capabilities. Goal. Conducting research in the field of digital signal processing in order to obtain fundamentally new software and hardware architectures, developing an RTL model of a complex functional block (SF block) of a digital signal processing system, its verification both at the logical and physical level. Results. In the course of the scientific research, a software and hardware model of the filter was developed to adjust the parameters during operation, taking into account their architectural advantages and disadvantages. In order to verify and confirm the adequacy of the methodology developed in the course of the study, an SF model was created-a digital signal processing unit. This model has been implemented and physically verified on the basis of a debugging board using FPGAs. Practical significance. The technique presented in this paper will allow the development of software and hardware devices for digital signal processing, with the possibility of their configuration at the software level for the required set of processing parameters, which in turn will significantly save resources spent on development.

Adaptive digital antenna array signal processing algorithm based on LDL decomposition

Two algorithms for inverting correlation matrices of digital antenna array signals are compared: LDL decomposition and the fringing method. The idea of comparing algorithms was to take into account the limitations on the length of the input data mantissa in the process of space-time processing using FPGAs. It has been found that rounding errors in the signal processing process in FPGAs can lead to the destruction of the directivity pattern. This is due to the fact that when implementing various algorithms for matrix inversion, the distribution of errors in the channels becomes interconnected. This means that when implementing adaptive antenna arrays on FPGAs, it is necessary to carefully choose the length of the mantissa and the conversion algorithm. In this regard, an algorithm for signal processing in an adaptive antenna array is proposed, its difference from the known ones is that when implemented on FPGAs, floating-point arithmetic of limited mantissa bit is used. When comparing two computationally efficient matrix inversion algorithms (the LDL method and the fringing method), the LDL method has higher stability. It was found that with an increase in the rank of the correlation matrix, the effect of rounding errors will be stronger. In this regard, it is necessary to determine in advance at what ratio of power sources and internal noise it is planned to use an adaptive processor.

EFFICIENT DSP-BASED REAL-TIME IMPLEMENTATION OF ANFIS REGULATOR FOR SINGLE-PHASE POWER FACTOR CORRECTOR

As a widely used technology, active power factor corrector (A-PFC) circuits face many control challenges, such as nonlinearity and uncertainties. With more and more power electrical appliances that are connected to the utility grid, the A-PFC is for the task of improving the power quality (PQ) to meet the requirement of the international standards, and this results in great challenges for keeping the total harmonic distortion (THD) as long as a power factor in the desired ranges. To this end, this paper focuses on the simulation and real-time implementation of a combined adaptive neural-fuzzy inference system (ANFIS) and predictive current controller for a single-phase PFC rectifier. The proposed control method has a simple, low-cost structure for better response and robustness. The performance of the proposed control approach was evaluated in real-time based on the dSPACE 1104 digital signal processor for different reference and load conditions. The results obtained from simulation and experimental tests validate the superiority of the proposed approach by evidencing a unity power factor, lower THD, fast dynamic response, and robustness against fast load and output voltage variations.

Sub-rate sampled, non-integer fractionally spaced Volterra nonlinear equalizer for IM/DD systems

As high-speed analog-to-digital converters (ADC) account for a significant portion of the receiver’s cost in intensity-modulation (IM)/direct-detection (DD) systems, there have been substantial efforts to employ an ADC operating at a relatively low sampling rate. However, half-symbol-spaced electronic nonlinear equalizers used to compensate for nonlinear waveform distortions commonly operate at 2 samples/symbols, and thus require digital upsampling before the equalization. This implies that the digital signal processing (DSP) at the receiver should also operate at 2 sample/symbol even though the ADC operates at the sub-rate (i.e., < 2 sample/symbol). Hence, we propose and experimentally demonstrate the sub-rate sampled, non-integer fractionally spaced Volterra nonlinear equalizer (VNLE). This equalizer does not require the digital upsampling, and thus makes the entire receiver DSP block operating at the sub-rate, the same as the sampling rate of ADC. We estimate the complexity of the proposed equalizer by the number of multipliers required for its implementation. We also evaluate the performance of the proposed VNLE over a 64-Gb/s 4-ary pulse amplitude modulation link and compare the performance with the conventional VNLE (requiring digital upsampling). The results show that the proposed VNLE incurs a very slight performance degradation compared with the conventional VNLE, but reduces the implementation complexity considerably since it obviates the need for digital upsampling at the receiver.

IQ-channel multiplexed DP-4ASK signal using power loading for downlink coherent PON system with access-span length difference

This study explores the integration of dual-polarized (DP) four-level amplitude shift keying (4ASK) signals within an intensity and quadrature division multiplexing framework, mainly focusing on coherent passive optical network (PON) systems. The primary objective is to address the challenges associated with distance disparities in downstream transmissions, which are prevalent in coherent PON architectures. We introduce a novel approach that significantly reduces the power consumption of digital-to-analog converters by implementing power loading strategies tailored explicitly for IQ channel division multiplexing (IQDM)-DP-4ASK signals. Our simulations confirm that ASK standard frequency offset compensation is adaptable to these signals, providing a robust method for managing frequency offsets in a dynamic network environment. Moreover, we propose and empirically validate an energy-efficient adaptive downlink solution capable of supporting 128 Gb/s per optical network unit (ONU), utilizing IQ-imbalanced DP-4ASK signals. This solution is particularly advantageous for systems where the transmission conditions include a 10 km variance in access span lengths between ONUs. Results from our experimental setup demonstrate that reducing the digital-to-analog converter output current for the Q channel by 137 mA is feasible without compromising signal integrity or system performance. Additionally, the research verifies the effectiveness of the automatic bias controller on the transmitter side, ensuring stable operation across varying conditions. Equally, the receiver-side digital signal processing effectively handles polarization separation, illustrating the system's capability to maintain high data integrity and reliability under diverse operational scenarios. These findings highlight the technical feasibility and operational benefits of using IQDM-DP-4ASK signals in coherent PON systems and underscore the potential for significant power savings and enhanced system efficiency in optical networks. The study paves the way for future research into scalable, energy-efficient solutions suitable for high-capacity optical access networks striving for increased sustainability and reduced operational costs.

Design and implementation of embedded hardware in furniture control based on DSP

The continuous progress of embedded technology and Internet of Things technology has accelerated the arrival of the era of home intelligence. By designing a smart home control system based on embedded DSP technology, it can detect temperature, humidity, flammable gas leakage, smoke, fire, and other indicators in the home environment, and carry out intelligent control of the detected security risks. The core of the system is the smart home management terminal, which is responsible for the network interconnection inside and outside the home. Terminal hardware includes a high-speed DSP chip, various interface modules, and so on. The software adopts the C/OS-II operating system to realize multi-task processing. This paper briefly summarizes DSP technology and embedded technology, and proposes the composition of intelligent home control system based on embedded DSP technology, as well as the hardware and software design and implementation of the system. Through the smart home system, users can control home conditions and obtain public service information anytime and anywhere, which is highly practical.

The specifics of the Galois field GF(257) and its use for digital signal processing

An algorithm of digital logarithm calculation for the Galois field GF(257)\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$GF(257)$$\\end{document} is proposed. It is shown that this field is coupled with one of the most important existing standards that uses a digital representation of the signal through 256 levels. It is shown that for this case it is advisable to use the specifics of quasi-Mersenne prime numbers, representable in the form p=2n+1\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$${p=2}^{n}+1$$\\end{document}, which includes the number 257. For fields GF(2n+1)\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$GF({2}^{n}+1)$$\\end{document}, an alternating encoding can be used, in which non-zero elements of the field are displayed through binary characters corresponding to the numbers + 1 and − 1. In such an encoding, multiplying a field element by 2 is reduced to a quasi-cyclic permutation of binary symbols (the permuted symbol changes sign). Proposed approach makes it possible to significantly simplify the design of computing devices for calculation of digital logarithm and multiplication of numbers modulo 257. A concrete scheme of a device for digital logarithm calculation in this field is presented. It is also shown that this circuit can be equipped with a universal adder modulo an arbitrary number, which makes it possible to implement any operations in the field under consideration. It is shown that proposed digital algorithm can also be used to reduce 256-valued logic operations to algebraic form. It is shown that the proposed approach is of significant interest for the development of UAV on-board computers operating as part of a group.