Racetrack Memory Research Articles

Current-Controllable and Reversible Multi-Resistance-State Based on Domain Wall Number Transition in 2D Ferromagnet Fe3GeTe2.

Controlling the multi-state switching is significantly essential for the extensive utilization of 2D ferromagnet in magnetic racetrack memories, topological devices, and neuromorphic computing devices. The development of all-electric functional nanodevices with multi-state switching and a rapid reset remains challenging. Herein, to imitate the potentiation and depression process of biological synapses, a full-current strategy is unprecedently established by the controllable resistance-state switching originating from the spin configuration rearrangement by domain wall number modulation in Fe3GeTe2. In particular, a strong correlation is uncovered in the reduction of domain wall number with the corresponding resistance decreasing by in-situ Lorentz transmission electron microscopy. Interestingly, the magnetic state is reversed instantly to the multi-domain wall state under a single pulse current with a higher amplitude, attributed to the rapid thermal demagnetization by simulation. Based on the neuromorphic computing system with full-current-driven artificial Fe3GeTe2 synapses with multi-state switching, a high accuracy of ≈91% is achieved in the handwriting image recognition pattern. The results identify 2D ferromagnet as an intriguing candidate for future advanced neuromorphic spintronics.

Dipolar skyrmions and antiskyrmions of arbitrary topological charge at room temperature.

Magnetic skyrmions are localized, stable topological magnetic textures that can move and interact with each other like ordinary particles when an external stimulus is applied. The efficient control of the motion of spin textures using spin-polarized currents opened an opportunity for skyrmionic devices such as racetrack memory and neuromorphic or reservoir computing. The coexistence of skyrmions with high topological charge in the same system promises further possibilities for efficient technological applications. In this work, we directly observe dipolar skyrmions and antiskyrmions with arbitrary topological charge in Co/Ni multilayers at room temperature. We explore the dipolar-stabilized spin objects with topological charges of up to 10 and characterize their nucleation process, their energy dependence on the topological charge and the effect of the material parameters on their stability. Furthermore, our micromagnetic simulations demonstrate spin-transfer-induced motion of these spin objects, which is important for their potential device application.

Roadmap for ferroelectric domain wall memory

Commercial nonvolatile Ferroelectric Random Access Memory employs a destructive readout scheme based on charge sensing, which limits its cell scalability in sizes above 100 nm. Ferroelectric domain walls are two-dimensional topological interfaces with thicknesses approaching the unit cell level between two antiparallel domains and exhibit electrical conductivity, distinguishing them from insulating matrices that are uniformly ordered. Recently, novel research has been devoted to utilizing this extraordinary interface for the application in nonvolatile memory with nanometer-sized scalability and low energy consumption. Here, we pay more attention to the development of the domain wall memory technologies in the future with challenges and opportunities to design planar and vertical arrays of the memory cells in the CMOS platform.

Antiferromagnetic interlayer exchange coupled Co68B32/Ir/Pt multilayers

Synthetic antiferromagnetic structures can exhibit the advantages of high velocity similarly to antiferromagnets with the additional benefit of being imaged and read-out through techniques applied to ferromagnets. Here, we explore the potential and limits of synthetic antiferromagnets to uncover ways to harness their valuable properties for applications. Two synthetic antiferromagnetic systems have been engineered and systematically investigated to provide an informed basis for creating devices with maximum potential for data storage, logic devices, and skyrmion racetrack memories. The two systems considered are (system 1) CoB/Ir/Pt of N repetitions with Ir inducing the negative coupling between the ferromagnetic layers and (system 2) two ferromagnetically coupled multilayers of CoB/Ir/Pt, coupled together antiferromagnetically with an Ir layer. From the hysteresis, it is found that system 1 shows stable antiferromagnetic interlayer exchange coupling between each magnetic layer up to N = 7. Using Kerr imaging, the two ferromagnetic multilayers in system 2 are shown to undergo separate maze-like switches during hysteresis. Both systems are also studied as a function of temperature and show different behaviors. Micromagnetic simulations predict that in both systems the skyrmion Hall angle is suppressed with the skyrmion velocity five times higher in system 1 than system 2.

Efficient Memory Layout for Pre-Alignment Filtering of Long DNA Reads Using Racetrack Memory

Efficient Memory Layout for Pre-Alignment Filtering of Long DNA Reads Using Racetrack Memory

Generation of skyrmions by combining thermal and spin-orbit torque: breaking half skyrmions into skyrmions.

Skyrmions, swirling spin textures with topologically protected stability and low critical driven-current density, can be generated from the stripe domain with current pulses, bringing them closer to practical applications in racetrack memory. However, the mechanism of this topological transition from the stripe domain to the skyrmion remains unclear because the transition process occurs at a nanosecond timescale, giving rise to difficulties in observing this process using imaging tools. In this study, we controlled the domain wall - skyrmion transition by combining Joule heating with spin-orbit torque (SOT) and experimentally observed the details of this process, by which we confirmed the mechanism: the spatial variation of the topological charge density induces half skyrmions branching from the stripe domains, and these half skyrmions overcome the surface tension and break away from the stripe domain, resulting in the generation of skyrmions. The details were observed by employing Joule heating to overcome the pinning effect and manipulating the strength of the SOT to induce the branching and breaking of half skyrmions. These findings offer new insights into skyrmion generation and serve as an important step towards the development of highly efficient devices for processing and computing based on skyrmionics.

Position error-free control of magnetic domain-wall devices via spin-orbit torque modulation

Magnetic domain-wall devices such as racetrack memory and domain-wall shift registers facilitate massive data storage as hard disk drives with low power portability as flash memory devices. The key issue to be addressed is how perfectly the domain-wall motion can be controlled without deformation, as it can replace the mechanical motion of hard disk drives. However, such domain-wall motion in real media is subject to the stochasticity of thermal agitation with quenched disorders, resulting in severe deformations with pinning and tilting. To sort out the problem, we propose and demonstrate a new concept of domain-wall control with a position error-free scheme. The primary idea involves spatial modulation of the spin-orbit torque along nanotrack devices, where the boundary of modulation possesses broken inversion symmetry. In this work, by showing the unidirectional motion of domain wall with position-error free manner, we provide an important missing piece in magnetic domain-wall device development.

Boosting domain wall velocity and stability in ferrimagnetic GdFe nanowires by applying laser-annealing process

This study highlights the significant achievement of enhancing domain wall (DW) velocity through the laser-annealing (LA) process in GdxFe100−x films, with a specific focus on the Gd26Fe74 composition. By investigating the current-induced DW motion, it was observed that the LA process on the edges and middle of the nanowires resulted in a remarkable improvement in DW velocity from around 600 m/s for non-laser-annealed to 1800 m/s for laser-annealed conditions. Furthermore, we conducted additional experiments to explore the stability and dynamics of a system involving DWs in a single wire. The experimental results revealed a stable and uniform movement of the DWs, as evidenced by a velocity of approximately 1800 m/s, even after the application of 20 pulses with a short pulse width of 1 ns. The resulting stability of the DW motion across a wide range of applied currents demonstrates the practical significance of the LA in achieving high-performance racetrack memories. Our findings suggest that the LA process has a similar effect on both the middle and edge treatments of the wire. This indicates that structural defects on the wire's edges are not the main cause of the observed low velocity or curvy shape of DWs. One possible mechanism for this effect is the reduction of the Ku value through the LA process. This study establishes a ground-breaking advancement by showcasing the effectiveness of the LA in enhancing DW motion velocity in GdFe ferrimagnetic thin films, thereby opening avenues for future research and industrial applications in this field.

Theory for anisotropic local ferroelectric switching

Theoretical modeling of polarization switching around a biased tip contact is important for fundamental understanding and advanced applications of ferroelectrics. Here we propose a simple in-plane two-dimensional model that considers surface charge transport and the associated evolution of the electric field driving domain growth. The model reproduces peculiar domain shapes ranging from round to faceted in KTiOPO4 (C2v symmetry) and LiNbO3 (C3v symmetry). This is done through modulation of dielectric permittivity, which mimics domain wall pinning on the lattice. In contrast to previous works, which attempted to justify domain anisotropy by means of point symmetry invariants, here we illustrate the necessity of taking translational symmetry into account. The results are pertinent to ferroelectric racetrack memories and other applications requiring domain tailoring.

Influence of Free Layer Surface Roughness on Magnetic and Electrical Properties of 300 mm CMOS-Compatible MTJ Stacks

The magnetic tunnel junction (MTJ) is a highly versatile device widely used in today’s spintronic applications such as magnetoresistive random-access memory (MRAM), magnetic sensors and prospectively as a read device in racetrack memory. Tuning the perpendicular (p-)MTJ stack to match the desired properties, such as tunnel magnetoresistance (TMR), magnetic anisotropies or coercive field of the free layer, requires careful optimization of the deposition parameters as well as precise layer thickness control. Here, the deposition of individual layers in a wedged manner across 300 mm wafers is proposed to engineer the thicknesses within the stack more efficiently. Furthermore, this technique provides detailed insights into effects related to surface roughness, magnetic anisotropy and TMR.

External Bias Field Control of Domain Wall to Skyrmion Conversion in a Typically Designed Magnetic Nanotrack

Understanding the evolution and tunable control of skyrmion dynamics is crucial for the effective development of next generation Racetrack Memory (RM) devices. In this study, we present the micromagnetic simulation demonstrating precise control of skyrmion motion in a magnetic nanotrack composed of two (three) narrow and a wider nanochannels under the influence of spin transfer torque (STT) and out of plane bias field. Our results reveal that out of plane magnetic field assists in efficient conversion of Domain wall (DW) pair to skyrmion and results in the achievement of uniform velocity for each skyrmion. Furthermore, a thorough analysis of individual and total energy terms during the DW pair to skyrmion conversion provides detailed insight into the role of bias field in overcoming the pinning potential at the junction of the narrow and wide nanochannel. The ability to precisely control the skyrmion motion stabilized from a DW pair under the influence of an external bias field is of significant importance for developing skyrmion based memory devices.

Hybrid Dry and Wet Etching of LiNbO3 Domain-Wall Memory Devices with 90° Etching Angles and Excellent Electrical Properties.

Ferroelectric domain walls, agile nanoscale interfaces of polar order, can be selectively controlled by electric fields for their position, conformation, and function, which is ultimately the key to realizing novel low-energy memory and computing structures. LiNbO3 single-crystal domain wall memory has the advantages of high operational speed, high integration density, and virtually unlimited endurance cycles, appearing as a good solution for the next generation of highly miniaturized low-energy memories. However, the etching process poses significant challenges in the nanofabrication and high-density integration of LiNbO3 domain-wall memories. Here, we employed a hybrid etching technique to achieve smooth sidewalls with a 90° inclined angle, leading to a 24% reduction in the coercive field and a 2.5-fold increase in the linear domain wall current density with a retention time of more than 106 seconds and endurance of over 105 writing cycles. Combined with the results of X-ray diffraction patterns and X-ray photoelectric spectra, it is concluded that the excellent electrical performance is related to the formation of an oxygen-deficient LiNbO3-x layer on the sidewall surface during the wet chemical etching process, which is a conductive layer that reduces the thickness of the "dead" layer between the side electrodes and the LiNbO3 cell and rectifies the diode-like wall currents with an onset voltage reduced from 1.23 to 0.28 V. These results prove the high-density integration of ferroelectric domain-wall memories at the nanoscale and provide a new strategy applicable to the development of LiNbO3 photonic devices.

Enhancing polarization retention in BiFeO3 domain wall nanodevices through controlled space charge redistribution

Ferroelectric thin films with binary switchable polarization offer promising applications in domain wall (DW) memory. However, achieving reliable polarization retention in size-reduced devices remains challenging. In this study, we present a planar ferroelectric BiFeO3 DW nanodevice demonstrating stable polarization retention through electrical cycling. By precisely controlling the device size, including the width and gap of planar Pt electrodes, we observed a back-switching process in switched polarization within 20 min, as characterized by ex-situ piezoresponse force microscopy (PFM). To overcome this issue, long-time alternating voltage pulse cycling effectively suppressed the back-switching behavior, leading to symmetrized polarization coercive voltages of the device. PFM characterization further confirmed the persistence of the artificially created DW between the electrode pair. This improved polarization retention was attributed to the migration of mobile charged defects, such as oxygen vacancies, at the domain boundary. The presence of these defects generated a local built-in field, which screened the net polarization induced by the charged DW. Upon erasing the DW, the local built-in field gradually dissipated during opposite voltage poling, resulting in restored poor polarization retention and asymmetric coercive voltage in the nanodevices. This work presents a promising approach to utilize defect redistribution for stabilizing the switched polarization in the development of high-density ferroelectric DW memory.

All-Electrical 9-Bit Skyrmion-Based Racetrack Memory Designed with Laser Irradiation.

Racetrack memories with magnetic skyrmions have recently been proposed as a promising storage technology. To be appealing, several challenges must still be faced for the deterministic generation of skyrmions, their high-fidelity transfer, and accurate reading. Here, we realize the first proof-of-concept of a 9-bit skyrmion racetrack memory with all-electrical controllable functionalities implemented in the same device. The key ingredient is the generation of a tailored nonuniform distribution of magnetic anisotropy via laser irradiation in order to (i) create a well-defined skyrmion nucleation center, (ii) define the memory cells hosting the information coded as the presence/absence of skyrmions, and (iii) improve the signal-to-noise ratio of anomalous Hall resistance measurements. This work introduces a strategy to unify previous findings and predictions for the development of a generation of racetrack memories with robust control of skyrmion nucleation and position, as well as effective skyrmion electrical detection.

Insdel codes from subspace and rank-metric codes

Insertion and deletion (insdel in short) codes are designed to deal with synchronization errors in communication channels caused by insertions and deletions of message symbols. These codes have received a lot of attention due to their applications in diverse areas such as computational biology, DNA data storage, race-track memory error corrections, language processing, and synchronous digital communication networks. In the present work, we study constructions and limitations of insdel codes from rank metric and subspace codes. This paper studies and improves the idea of the work [4] by Hao Chen on the connection between insdel codes and subspace codes.We discuss why subspace code is a natural choice for constructing insdel codes and show that the interleaved Gabidulin codes can be used to construct nonlinear insdel codes approaching the Singleton bound. Then we show that the indexing scheme of transforming efficient Hamming metric codes to efficient insdel codes can be adapted for the class of rank metric codes. And that improves the base field size of the construction of insdel codes from lifted rank-metric codes. It is also shown that the size of the insdel code from a subspace code can be improved significantly than in the previously proposed construction. We give an algebraic condition for a linear Gabidulin rank metric code to be optimal insdel code adapting the condition proved for Reed-Solomon codes. Moreover, we give constructions of linear and nonlinear insdel codes from Sidon spaces.

Dynamics of skyrmion bags driven by spin wave

Skyrmion bags are spin textures with arbitrary integer topological charge numbers, holding promise for utilization in high-density racetrack memory devices. In this study, we investigate the dynamics of skyrmion bags driven by propagating spin waves in a magnetic nanostrip, employing micromagnetic simulations. Our findings reveal that propagating spin waves can induce a stable movement of skyrmion bags, irrespective of their topological charge numbers. The amplitude and frequency of the spin wave, alongside material parameters such as damping constant and saturation magnetization, exhibit discernible effects on the behavior of skyrmion bags. These outcomes have the potential to advance the development of racetrack memory based on skyrmion bags.

Dynamics of magnetic skyrmionium driven by voltage-controlled strain gradients

A magnetic skyrmionium with zero topological number has no skyrmion Hall effect during motion; hence, it has excellent application prospects in racetrack memory. Here, we investigate dynamics of magnetic skyrmionium driven by voltage-controlled in-plane strain gradients via both electromechanical and micromagnetic simulations. It is found that the skyrmionium can be efficiently driven along the direction of the in-plane strain gradients without deflection, that is, the skyrmion Hall angle is zero, and the velocity of skyrmionium can be effectively increased by reducing the magnetic damping constant and increasing the intensity of the strain gradient. Moreover, the driving force and velocity of the skyrmionium increase correspondingly with the increase in size. Most importantly, we demonstrate that the skyrmionium can be efficiently driven by strain gradients under realistic conditions with thermal noise and material inhomogeneity in the ferromagnetic film. The results presented in this study are promising for applications in skyrmionium-based information memory devices.

Oxygen vacancy-mediated enhancement of ferroelectric domain wall memory performance at elevated temperatures

The demand for reliable memory devices capable of operating in harsh environments, such as space and vehicles, necessitates the development of high-temperature-resistant technologies. In this study, we propose a novel ferroelectric domain wall (DW) memory utilizing BiFeO3 thin films, which exhibit exceptional retention and fatigue properties at 135 °C. Achieving this performance was made possible through precise control of the oxygen vacancy density in the epitaxial thin films induced by a post-annealing procedure conducted under an appropriate oxygen pressure of 10 Pa. Initially, prototype nano-memory devices lacking post-annealing treatment demonstrated resistive switching behavior at room temperature, with a current rectification ratio of 100:1, achieved by manipulating the uncompensated DW induced by polarization switching. With the additional annealing procedure in lower oxygen pressure, the wall current magnitude of the devices increased significantly, indicating the critical role of the oxygen vacancies in modulating the DW conductivity. Moreover, the nanodevices exhibited improved polarization retention due to oxygen vacancy-mediated charge injection that can be further enhanced at the elevated temperature. The electrons trapped deeply at the artificial DW were found to stabilize the switched polarization at the expense of reduced DW conductivity, emphasizing the importance of precise control over oxygen vacancy density for achieving a balance between high DW conductivity and excellent polarization retention.

DownShift: Tuning Shift Reduction With Reliability for Racetrack Memories

Ultra-dense non-volatile <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">racetrack memories</i> (RTMs) have been investigated at various levels in the memory hierarchy for improved performance and reduced energy consumption. However, the innate <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">shift</i> operations in RTMs, required for data access, incur performance penalties and can induce position errors. These factors can hinder their applicability in replacing low-latency, reliable on-chip memories. Intelligent placement of memory objects in RTMs can significantly reduce the number of shifts per memory access with little to no hardware overhead. However, existing placement strategies may lead to sub-optimal performance when applied to different architectures. Additionally, the impact of these shift optimization techniques on RTM reliability has been insufficiently investigated. We propose DownShift, a generalized data placement mechanism that improves upon prior approaches by taking into account (1) the timing and liveliness information of memory objects and (2) the underlying memory architecture, including required shifting fault tolerance. Thus, we also propose a collaboratively designed new shift alignment reliability technique called GROGU. GROGU leverages the reduced shift window made possible through DownShift allowing improved reliability, area, and energy compared to the state-of-the-art reliability approaches. DownShift reduces the number of shifts, runtime, and energy consumption by 3.24×, 47.6%, and 70.8% compared to the state-of-the-art. GROGU consumes 2.2× less area and 1.3× less energy while providing 16.8× improvement in shift fault tolerance compared to the leading reliability approach for a latency degradation of only 3.2%.

Correcting Multiple Deletions and Insertions in Racetrack Memory

Racetrack memory is a tape-like structure where data is stored sequentially as a track of single-bit memory cells. The cells are accessed through read/write ports, called heads. When reading/writing the data, the heads stay fixed and the track is shifting. One of the main challenges in developing racetrack memory systems is the limited precision in controlling the track shifts, that in turn affects the reliability of reading and writing the data. A current proposal for combating deletions in racetrack memories is to use redundant heads per-track resulting in multiple copies (potentially erroneous) and recovering the data by solving a specialized version of a sequence reconstruction problem. Using this approach, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> -deletion correcting codes of length <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> , with <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</i> ≥ 2 heads per-track, with redundancy log log <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> + 4 were constructed. However, the known approach requires that <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> ≤ <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</i> , namely, that the number of heads <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</i> is larger than or equal to the number of correctable deletions <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> . Here we address the question: What is the asymptotically optimal order of redundancy that can be achieved for a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> -deletion code ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> is a constant) if the number of heads is fixed at <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</i> (due to implementation constraints)? One of our key results is an answer to this question, namely, we construct codes that can correct <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> deletions, for any <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> beyond the known limit of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</i> . The codes have asymptotically 8 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> log log <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> + <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</i> (log log <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> ) redundancy for <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</i> ≤ <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> ≤ 2 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</i> – 1. In addition, when <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> ≥ 2 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</i> , our codes have asymptotically 2 ⌊ <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k/d</i> ⌋ log <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> + <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</i> (log <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> ) redundancy, that we prove it is order-wise optimal, specifically, we prove that the redundancy required for correcting <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> deletions is at least ⌊ <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> /2 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</i> ⌋ log <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> + <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</i> (log <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> ). The encoding/decoding complexity of our codes is <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</i> ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> log <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2<i>k</i>+1</sup> <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> ). Finally, we ask a general question: What is the order-wise optimal redundancy for codes correcting a combination of at most <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> deletions and insertions in a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</i> -head racetrack memory? We prove that the redundancy used for a combination of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> deletion and insertion errors is asymptotically the same as that needed in the case of k deletion errors.