Quotient Digit Research Articles

Constructing High Radix Quotient Digit Selection Tables for SRT Division and Square Root

High radix SRT division plays an important role in contemporary microprocessors as the quotient digit selection tables effectively reduce the computation complexity of the quotient digits. The quotient digit selection table is constructed according to the rounded lower and upper bounds of the overlapping regions in the traditional method. The table construction process lacks in mathematical rigor and consequently is susceptible to error. This paper proposes an algebraic method for computing the quotient digit selection tables. We characterize the quotient digit selection functions to construct quotient digit selection tables required for SRT division and SRT square root with any valid redundancy. The functions include the maximum and minimum legal quotient digit selections. We compute the truncations of the remainder <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$p$</tex-math></inline-formula> and divisor <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$d$</tex-math></inline-formula> when <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$d \in [1,2)$</tex-math></inline-formula> . We implement procedures to compute quotient digit selection tables by our functions. The computation of the quotient digit selection table for the case radix-4 with the quotient digit set <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$[-2,2]$</tex-math></inline-formula> is presented by using the minimum quotient digit selection function. Our functions can compute quotient digit selection tables in the design phase of SRT division and square root by given radix and redundancy.

An Architecture of Area-Effective High Radix Floating-Point Divider With Low-Power Consumption

In this paper, a novel architecture of area-effective high-radix floating-point divider with low power consumption is proposed. By extending the principle of the standard SRT algorithm, the divider can estimate the partial quotient digits by a simpler circuit and tolerate certain calculation errors in each recurrence cycle. In addition, the accumulation of errors in the recurrence process can be eliminated automatically without additional calculation cycle. The latency and area cost of the divider are linear with the radix number, which solves the problem that the quotient digits selection tables in high-radix divider have high area cost. Base on the proposed architecture a single-precision floating-point divider is implemented, which has an area of 6037.20 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu {\mathrm{ m}}^{2}$ </tex-math></inline-formula> in 65nm process. The dynamic power consumption of the divider is only 0.848mW at 250MHz. Compared with other dividers reported in the literature, the area cost can be reduced by about 90% with the same computation precision and performance.

Design of Unsigned Approximate Hybrid Dividers Based on Restoring Array and Logarithmic Dividers

Approximate computer arithmetic has been extensively studied due to its advantages to further reduce power consumption and increase performance at reduced accuracy. Although a number of approximate adders and multipliers have been studied, only a few approximate dividers have been proposed. A logarithmic divider (LD) has low complexity and accuracy, while an exact array divider (EXD) has a high complexity. Therefore, in this article, an approximate hybrid divider (AXHD) is proposed. It takes advantage of both LD and EXD to achieve a tradeoff between hardware performance and accuracy. Exact restoring divider cells are used to generate the most significant bits (MSBs) of the quotient for attaining a high accuracy while the other quotient digits are generated by using a LD as an approximate scheme to improve figures of merit such as power consumption, area and delay. To further save hardware resources, a so-called eliminated approximate hybrid divider (E-AXHD) based on AXHD is also proposed. In this improved design, a reduced width divider is used to replace the EXD in AXHD. Specifically, for a 16-by-8 design, <inline-formula><tex-math notation="LaTeX">$n/(n+1)$</tex-math></inline-formula> array division is used to replace the <inline-formula><tex-math notation="LaTeX">$n/8$</tex-math></inline-formula> array division <inline-formula><tex-math notation="LaTeX">$(n&lt;8)$</tex-math></inline-formula> . The proposed AXHD and E-AXHD are evaluated and analyzed using error and hardware metrics. The proposed designs are also compared with EXD, LD and previous approximate dividers. The results show that the proposed designs outperform previous approximate dividers by considering both energy and error. The proposed hybrid dividers are of particular interest for error tolerant applications such as image processing and machine learning.

Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems

VLSI realizations of digit-recurrence binary division usually use redundant representation of partial remainders and quotient digits. The former allows for fast carry-free computation of the next partial remainder, and the latter leads to less number of the required divisor multiples. In studying the previous relevant works, we have noted that the binary carry-save (CS) number system is prevalent in the representation of partial remainders, and redundant high radix representation of quotient digits is popular in order to reduce the cycle count. In this paper, we explore a design space containing four division architectures. These are based on binary CS or radix-16 signed digit (SD) representations of partial remainders. On the other hand, they use full or partial precomputation of divisor multiples. The latter uses smaller multiplexer at the cost two extra adders, where one of the operands is constant within all cycles. The quotient digits are represented by radix-16 [−9, 9] SDs. Our synthesis-based evaluation of VLSI realizations of the best previous relevant work and the four proposed designs show reduced power and energy figures in the proposed designs at the cost of more silicon area and delay measures. However, our energy-delay product is 26%–35% less than that of the reference work.

An Efficient Radix-4 Scalable Architecture for Montgomery Modular Multiplication

To achieve low latency, existing radix-4 scalable architectures for word-based Montgomery modular multiplication usually suffer from high design and hardware complexities. This brief presents a simple compression scheme and circuit to remove the data dependence in the accumulation process and accomplish one-cycle latency without quotient pipeline. The complex computation and encoding of quotient digits are thus avoided, leading to up to 10.6% and 17.7% reductions in area and power than previous work while maintaining very high performance. Consequently, the proposed radix-4 scalable architecture appears to be very suited for low-complexity and low-power cryptographic applications.

Radix-2 Division Algorithms with an Over-Redundant Digit Set

This paper presents a derivation of four radix-2 division algorithms by digit recurrence. Each division algorithm selects a quotient digit from the over-redundant digit set {−2, −1, 0, 1, 2}, and the selection of each quotient digit depends only on the two most-significant digits of the partial remainder in a redundant representation. Two algorithms use a two’s complement representation for the partial remainder and carry-save additions, and the other two algorithms use a binary signed-digit representation for the partial remainder and carry-free additions. Three algorithms are novel. The fourth algorithm has been presented before. Results from the synthesized netlists show that two of our fastest algorithms achieve an improvement of 10 percent in latency per iteration over a standard radix-2 SRT algorithm at the cost of 36 percent more power and 50 percent more area.

Decimal Division Algorithms: The Issue of Partial Remainders

The efficiency of decimal digit-recurrence division algorithms is totally affected by the number representations of the quotient, the divisor and partial remainders participated in quotient digit selection (QDS). This paper establishes general rules and conditions for QDS with operands represented in the generalized signed-digit format. As a result of this generalization, a universal convergence condition is introduced which obviates the unnecessary conservatism of previous algorithms and hence paves the way for more correct and efficient decimal division hardware designs. It is also concluded that keeping the partial remainders in minimally redundant symmetric signed-digit representation (with digit-set [?5,6])and applying into QDS the divisor represented in minimally asymmetric non-redundant signed-digit format (with digit-set [?4,5]) lead to the smallest minimum precision required, of the divisor and the partial remainder, for QDS and thus faster and simpler division algorithm. Moreover, it is shown that even in case of using non-redundant partial remainders (for the sake of lower area cost); minimally asymmetric signed-digit representation brings about more efficiency. The suggested representations are applied to the fastest previous decimal digit-recurrence divider and 10 % speed-up is achieved while keeping the area cost approximately unaltered.

Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs

Decimal floating point operations are important for applications that cannot tolerate errors from conversions between binary and decimal formats, for instance, commercial, financial, and insurance applications. In this paper we present five different radix-10 digit recurrence dividers for FPGA architectures. The first one implements a simple restoring shift-and-subtract algorithm, whereas each of the other four implementations performs a nonrestoring digit recurrence algorithm with signed-digit redundant quotient calculation and carry-save representation of the residuals. More precisely, the quotient digit selection function of the second divider is implemented fully by means of a ROM, the quotient digit selection function of the third and fourth dividers are based on carry-propagate adders, and the fifth divider decomposes each digit into three components and requires neither a ROM nor a multiplexer. Furthermore, the fixed-point divider is extended to support IEEE 754-2008 compliant decimal floating-point division for decimal64 data format. Finally, the algorithms have been synthesized on a Xilinx Virtex-5 FPGA, and implementation results are given.

Computation and Formal Verification of SRT Quotient and Square Root Digit Selection Tables

Computation and Formal Verification of SRT Quotient and Square Root Digit Selection Tables

Improving the speed of decimal division

The authors study previous major contributions to digit recurrence decimal division hardware and focus on techniques for improving the performance of quotient digit selection (QDS) as the most complex part. In particular, Design D1 uses the digit set [-5, 5] for quotient digits. Another design (D2) uses mixed binary/decimal carry-save manipulation of the few most significant digits of partial remainders. Motivated by successful combined arithmetic algorithms such as hybrid adders, the authors offer a decimal division scheme that takes advantage of the best design options of D1 and D2 with due modifications that significantly enhance the division speed. In particular, they configure the architectures of QDS and partial remainder computation paths in favour of reduced balanced latencies of both. Furthermore, they remove the rounding cycle by cost-free auto-rounding, which is an exclusive advantage of the digit set [-5, 5]. The authors of D1 and D2 have used logical effort (LE) and circuit synthesis to evaluate their dividers, respectively. Therefore for a fair comparison, the authors evaluate the proposed design (D3) with both methods. The LE-based D3/D1 comparison shows 21- more speed at the cost of 6- more area, whereas the synthesis-based D3/D2 comparison results in 46- less latency and 23- less area.

High-Radix Multiplier-Dividers: Theory, Design, and Hardware

This paper describes the theory and design of digital high-radix multiplier-dividers (Patent Pending). The theory of high-radix division is extended to high-radix multiplier-dividers that can perform fused multiplication and division operations using a single recurrence relation. With the fused implementation of multiplication and division, the two operations can be executed using a single instruction, implying only a single rounding operation. The recurrence relation is described, the quotient digit selection function derived, and important design parameters together with their optimal values and relations are defined. Efficient design procedure and implementation hardware are described and important system parameter values for various radix systems computed. Compared to pure dividers, the multiplier-divider requires a slightly more complex data path and quotient digit selection function.

A novel implementation of radix-4 floating-point division/square-root using comparison multiples

A new implementation for minimally redundant radix-4 floating-point SRT div/sqrt (division/square-root) with the recurrence in the signed-digit format is introduced. The implementation is developed based on the comparison multiples idea. In the proposed approach, the magnitude of the quotient (root) digit is calculated by comparing the truncated partial remainder with 2 limited precision multiples of the divisor (partial root). The digit sign is determined by investigating the polarity of the truncated partial remainder. A timing evaluation using the logical synthesis (Synopsys DC with Artisan 0.18 μm typical library) shows a latency of 2.5 ns for the recurrence of the proposed div/sqrt. This is less than of the conventional implementation.

Higher Radix and Redundancy Factor for Floating Point SRT Division

The execution performances of the Sweeney, Robertson, Tocher (SRT) division algorithm depend on two parameters: the radix-r and the redundancy factor p. In this paper, a study of the effect of these parameters on the division performances is presented. At each iteration, the SRT algorithm performs a multiplication by the quotient digit qi+1. This last can be just a simple shift, if the digit qi i +1is a power of two (qi+1 = 2k), otherwise, the SRT iteration needs a multiplier. We propose, in this work, an approach to circumvent this multiplication by decomposing the quotient digit qi+1 into two or three terms multiples of 2. Then, the multiplication is carried out by simple shifts and a carry save addition. The implementation of this approach on Virtex-II field-programmable gate-array (FPGA) circuits gives best performances than the approach which uses the embedded multipliers 18times18 bits. The iterations delays are operands sizes independent. The reduction tree delays are at most equivalent to the delay of two Virtex-II slices. This approach was tested for the 4, 8, and 16 radixes in the two cases of minimum and maximum redundancy factors. By this study, we conclude that the use of the radix-8 with a maximum redundancy factor gives the best performances by using our approach for the double precision computation of the SRT division.

A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture

In this work, we present a radix-10 division unit that is based on the digit-recurrence algorithm. The previous decimal division designs do not include recent developments in the theory and practice of this type of algorithm, which were developed for radix-2k dividers. In addition to the adaptation of these features, the radix-10 quotient digit is decomposed into a radix-2 digit and a radix-5 digit in such a way that only five and two times the divisor are required in the recurrence. Moreover, the most significant slice of the recurrence, which includes the selection function, is implemented in radix-2, avoiding the additional delay introduced by the radix-10 carry-save additions and allowing the balancing of the paths to reduce the cycle delay. The results of the implementation of the proposed radix-10 division unit show that its latency is close to that of radix-16 division units (comparable dynamic range of significant) and it has a shorter latency than a radix-10 unit based on the Newton-Raphson approximation

High-performance two's complement divider

This paper presents a novel area-efficient two's complement high radix divider without affecting the high speed of the radix- 2 k structure. In the proposed approach, only the odd values (rather than all the 2 k values) of the quotient digit set are used to generate the multiples of divisor. Moreover, the set of ( N + k + 1 ) -bit additions are replaced with a set of few most significant bits ( k + 2 bits) additions followed by two ( N + 3 ) -bit additions only. The new radix- 2 k structure has been evaluated for different values of k. It is shown that the silicon area required by the new design could be as low as 15% of that of the conventional two's complement radix- 2 k architecture for radix-64 (20% for radix-32) while the speed is nearly the same. Despite that the proposed algorithm is originally developed in order to improve the performance of the two's complement approach, it has also been compared with the redundant SRT algorithm. The area–time ratios of the new radix-16 and radix-32 dividers to that of the SRT divider are equal to 85% and 77%, respectively.

A Fast Radix-4 Floating-Point Divider with Quotient Digit Selection by Comparison Multiples

A new implementation for minimally redundant radix-4 SRT division with the recurrence in the signed-digit format is introduced. The implementation is developed based on the comparison multiples idea. In the proposed approach, the quotient digit's magnitude is calculated by comparing the truncated partial remainder with two limited precision multiples of the divisor. The sign is determined by investigating the polarity of the truncated partial remainder. A timing evaluation using logical synthesis shows a latency of 2.34 ns for the recurrence of the proposed divider. It is ∼22% less than the conventional implementation.

Fast Decimal Floating-Point Division

A new implementation for decimal floating-point (DFP) division is introduced. The algorithm is based on high-radix SRT division The SRT division algorithm is named after D. Sweeney, J. E. Robertson, and T. D. Tocher. with the recurrence in a new decimal signed-digit format. Quotient digits are selected using comparison multiples, where the magnitude of the quotient digit is calculated by comparing the truncated partial remainder with limited precision multiples of the divisor. The sign is determined concurrently by investigating the polarity of the truncated partial remainder. A timing evaluation using a logic synthesis shows a significant decrease in the division execution time in contrast with one of the fastest DFP dividers reported in the open literature

Digit-recurrence dividers with reduced logical depth

In this paper, we propose a class of division algorithms with the aim of reducing the delay of the selection of the quotient digit by introducing more concurrency and flexibility in its computation. From the proposed class of algorithms, we select one that moves part of the selection function out of the critical path, with a corresponding reduction in the critical path compared with existing alternatives: we present the algorithm and describe the architectures for radix 4 and for radix 16. For radix 16, we use the scheme of overlapping two radix-4 stages. In both cases, radix 4 and radix 16, we show that our algorithms allow the design of units with well-balanced critical paths with consequent decreases of the cycle times. Moreover, in the radix-16 case, we include some additional speculation techniques. To estimate the speedup, we used a rough timing model based on logical effort. For both radices, we estimate a speedup of about 25 percent with respect to previous implementations. In the radix-4 case, this is achieved by using roughly the same area, while, in the radix-16 case, the area is increased by about 30 percent. We verified our estimations by performing a synthesis of the radix-4 units.

Digit selection for SRT division and square root

The quotient digit selection in the SRT division algorithm is based on a few most significant bits of the remainder and divisor, where the remainder is usually represented in a redundant representation. The number of leading bits needed depends on the quotient radix and digit set, and is usually found by an extensive search, to assure that the next quotient digit can be chosen as valid for all points (remainder, divisor) in a set defined by the truncated remainder and divisor, i.e., an uncertainty rectangle. This work presents expressions for the number of bits needed from the truncated remainder and divisor (the truncation parameters), thus eliminating the need for a search through the truncation parameter space for validation. The analysis is then extended to the digit selection in SRT square root algorithms, where it is shown that, in general, it may be necessary to increase the number of leading bits needed for digit determination in a combined divide and square root algorithm. An easy condition to check the number of bits needed is established, also checking the number of initial digits of the root may have to be found by other means, e.g., by table look-up. The minimally redundant, radix-4 combined divide and square root algorithm is finally analyzed and it is shown that, in this case, it can be implemented without such a special table to determine initial digits for the square root.

Area-efficient nonrestoring radix- division

This paper presents an area-efficient twos complement high radix division algorithm and its architecture. The advantage of using high radix division is to generate more quotient bits per iteration while binary division results in one bit per iteration. In the conventional restoring radix-2^k division, the selection of the quotient digit requires the use of all the multiples of the divisor. As a result, the area increases exponentially (area of radix 2^k divider is about 2^k times the area of binary divider) while the speed increases linearly (speed of radix 2^k divider is approximately k times that of binary divider). In this paper, a new algorithm that makes use only of the even multiples of the divisor is proposed. The area is nearly halved since the number of multiples is reduced from 2^k to 2^k^-^1. We use the even multiples rather than the odd ones because the even multiples are easier to generate and some of them are produced by simply shifting the divisor. For example, the even multiples 2D and 4D are generated by shifting D one and two bits to the left, respectively, while the odd multiples 3D and 5D require an addition of D to 2D and D to 4D, respectively.