Queue Structure Research Articles

VME imaging boards target machine vision: Birenbaum, R I and King, D RDigital Des. Vol 16 No 8 (May 1986) pp 28–32

In order to conduct an accurate hydrological analysis of a watershed, certain conditions need to be understood. Flow direction and flow accumulation are important watershed characteristics that need to be determined before an analysis can be made. Other important characteristics which can be gleaned from analysing the digital elevation model (DEM) of a watershed include channel networks, stream lengths and watershed boundaries. Determining flow direction and flow accumulation is usually carried out in separate steps. Flat regions are types of terrain in raster DEMs without local elevation gradients. Evaluating flow direction and flow accumulation in flat regions using DEMs is a well-known problem in watershed analysis because of the occurrence of problematic parallel flow lines. Calculations also tend to be time-consuming. We have developed an efficient and comprehensive integrated approach to assign flow directions and flow accumulation in flat regions. This approach uses values for non-flat flow accumulation and a maze algorithm with a weight value (MW method) to determine several things: a main flow line through the flat area to the local outlet, an octree tree, and first-in first-out queue structures to calculate flow accumulation. The MW method can be applied to hydrologically corrected DEMs and a single flow path can be provided to resolve all flat areas. To investigate the influence on the topological properties of the channel networks, we used this integrated algorithm to extract three sets of flow accumulation areas from existing DEMs. Using this new integrated method was faster than using the two existing methods and produced continuous channel networks without the occurrence of problematic parallel flow lines.

Modified two-moment approach for constant-service tandem queues

A modified two-moment (MTM) method is proposed for waiting-time analysis of constant-service tandem queueing systems. Input to an intermediate queueing station consists of internal stream(s) provided by the output from previous queue(s) in addition to external Poisson traffic. Internal traffic at a queue is assumed to have initially originated from external Poisson sources and is permitted to exit from the tandem path with fixed independent probability. Analysis of such complex configuration is not tractable and known exact results are restricted to very special cases. It is shown that the MTM method provides a systematic and more accurate tool for waiting-time analysis of such queueing structures as compared to other known approximations.

Optimising the queuing system for an ear, nose and throat outpatient clinic

Several authors have considered the problem of the efficient running of hospital outpatient clinics. The first solution was probably by Welch & Bailey (1952). More recent authors include Fetter & Thompson (1966), Vissers (1979), Stafford & Aggarwal (1979). The Ear, Nose and Throat outpatient clinic presents a special case due to the complex queuing structure involved, which is described in the next section. A simulation of this special clinic was undertaken, any useful theoretical results being impossible to obtain.

OR Practice—A Queueing Model for Telephone Operator Staffing

This paper describes a queueing model of telephone operator staffing and the application of the model. The Bell System has used the model to reduce the cost of meeting its service criteria, for planning purposes, and to help explain to regulatory agencies changes in service measurement criteria. The model deals with large server team sizes, bimodal service time distributions, nonstationary arrivals, customer abandonments and reattempts, and certain priority queueing structures.

A unified model and implementation for interprocess communication in a multiprocessor environment

This paper describes interprocess communication and process dispatching on the Intel 432. The primary assets of the facility are its generality and its usefulness in a wide range of applications. The conceptual model, supporting mechanisms, available interfaces, current implementations, and absolute and comparative performance are described. The Intel 432 is an object-based multiprocessor. There are two processor types: General Data Processors (GDPs) and Interface Processors (IPs). These processors provide several operating system functions in hardware by defining and using a number of processor-recognized objects and high-level instructions. In particular, they use several types of processor-recognized objects to provide a unified structure for both interprocess communication and process dispatching. One of the prime motivations for providing this level of hardware support is to improve efficiency of these facilities over similar facilities implemented in software. With greater efficiency, they become more practically useful [Stonebraker 81]. The unification allows these traditionally separate facilities to be described by a single conceptual model and implemented by a single set of mechanisms. The 432 model is based on using objects to play roles. The roles are those of requests and servers. In general, a request is a petition for some service and a server is an agent that performs the requested service. Various types of objects are used to represent role-players. The role played by an object may change over time. The type and state of an object determines what role it is playing at any given instant. For any particular class of request, based upon type and state, there is typically a corresponding class of expected server. The request/server model may be applied to a number of common communication situations. In the full paper, several situations are discussed: one-way requestor to server, two-way requestor to server to requestor, nondistinguished requestors, resource source selectivity, nondistinguished servers, and mutual exclusion. While the model embodies most of the essential aspects of the 432's interprocess communication and process dispatching facilities, it leaves a great many practical questions unanswered. The full paper describes our solutions to those problems which often stand between an apparently good model and a successful implementation, namely: binding, queue structure, queuing disciplines, blocking, vectoring, dispatching mixes, and hardware/software cooperation. With an understanding of the mechanisms employed, the paper then reviews the instruction interface to and potential uses of the port mechanism. This instruction interface is provided by seven instructions: SEND, RECEIVE, CONDITIONAL SEND, CONDITIONAL RECEIVE, SURROGATE SEND, SURROGATE RECEIVE, and DELAY. The implementations of the port mechanism are then discussed. The port mechanism is implemented in microcode on both the GDP and IP. Although the microarchitectures differ, in both cases the implementation requires between 600 and 800 lines of vertically encoded 16-bit microinstructions. The corresponding execution times are roughly comparable, with the IP about 20% slower even though most of its microinstructions are twice as slow. Both implementations resulted from the hand translation of the Ada-based algorithms that describe these operations. Finally, the paper characterizes the performance of the 432 port mechanisms and contrasts its performance to other implementations of similar mechanisms. Three recently implemented mechanisms were chosen: one implemented completely in software (i.e., the Exchange mechanism of RMX/86 [Intel 80]) and two implemented in a combination of hardware and software (i.e., the Star0S and Medusa mechanisms of Cm* [Jones 80]). To make the comparison as fair as possible, times for each system are normalized to account for differences in their underlying hardware. The normalization factor is called a “tick” (similar to [Lampson 80]). In the full paper, the absolute and normalized performance of these implementations is examined in six different cases: conditional send time, conditional receive time, minumum message transit time, send plus minimum dispatching latency time, non-blocking send time, and blocking receive time. These performance comparisons show a 3 to 7x normalized performance advantage over the software implemented RMX/86. They show similar normalized performance to the Cm* implementations.

Policy function scheduling

Scheduling disciplines have traditionally been specified in terms of a queue structure and algorithms for routing jobs within this structure. Alternatively, a discipline may be formally defined by a policy function, a function of job and system parameters. A policy function scheduler is a parameterized scheduler that — when supplied with a specific policy function — behaves like the specified discipline. The formal definition allows performance measures of a discipline (e.g., the response function) to be expressed in terms of the defining policy function. We review the principles of formal definitions, summarize previous queueing-theoretical results concerning response functions of policy function schedulers, and extend them to multiple preemptive job classes with processor-sharing subclasses. For a large variety of disciplines and job classes, we also express the policy functions in terms of the resulting response functions. Given a desired realizable performance goal, this relation serves to determine the discipline that achieves it. Policy function schedulers with their explicit relation between policy and response functions, which we plot for several different job characteristics, thus offer increased precision in controlling the performance of a computer system.

Analysis of an algorithm for priority queue administration

A special kind of priority queue structure, priority trees (p-trees), and an algorithm for building such trees are investigated. The main part of the paper is devoted to a mathematical analysis of the algorithm showing that the expected number of key comparisons to insert a “random” element into a “random”p-tree withn nodes isO((logn)2). Also some practical experiments, comparing different types of priority queue strategies, are presented.

Random insertion into a priority queue structure

The average number of levels that a new element moves up when inserted into a heap is investigated. Two probabilistic models under which such an average might be computed are proposed. A `Lemma of Conservation of Ignorance' is formulated and used in the derivation of an exact formula for the average in one of these models. It is shown that this average is bounded by a constant and its asymptotic behaviour is discussed. Numerical data for the second model are also provided and analyzed.

The covariance structure of queues and related processes – a survey of recent work

This paper surveys recent results on the covariance structure of processes generated by queues and related stochastic processes. The generated processes include the number X(t) of customers at time t, the waiting time Wn of the nth customer and the inter-departure interval Dn, i.e., the interval between departures of the nth and (n+1)th customers. The importance of these results is discussed, particularly in the field of estimation.

The covariance structure of queues and related processes – a survey of recent work

This paper surveys recent results on the covariance structure of processes generated by queues and related stochastic processes. The generated processes include the number X(t) of customers at time t, the waiting time W n of the nth customer and the inter-departure interval D n , i.e., the interval between departures of the nth and (n+1)th customers. The importance of these results is discussed, particularly in the field of estimation.

Hierarchical techniques for the development of realistic models of complex computer systems

This paper presents a case study of the development of a realistic, but analytically soluble, model of a very complex Computer system. This modeling project required the development and application of new dements of technology to support the modeling process. These included the use of a hierarchic structuring procedure to provide a fonnal control structure for the modeling process, and the use of perturbation analysis to correct known deficiencies in the faithfulness of the model representation of the actual system. Particular attention was paid to the effects of passive resources, and to contention and interference effects caused by competition for shared resources. The system actually modeled is the Advanced Logistics System of the United States Air Force Logistics Command. The computer configuration of this system includes multiple CDC Cyber 70 mainframes, a large quantity of extended core storage, and approximately 100 disk drives. The analytic model was validated against a simulation which uses the logical queue structure of the software system as its basis. Excellent agreement was obtained. The entire modeling process was completed and documented in two months by a team of six analysts.

Analysis of A time‐shared processor

AbstractThis paper analyzes a queueing structure for a time‐shared service facility (or processor) and compares these results with a straightforward first‐come first‐served discipline. The assumption is that the processing time for each job is chosen from a geometric distribution. This time‐shared discipline shares the desirable features of a first‐come first‐served principle, as well as that of a discipline which services short jobs first. It is shown that those jobs with shorter than average processing requirements, spend less time in the queue than they would in a strict first‐come first‐served system, and conversely for longer than average jobs.