Quaternary Signed Digit Research Articles

Design and implementation of low power and high speed multiplier using quaternary carry look-ahead adder

Need of Digital Signal Processing (DSP) systems which is embedded and portable has been increasing as a result of the speed growth of semiconductor technology. Multiplier is a most crucial part in almost every DSP application. So, the low power, high speed multipliers is needed for high speed DSP. Array multiplier is one of the fast multiplier because it has regular structure and it can be designed very easily. Array multiplier is used for multiplication of unsigned numbers by using full adders and half adders. It depends on the previous computations of partial sum to produce the final output. Hence, delay is more to produce the output. In the previous work, Complementary Metal Oxide Semiconductor (CMOS) Carry Look-ahead Adders (CLA) and CMOS power gating based CLA are used for maximizing the speed of the multiplier and to improve the power dissipation with minimum delay. CMOS logic is based on radix 2(binary) number system. In arithmetic operation, major issue corresponds to carry in binary number system. Higher radix number system like Quaternary Signed Digit (QSD) can be used for performing arithmetic operations without carry. The proposed system designed an array multiplier with Quaternary Signed Digit number system (QSD) based Carry Look-Ahead Adder (CLA) to improve the performance. Generally, the quaternary devices require simpler circuit to process same amount of data than that needed in binary logic devices. Hence the Quaternary logic is applied in the CLA to improve the speed of adder and high throughput. In array multiplier architecture, instead of full adders, carry look-ahead adder based on QSD are used. This facilitates low consumption of power and quick multiplication. Tanner EDA tool is used for simulating the proposed multiplier circuit in 180 nm technology. With respect to area, Power Delay Product (PDP), Average power proposed QSD CLA multiplier is compared with Power gating CLA and CLA multiplier.

Logical Design of Quaternary Signed Digit Conversion Circuit and its Effectuation using Operational Amplifier

In binary number system carry is a major problem in arithmetical operation. We have to suffer O(n) carry propagation delay in n-bit binary operation. To overcome this problem signed digit is required for carry free arithmetical operation. Further, literature reviews suggest that multi-valued logic (MVL) would be a better choice to address the problem of developing faster chips for performing faster computational operation. Quaternary Signed Digit (QSD) have a major contribution in higher radix (=4) carry free arithmetical operation. For digital implementation, the signed digit quaternary numbers are represented using 3-bit 2's compliment notation. In this paper, a simple and new technique of binary (2's compliment) to QSD conversion is proposed and described. Well-known operational amplifier (OPAMP) based digital to analog converter circuit is also given to verify the above technique.

Interferometric switch based all optical scheme for conversion of binary number to its quaternary-signed digit form

Multi-valued logic (with radix>2) can be viewed as an alternative approach to solve many problems in transmission, storage and processing of large amount of information in digital signal processing. In arithmetical operation signed digit number is very essential for carry free computation. To achieve the parallelism in computation, a suitable number system and an efficient encoding/decoding scheme for handling the data are very much essential. In radix-4 system negative number is represented by quaternary-signed digit (QSD). In this study a conversion from 3-bit binary number (2's complement representation) to its equivalent single-digit QSD is reported. The technique for conversion of QSD to its binary equivalent form is also presented. All-optical circuits are designed with non-linear material-based interferometric switches such as terahertz optical asymmetric demultiplexer in optical tree architecture, where the numbers are represented by different discrete polarised state of light. Device-based simulation of the proposed optical circuit is used to verify the operation of the optical converter.

Parallel computation of complex elementary functions using quaternary signed-digit arithmetic

A variety of algorithms for computing complex elementary functions based on the quaternary signed-digit (QSD) number system are proposed. An arithmetic unit that performs parallel one-step addition (subtraction), multiplication, and division is proposed to perform the computations of elementary functions such as square root, logarithmic, exponential, and other related functions. An optoelectronic-correlator-based architecture is suggested for implementing the proposed QSD elementary function algorithms. We used the symbolic substitution technique to reduce the number of the computation rules involved.

Two-step optoelectronic quaternary signed-digit adder using optical correlation

A symbolic substitution (SS) based optical numeric processor using quaternary signed-digit (QSD) number representations is proposed. Also, we propose new joint spatial encodings for the QSD numbers that reduce the SS computation rules involved in the processor. Optoelectronic implementation of the proposed QSD adder is feasible. The proposed adder is more compact than recently reported QSD counterparts.

Canonical quaternary signed-digit arithmetic using optoelectronics symbolic substitution

A higher radix based signed-digit number system, such as the quaternary signed-digit (QSD) number system, allows higher information storage density, less complexity, fewer system components, and fewer cascaded gates and operations. An optoelectronics symbolic substitution scheme to handle the parallel quaternary signed-digit (QSD) arithmetic operations is proposed. A conversion algorithm is employed on the QSD numbers to simplify the addition process and reduce the number of the optical symbolic substitution rules. The optical addition operation of two QSD numbers is performed in one-step. An efficient shared content-addressable memory (SCAM)-based optical implementation of the QSD addition/subtraction operations employs a fixed number of minterms for any operand length. The canonical QSD number addition/subtraction scheme requires a significantly reduced number of minterms when compared with a similar previously reported technique.

High-radix signed-digit arithmetic using symbolic substitution computations

High-radix number representations such as the quaternary signed-digit (QSD) number system allow higher information storage density, less complexity, fewer system components, and fewer cascaded gates and operations. Arithmetic operations on the quaternary signed-digit are carried out using the powerful symbolic substitution scheme. A single-step or two-step conversion algorithm is employed on the QSD numbers to simplify the higher-order QSD addition process and reduce the number of the optical symbolic substitution rules. The optical addition operation of two QSD numbers is performed in one step. An efficient content-addressable memory (CAM) optical implementation of the QSD addition/subtraction operations is proposed. The QSD number addition/subtraction operations require a significantly reduced number of minterms (symbolic substitution rules) when compared to a similar previously reported technique.