Quasi-static Capacitance Research Articles

Reversible interaction of hydrogen with thin layers of thermally grown silicon dioxide

Some effects of hydrogen on the electrical properties of Pd-metal-thin (≊10 nm) oxide-silicon capacitors are reported. High-frequency (1 MHz) and quasistatic capacitance voltage curves are measured at 100 °C as a function of hydrogen partial pressure in a background atmosphere of 20% O2/Ar. Besides the standard hydrogen-induced shift of the capacitance-voltage characteristics we find: (1) an increase in the accumulation capacitance with increasing hydrogen partial pressure, and (2) a nonmonotonic increase in the quasistatic capacitance minimum with increasing hydrogen pressure. The relative increase in the accumulation capacitance is shown to be related to the square of the hydrogen-induced voltage shift (and hence to the square of the concentration of hydrogen atoms at the Pd-SiO2 interface). We discuss our findings, based on existing hydrogen-silicon dioxide models, to interpret the effects of hydrogen on the high-frequency and quasistatic capacitance characteristics.

Forward-voltage capacitance of heterojunction space-charge regions

An analytical treatment is presented for modeling the capacitance of heterojunction space-charge regions under forward voltages. First, the conventional depletion model is reviewed and the inadequacy of the use of such a model at forward voltages is noted. The study then turns to the development of a more accurate model for the thickness and potential barrier of the space-charge region for all voltages. Based on this model and the approximation that the intrinsic level is piecewise linear with respect to position in the space-charge region, an analytical quasistatic capacitance model applicable for forward-biased conditions is derived. The model, however, encounters difficulties at very large forward voltages, and a qualitative treatment is employed there. The comparison of the present capacitance model with measured dependencies and with existing capacitance models is included.

Quasistatic capacitance of p/n junction space-charge layers by the Leibnitz rule

The Leibnitz rule of integral calculus yields a useful expression for the quasistatic capacitance versus voltage characteristic of a p/n junction space-charge layer that holds for all doping profiles and for forward as well as for reverse applied voltages. This capacitance is the sum of two components. One accounts for the incremental mobile charge within the volume of the layer. The other accounts for the incremental mobile charge at its edges.This expression enables novel analytical characterizations and interpretations of numerical solutions.

High-forward-voltage junction capacitance including effects of excess carrier storage in electron-hole plasma

A previous quasistatic junction space-charge region capacitance model is improved by including the Fermi statistics and energy band-gap narrowing that occurs in electron-hole plasmas. The model is applicable for junctions under large forward voltages. A factor of 2–4 is predicted when the present capacitance model is compared with the previous capacitance model.

Forward-voltage capacitance and thickness of p-n junction space-charge regions

A comprehensive analytical model for the quasi-static capacitance of the space-charge region of p-n junction devices is presented. It describes the capacitance for all voltages, including voltages large enough to cause the junction barrier to vanish. The model applies for exponential-constant doping profiles, the limiting cases of which are the step and the linear-graded profiles. In addition to the analytical model, an iterative technique is developed to yield numerically the thickness of the space-charge region as a function of voltage. The capacitance model shows good agreement when compared with measured dependencies, With an empirical model for circuit simulation, and with models based on device simulation. The model extends previous replacements of the depletion capacitance, provides a tool for circuit simulation, and is intended to provide understanding of the physics related to storage of mobile holes and electrons in the junction space-charge region.

Mos constant current quasi-static smallsignal technique for determination of low interface states distribution of Si−SiO2 system

A new technique know as “MOS Constant Current Quasi-static Small-Signal Technique” by which quasi-static capacitance, high frequency capacitance, and semiconductor surface potential of a MOS capacitor can be measured simultaneously is proposed. The low interface states densities and its distribution of Si−Sio2 system can be rapidly and accurately determined by this technique. By the use of synchronous differential amplification technique with limited amplitude, the sensitivity of measuring interface states densities can be raised about an order of magnitude.

The electrical properties of Hg-sensitized “photox”-oxide layers deposited at 80°C

This paper deals with the electrical properties of low-pressure CVD SiO 2 deposited at 80°C. The deposition rate is enhanced by UV radiation in the presence of Hg vapor. The photo-enhanced low-pressure chemical-vapor-deposited oxide, known also as “photox,” offers a good quality oxide deposited at temperatures as low as 80°C. The films are deposited in a batch-load “photox” barrel reactor and subsequently annealed at 950°C for 30 min in a conventional hot-wall furnace. Cold-sputtered aluminum-gate guard-ring capacitors are fabricated on the oxide films. High-frequency and quasi-static capacitance measurements indicate the interfacial properties of “photox” are comparable to those of thermal oxide. Fast interface states density are less than 2 × 10 10 cm −2 eV −1 and a light negative interfacial charge could just be detected. The dielectric breakdown field is typically 4–5 MV/cm. Deep-depletion transient-capacitance measurements were performed at temperatures between 20 and 100°C to investigate the possible impact of “photox” processing on the generation lifetime. The Hg in particular might be suspected as a heavy-metal contaminant. Typical recovery times observed at 20°C were in the range of 10–15 min. The generation lifetime derived from such measurements ranges from 140 to 200 μs which is comparable to values for control samples made with standard thermal oxide. The magnitude and temperature dependence of the generation lifetime suggest that the same G-R centers are present in both “photox” and thermal oxide devices. The only apparent electrical effect of the Hg vapors used in the deposition process is a small negative fixed interface charge, 2 × 10 10 cm −2.

Degradation of the electrical characteristics of the Si–SiO2 interface induced by electron injection

The effects of electron injection on the electrical characteristics of the Si–SiO2 interface have been studied on metal-oxide-semiconductor type structures incorporating very thin oxide films (≲200 Å). Electron current across the oxide is obtained by Fowler–Nordheim tunneling in Al:SiO2:Si structures or by enhanced Fowler–Nordheim tunneling in Al:Si-rich-SiO2:SiO2:Si devices. The changes induced by charge injection in these structures were monitored by measuring the 1-MHz and the quasistatic capacitance versus voltage characteristic curves. In both structures negative charge trapping in the oxide and positive charge accumulation were observed as well as generation of interface states at approximately 0.6 eV from the top of the Si valence band. However, in structures with Si-rich-SiO2 layers an anomalous peak in the quasistatic capacitance curves was observed to be induced by the injection of electrons. The role of the Si-rich-SiO2 layer in these phenomena is discussed.

Modeling MOS capacitors to extract Si—SiO2interface trap densities in the presence of arbitrary doping profiles

A conventional Poisson solver has been used to calculate the quasi-static capacitance of an MOS capacitor. The effects of an energy dependent Si-SiO 2 interface trap density and of an arbitrary silicon substrate doping profile have been included. This model has been used to calculate the quasi-static C-V characteristics and to compare them with those measured using Kuhn's technique for as-received and for gamma-irradiated p-type and n-type silicon MOS capacitors. The substrate doping profiles were obtained from high-frequency C-V curves. Experimental and theoretical C-V curves were made to agree by varying the voltage offset due to fixed oxide charge and both the magnitude and the energy distribution of interface trapped charge. The distributions of interface traps that gave the best fits between experiment and theory are donor-like with a peak 0.1 eV below midgap for the p-type and 0.1 eV above midgap for the n-type silicon MOS capacitors. The predicted C-V curves are insensitive to increases in the density of interface traps near the band edge.

Transit time and charge storage measurements in heavily doped emitters

We report results of a first direct measurement of the minority-carrier transit time in a transparent heavily doped emitter layer. The value was obtained by a high-frequency conductance method recently developed and used for low-doped Si. The transit time coupled with the steady-state current enables the determination of the quasi-static charge stored in the emitter and the quasi-static emitter capacitance. Using a transport model, we estimated, from the measured transit time, the value for the minority-carrier diffusion coefficient and mobility. The measurements were done using a heavily doped emitter of the Si p+-n-p bipolar transistor. The new result indicates that the position-averaged minority-carrier diffusion coefficients may be much smaller than the corresponding majority-carrier values for emitters having a concentration ranging from about 3 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">20</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> .

Measurement and modeling of charge feedthrough in n-channel MOS analog switches

Charge feedthrough in analog MOS switches has been measured. The dependence of the feedthrough voltage on the input and tub voltages, device dimensions, and load capacitances was characterized. Most importantly, it was observed that the feedthrough voltage decreases linearly with the input voltage. The significance of this observation when considering harmonic distortion in sample-and-hold circuits is discussed. A first-order computer simulation based on the quasi-static small-signal MOSFET capacitances shows good agreement with experimental results.

PH dependence of the Si/SiO 2 interface state density for EOS systems : Quasi-static and AC conductance methods

Two combined impedance methods, developed for solid state MOS (Metal Oxide Semiconductor) devices, are used to check the electrical properties of home-made EOS (Electrolyte Oxide Semiconductor) systems. This set-up, fitted with a three-electrode monitoring system, allows both the quasi-static capacitance and the ac conductance of wet heterostructures to be measured. The two sets of data, which complement each other perfectly, show that for oxidized silicon EOS devices, the pH has an extremely small and erratic influence on the Si/SiO 2 interface state density. This result confirms that the sensitive dielectric interface in such pH sensors is the SiO 2/electrolyte interface.

Electrical properties of the SiO2:HgCdTe interface

By determining the dependence of flatband bias on insulator thicknesses in MIS devices made with PHOTOX SiO2 on n-type Hg0.7Cd0.3Te, we have for the first time determined the amount of interface charge and the effective work function of the semiconductor surface. Flatband bias was determined from the surface potential as obtained by Berglund integration of quasistatic capacitance measurements at 77 K. Insulator thickness was varied from 500 to 4000 Å. The amount of fixed charge was seen to vary between −0.3×109 cm−2 and +8×1010 cm−2 depending on the type of deposition sequence used. It was also seen that H2O could be absorbed into the layer and removed by vaccum baking at temperatures of 60–100 °C and resulted in a change of interface fixed charge of up to 8×1010 cm−2. This is in agreement with the range of charge variation seen above. The presence of large amounts of H2O also was seen to introduce surface states at 0.06 and 0.14 eV above the valence band edge (Eg=0.24 eV at 77 K). The effective work function difference between the Ti/ Au bilayer gate and the HgCdTe surface was determined to be +0.03 V ±0.05 V.

The Si–SiO2 interface: Correlation of atomic structure and electrical properties

The roughness at the Si–SiO2 interface has been determined quantitatively on an atomic scale by SPA-LEED (spot profile analysis of low energy electron diffraction) in ultrahigh vacuum after removal of the oxide. At the Si–SiO2 interface the steps are randomly distributed. With the help of model calculations the measured spot broadening provides the step atom density and therefore the roughness on an atomic scale. The roughness will be decreased by low oxidation rates (thick oxides, dry atmosphere) and appropriate annealing in N2 and will be increased by high oxidation rates (thin oxides and wet atmosphere). Furthermore metal oxide semiconductor (MOS) structures were built on chips which were also suited for LEED measurements. Hall mobilities for Si(111) p-channel inversion layers MOS-FETs with varying roughness at the Si–SiO2 interface have been measured at temperatures between 4.2 K and room temperature. It was found that there exists a strong correlation between Hall mobility and atomic roughness at high inversion, nearly a proportionality. Even at room temperature the transistors with the lower interface roughness exhibit the higher mobility. Further quasistatic capacitance–voltage (C–V) measurements have been performed on Si(111) MOS structures with different but well-known atomic roughness. The results demonstrate a strong correlation between atomic roughness and interface state density too, even after an additional postmetallization-annealing (PMA) treatment. A simple model which is associated with each kind of step atom, i.e., edge or kink atoms, suggests the creation of a dangling bond and therefore, a surface state can explain the result. Assuming that ionized atoms which are responsible for Qfix are located preferentially at those steps or kinks which are also correlated to the dangling bonds at the interface, we confirm the general opinion that Qfix and surface states have at least one common physical origin: the atomic roughness.

Spectral Domain Analysis of an Elliptic Microstrip Ring Resonator (Short Paper)

The quasi-static capacitance of an elliptic microstrip ring resonator is evaluated with the spectral domain technique. The effect of fringing of fields associated with the structure is determined using this capacitance value in terms of the effective eccentricities of the inner and outer ellipses, the effective values of the ratio of the semimajor and semiminor axes, and the effective dielectric constant. The resonant frequency of the even TM /sub c110/ mode, calculated utilizing them, is in good agreement with the experiment. Mode charts for the dominant and higher order even and odd TM/sub cm10/ resonance modes are also presented.

Quasi-static capacitance and ultra slow relaxation of linear and non-linear dielectrics

Abstract The time dependence of quasi-static capacitance of linear and non-linear materials can be measured using a constant voltage ramp method. The measured data are consistent with a theoretical equation derived from a superposition theorem. The capacitance of fast polarization, saturated polarization and the time constant of the relaxation process can be obtained using a non-linear least squares method. Ultra slow relaxation for linear dielectrics and ferroelectrics are reported.

Limitations of quasi-static capacitance models for the MOS transistor

This letter compares the Meyer [1] and Ward [2,3] quasi-static, intrinsic capacitance formulations for the MOS transistor to an exact, non-quasi-static, incremental analysis of a simplified device. This analysis yields an incremental admittance matrix for the device whose terms are ratios of power series. The Meyer and Ward models are shown to be approximations to this exact solution. Experimental admittance versus frequency data are presented which show good agreement with this theory. The high-frequency modeling of the Ward and Meyer formulations are compared to the data above, and the limitations of these models are discussed.

Determination of energy density distribution and capture cross-section of interface states in the metal-nitride-oxide-semiconductor (MNOS) structure

The capacitance and conductance of a metal-nitride-oxide-semiconductor (MNOS) capacitor was measured as a function of voltage at various frequencies between 10 Hz and 200 kHz using a “lock-in” amplifier. The capacitance as a function of voltage was also measured at a frequency of 1 MHz as well as under quasi-static conditions. All the measurements were made at a temperature of 298°K. The high-frequency C-V measurements were used to establish the relation between the surface potential and gate voltage. The experimental data was analysed in terms of the theoretical models of Lehovec and of Deuling et al. to determine the energy density distribution of the interface states. The interface states density calculated from the quasi-static capacitance measurements agreed with those obtained from the low frequency capacitance results analysed in terms of Lehovec's model. However, in the energy range between 0.5 and 0.9 eV, the vlaues of the interface states energy density calculated from fitting the conductance data to the model of Deuling et al. differ from those obtained by the other two methods by as much as a factor of two due to the high density of interface states in the MNOS device. The analysis of conductance data also furnished the values of electron capture cross-section which decreases approximately exponentially with interface states energy, varying from 10 −13 cm 2 at 0.4 eV to 10 −19 cm 2 at 0.86 eV.

A new method for the determination of dopant and trap concentration profiles in semiconductors

A new method is described and experimentally verified using a computer-controlled data acquisition system. It is capable of measuring sharply peaked and rapidly varying impurity-concentration profiles in semiconductors, including situations where the trap density exceeds the dopant density, with resolution limited by the Debye length. It combines two well-known techniques: the constant-capacitance junction voltage transient and the quasi-static junction capacitance measurements as a function of dc bias voltage. We propose the acronym CCQS. New implementation methods of these two techniques are developed which offer better reliability, capability, and convenience than those reported previously. The quasi-static low-frequency capacitance is used to obtain experimentally the edge region correction which was estimated only theoretically in the past. The method is verified using gold-diffused p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> /n and ion-implanted n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> /p silicon diodes.

Gold-related interface states in MOS systems

We studied the trap levels induced by gold in bulk silicon and at the SiSiO 2 interface. We were principally interested their influence on the bulk and surface generation-recombination rates. The study involved the measurement of the low frequency quasi-static capacitance responses (QSM technique). Analysis of the equilibrium and the non-equilibrium behaviour led to the characterization of the gold-related electronically active sites.