Quasi-static Capacitance-voltage Research Articles

Correction to: Quantization Effect in N-Channel Inversion Mode Si, In0.53Ga0.47As and Ge Based Double Gate MOSFET Using Quasi-Static Capacitance–Voltage Characteristics for Upcoming Sub 10 nm Technology Node

Correction to: Quantization Effect in N-Channel Inversion Mode Si, In0.53Ga0.47As and Ge Based Double Gate MOSFET Using Quasi-Static Capacitance–Voltage Characteristics for Upcoming Sub 10 nm Technology Node

Hydrogen Termination Effect on SiO2/Si Interface State Density in CH3O-Molecular-Ion-Implanted Silicon Epitaxial Wafer for CMOS Image Sensors

The reduction in SiO2/Si interface state density (Dit) at the SiO2/Si interface region is important to improve the performance of complementary metal-oxide semiconductor (CMOS) image sensors. The CH3O-ion-implanted region stores hydrogen and releases the stored hydrogen during the subsequent heat treatment. This study demonstrates that a CH3O-ion-implanted epitaxial silicon wafer can reduce the Dit and Pb0 center density in SiO2/Si interface regions, as analyzed by quasi-static capacitance–voltage and electron spin resonance measurements, respectively. Both Dit and Pb0 center density in the CH3O-implanted wafer decreased with increasing heat treatment temperature. Moreover, the activation energy is estimated to be 1.57 eV for the hydrogen termination reactions induced by the CH3O-ion-implanted wafer. The activation energy is close to those of hydrogen molecules and Si dangling bonds at the SiO2/Si interface. This result means that Dit can be reduced by hydrogen from inside the silicon wafer, regardless of the heat treatment atmosphere. It has unique characteristics not found in conventional silicon wafers. The termination effect of the CH3O-molecular-ion-implanted epitaxial silicon wafers can contribute to the high electrical performance of CMOS image sensors.

Sources of error and methods to improve accuracy in interface state density analysis using quasi-static capacitance–voltage measurements in wide bandgap semiconductors

Characterizing interface trap states in commercial wide bandgap devices using frequency-based measurements requires unconventionally high probing frequencies to account for both fast and slow traps associated with wide bandgap materials. The C−ψS technique has been suggested as a viable quasi-static method for determining the interface trap state densities in wide bandgap systems, but the results are shown to be susceptible to errors in the analysis procedure. This work explores the primary sources of errors present in the C−ψS technique using an analytical model that describes the apparent response for wide bandgap MOS capacitor devices. Measurement noise is shown to greatly impact the linear fitting routine of the 1/CS∗2 vs ψS plot to calibrate the additive constant in the surface potential/gate voltage relationship, and an inexact knowledge of the oxide capacitance is also shown to impede interface trap state analysis near the band edge. In addition, a slight nonlinearity that is typically present throughout the 1/CS∗2 vs ψS plot hinders the accurate estimation of interface trap densities, which is demonstrated for a fabricated n-SiC MOS capacitor device. Methods are suggested to improve quasi-static analysis, including a novel method to determine an approximate integration constant without relying on a linear fitting routine.

Evaluation of the border traps in LPCVD Si3N4/GaN/AlGaN/GaN MIS structure with long time constant using quasi-static capacitance voltage method

We extract the electric properties of border traps with long time constant in low-pressure chemical vapor deposition (LPCVD) Si3N4/GaN/AlGaN/GaN metal–insulator–semiconductor (MIS) structure using quasi-static capacitance voltage method. The energy and depth distribution of the border traps is calculated based on the analysis of energy band diagram and charging dynamic of border traps in the MIS structures. With this method, it is found that LPCVD Si3N4/GaN/AlGaN/GaN MIS structure have a high density of border traps in the order up to 1021 cm−3 eV−1 located at energy level between E C,GaN − 0.04 eV and E C,GaN − 0.66 eV with distance of 1.0–4.2 nm from the Si3N4/GaN interface. Microstructure analysis suggests that the high density of border traps is possibly correlated to the oxygen content at the Si3N4/GaN interface. Meanwhile, the proposed method is also suitable for MIS or metal-oxide-semiconductor structure on other semiconductors, providing another powerful tool to analysis the physical properties of border traps.

Hydrogen passivation for reduction of SiO2/Si interface state density using hydrocarbon-molecular-ion-implanted silicon wafers

The reduction in the density of SiO2/Si interface state (Dit) in the isolation region and transfer transistor gate oxide is necessary to improve the performance of complementary metal-oxide semiconductor (CMOS) image sensors. In this study, we demonstrated that a hydrocarbon-molecular-ion-implanted epitaxial silicon wafer can reduce the Dit and Pb0 center density in SiO2/Si interface regions analyzed by quasi-static capacitance–voltage and electron spin resonance measurements, respectively. The Dit and Pb0 center density of wafers without hydrocarbon molecular ions increased after annealing at 700 °C. On the other hand, the Dit and Pb0 center density of wafers implanted with hydrocarbon molecular ions decreased after annealing at 700 °C. We also estimated the activation energy to be 1.67 eV for the hydrogen termination reactions with hydrogen molecules and Si dangling bonds at the SiO2/Si interface. The termination effects of the hydrocarbon-molecular-ion-implanted epitaxial silicon wafers can contribute to the high electrical performance of CMOS image sensors.

Effect of Channel Engineering on Quasi-Static Capacitance-Voltage Characteristics of Double-Gate MOSFET

The quasi-static capacitance–voltage (QSCV) characteristics of 10-nm-gate-length double-gate N-type metal–oxide–semiconductor field-effect transistors (NMOSFETs) with Si, Ge, InAs, $$ {\hbox{In}}_{0.53} {\hbox{Ga}}_{0.47} {\hbox{As}} $$ , and GaAs as channel materials are studied and simulated using Silvaco ATLAS three-dimensional (3D) technology computer-aided design (TCAD) software. The QSCV approach offers the advantage of immunity against frequency dependence effects and the ability to measure small capacitances in the 100 fF range. In this device, we consider the self-consistent solution of Schrodinger’s equation with Poisson’s equation. The splitting of the conduction band into multiple subbands is considered, while there is no doping in the channel region. The effects of metal gate electrode engineering, channel engineering (Si, Ge, GaAs, $$ {\hbox{In}}_{0.53} {\hbox{Ga}}_{0.47} {\hbox{As}} $$ , and InAs), and different channel thicknesses with $$ \left( {{\hbox{Al}}_{2} {\hbox{O}}_{3} } \right) $$ as gate oxide having thickness of 0.8 nm on the QSCV characteristics are studied. A comparison of the QSCV characteristics is carried out for the above-mentioned channel materials, revealing a significant reduction in the inversion-mode QSCV characteristics for all the materials due to quantization that results in a decrease in the overall gate-to-channel capacitance and hence increases the threshold voltage of the MOS device. The QSCV characteristics are also useful to measure the oxide thickness, flat-band voltage, threshold voltage, maximum depletion region thickness, charge distribution in the dielectric, interface trap charge, and interface states between the channel and gate oxide before device fabrication.

Metal gate electrode, channel and gate oxide engineering to improve DC and analog/RF performance of double-gate MOSFET for high-speed applications

In the present work, for high-speed and high-frequency applications, various DC and analog/RF parameters like drain current ( $$I_{{\text{D}}}$$ ), transconductance $$(g_{m} )$$ , output conductance $$(g_{d} )$$ , transconductance generation factor (TGF), the cutoff frequency $$(f_{T} )$$ , transit time $$\left( \tau \right)$$ , frequency transconductance product (FTP), channel resistance $$(R_{{{\text{ch}}}} )$$ , direct tunneling current ( $$I_{{\text{G}}}$$ ) and quasi-static capacitance–voltage (QSCV) characteristics for 10-nm double-gate NMOSFETs of Si and $${\text{In}}_{0.53} {\text{Ga}}_{0.47} {\text{As}}$$ have been studied and simulation results are reported using Silvaco ATLAS 3D TCAD. In this device, we consider the drift diffusion approach and the self-consistent solution of Poisson’s equation with Schrodinger’s equation (to account for quantization). The effect of including conduction band splitting into multiple sub-bands has been taken into account, and the channel region is very lightly doped. The effect of metal gate electrode, channel and gate oxide engineering on $$I_{{\text{D}}}$$ , $$g_{m}$$ , TGF, $$g_{d}$$ , $$f_{T}$$ , $$\tau$$ , TFP, $$R_{{{\text{ch}}}}$$ , $$I_{{\text{G}}}$$ and QSCV has been simulated. Also, a comparison of these parameters has been done between Si and $${\text{In}}_{0.53} {\text{Ga}}_{0.47} {\text{As}}$$ . It was found that except TGF at the higher $$V_{{{\text{GS}}}}$$ and $$I_{{\text{G}}}$$ values for Si, all the other above-mentioned parameters are higher for $${\text{In}}_{0.53} {\text{Ga}}_{0.47} {\text{As}}$$ . It was found that there is about 7.99 × 105% increase in $$I_{{{\text{ON}}}}$$ for $${\text{In}}_{0.53} {\text{Ga}}_{0.47} {\text{As}}$$ as compared to Si. Also, the device has a small drain-induced barrier lowering ~ 8.44 mV/V, almost an ideal subthreshold slope ~ 60 mV/dec and high ION/IOFF ratio ~ 6.30 × 107.

Trap Characterization of ALD Al2O3/4H-SiC Metal-Oxide-Semiconductor Interfaces

4H-Silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs) are enabling high-efficiency power switching applications under high-temperature, and harsh environment conditions because of SiC’s superior physical properties. However, 4H-SiC MOSFETs have a much lower channel conductance due to the trapping of electrons by a high-density of near-interface traps (NITs) at the SiO2/4H-SiC interface [1,2]. These states are spatially located within ~1 nm from the interface and energetically positioned near the conduction band edge of 4H-SiC. Among the many approaches to solve this issue, using atomic layer deposition (ALD) of high k-dielectrics such as Al2O3 is promising. It has been reported that appropriate surface termination of 4H-SiC prior to ALD with hydrogen [3,4] or SiO [5,6] results in improved properties of Al2O3/4H-SiC MOS devices. The SiO termination refers to the insertion of an ultra-thin (~0.7 nm) silicon oxide layer between Al2O3 and 4H-SiC that results in effective channel mobility greater than 250 cm2Vs-1[5, 6]; significantly higher than that obtained by using standard nitrided (NO annealed) [7] SiO2 as the gate dielectric. In this work, we studied the above two surface termination approaches for ALD Al2O3 using electrical characterization and compared to typical thermally grown SiO2. To this end, Si-face n-type 4H-SiC MOS capacitors were fabricated and characterized using the simultaneous high-low frequency capacitance-voltage (CV), current-voltage (IV) and constant capacitance deep level transient spectroscopy (CCDLTS). For H- termination, prior to ALD, samples were etched in H2 at 1600 ◦C followed by annealing in H2 at 1000 ◦C [3, 4]. Following this, ALD was performed at 200 °C using Trimethylaluminum (TMA, Al(CH3)3) as the precursor to deposit ~50 nm of Al2O3. Electrical measurements were carried out after patterning and deposition of Au/Ti gates. In these samples, the interface state density (Dit ~3x1011 cm-2eV-1) near the conduction band edge was comparable to nitrided SiO2 as shown in Fig. 1. In addition, the CCDLTS showed that the typical ‘O1’ and ‘O2’ NITs[8] detected by CCDLTS at 4H-SiC/SiO2 interfaces, with emission activation energies of about 0.15±0.05 eV and 0.39±0.1 eV[4,8] below the 4H-SiC conduction band, were absent at these Al2O3/4H-SiC interfaces (Fig.2), which is extremely encouraging. In the second surface termination approach, ultra-thin (<1 nm) silicon oxide layers were grown thermally before Al2O3 deposition. Different oxidation conditions were employed varying the furnace temperature as 550 ◦C, 600 ◦C and 650 ◦C with 5 min oxidation time. Then, ~40 nm Al2O3 was deposited using the above ALD process and Al gate contacts were formed. Figure 3 shows the typical quasistatic CVs. It can be clearly observed that, with increasing oxidation temperature, the CV curves shift to the left indicating a reduction of negative charges at the interface, consistent with Dit reduction. However as shown in Fig.1, the simultaneous high-low CV reveals much higher Dit for these devices (~1x1013 cm-2eV-1 near the conduction band edge), comparable to typical unpassivated thermal oxides. Previous reports suggest that the ultra-thin oxide film thickness should be about ~0.7 nm to obtain low Dit and high channel mobility [5,6]. Our preliminary XPS analysis suggests that our film thickness is less than this critical value which might be the cause of the higher Dit here. Therefore, within our current results, we observe that surface H-termination prior to ALD of Al2O3 results in significantly lower Dit compared to SiO termination. Further studies with thicker SiO interlayers will be presented at the conference along with chemical bonding results from XPS analysis. Acknowledgments: This work was supported by the II-VI Foundation and US Army Research Lab. The authors thank Drs. Chunkun Jiao and Koushik Ramadoss from Purdue and Drs. Leonard C. Feldman and Ryan Thorpe from Rutgers University for sample fabrication and XPS analysis. [1] T. Kimoto, and J. A. Cooper, Fundamentals of Silicon Carbide Technology, John Wiley, 2014. [2] B. J. Baliga, Fundamentals of power semiconductor devices,1st edn., Springer, US, 2010. [3] T. Seyller, Appl. Phys. A. 85. 4. 371–385, Dec. 2006. [4] I. Jayawardhena, A. Jayawardena, C. Jiao, D. Morisette, and S. Dhar, Materials Science Forum, Proceedings of the 2018 ECSCRM (accepted 2019) [5] T. Hatayama, S. Hino, N. Miura, T. Oomori, and E. Tokumitsu, IEEE Trans. Electron Devices. 55. 8. 2041–2045. 2008. [6] J. Urresti, F. Arith, S. Olsen, N. Wright, and A. O’Neill, IEEE Trans. Electron Devices,66, 4, 1710–1716, Apr. 2019. [7] G. Y. Chung et al., Appl. Phys. Lett. 76. 13. 1713–1715, 2000. [8] A. F. Basile, J. Rozen, J. R. Williams, L. C. Feldman, and P. M. Mooney, J. Appl. Phys., 109, 6, 064514, Mar. 2011. Figure 1

Characterization of Deep and Shallow Traps in GaN HEMT Using Multi-Frequency C-V Measurement and Pulse-Mode Voltage Stress

In this paper, the influence of interface traps at the SiN/GaN interface and carbon-related buffer traps on GaN high electron mobility transistor (HEMT) on silicon substrate has been studied using high-frequency capacitance-voltage (HFCV) and quasi-static C-V (QSCV) measurement. The correlation between dynamic resistance degradation and trap density distribution subjected to pulse stress conditions has been examined. Deeper-level traps from the hole-emission process of the carbon-related buffer layer are activated by high drain voltage during off-state stress, and shallow-level traps at the SiN interface are enhanced by an increase in gate voltage during the on-state stress. 2-D device simulations have been carried out to probe the physical insight into the dynamic resistance degradation. Good agreement between experimental data and simulated results is obtained while taking into account shallow-level and deeper-level traps.

Effect of Grinding-Induced Stress on Interface State Density of SiC/SiO2

Back-grinding process was applied to the 4H-SiC (0001) epitaxial wafers. We found that the parameters about stress increased after back-grinding process. In our work, the characterization of stress on interface state density (Dit) of SiC/SiO2 was investigated. Furthermore, the absorption of peak frequencies was also observed by fourier transform infrared spectroscopy attenuated total reflection (ATR-FTIR) analysis, and the Dit of SiC/SiO2 was obtained by quasi-static capacitance voltage (QSCV) measurement as well as C-φs method. The above results suggested that the Dit increased with the increasing grinding-induced stress.

Structural, optical, and electrical properties of orthorhombic κ-(InxGa1−x)2O3 thin films

Material properties of orthorhombic κ-phase (InxGa1−x)2O3 thin films grown on a c-plane sapphire substrate by pulsed-laser deposition are reported for an indium content up to x ∼ 0.35. This extended range of miscibility enables band gap engineering between 4.3 and 4.9 eV. The c-lattice constant as well as the bandgap depends linearly on the In content. For x &amp;gt; 0.35, a phase change to the hexagonal InGaO3(ii) and the cubic bixbyite structure occurred. The dielectric function and the refractive index were determined by spectroscopic ellipsometry as a function of the alloy composition. We propose zirconium to induce n-type conductivity and have achieved electrically conducting thin films with a room temperature conductivity of up to 0.1 S/cm for samples with a low In content of about x = 0.01. Temperature-dependent Hall-effect measurements yielded a thermal activation energy of the free electron density of 190 meV. Schottky barrier diodes with rectification ratios up to 106 were investigated by quasi-static capacitance voltage and temperature-dependent current voltage measurements.

The Impact of Ti/Al Contacts on AlGaN/GaN HEMT Vertical Leakage and Breakdown

Enhanced leakage paths below Ti-/Al-based contacts to GaN-on-Si HEMTs have been identified and studied. Through a novel use of the quasi-static capacitance–voltage technique, the depth of these preferential leakage paths was determined to be $\sim 1.6~\mu \text{m}$ , extending down into the superlattice strain relief layer. Along these paths, the material resistivity was reduced by more than a factor of 100 compared to the uncontacted epitaxy. It is suggested that the cause of the additional leakage is decoration of dislocations. This result is important for understanding buffer transport, a critical parameter for breakdown, and buffer charge storage.

Temperature dependent quasi-static capacitance-voltage characterization of SiO2/β-Ga2O3 interface on different crystal orientations

The interface trap density (Dit) of the SiO2/β-Ga2O3 interface in (2¯01), (010), and (001) orientations is obtained by the Hi-Lo method with the low frequency capacitance measured using the Quasi-Static Capacitance-Voltage (QSCV) technique. QSCV measurements are carried out at higher temperatures to increase the measured energy range of Dit in the bandgap. At room temperature, higher Dit is observed near the band edge for all three orientations. The measurement at higher temperatures led to an annealing effect that reduced the Dit value for all samples. Comparison with the conductance method and frequency dispersion of the capacitance suggests that the traps at the band edge are slow traps which respond to low frequency signals.

Analysis of border and interfacial traps in ALD-Y2O3 and -Al2O3 on GaAs via electrical responses - A comparative study

Y2O3 and Al2O3 were in-situ atomic layer deposited (ALD) on pristine GaAs(001)-4×6 reconstructed surfaces without surface pretreatments. We have studied the border and interfacial traps in both hetero-structures using the measured electrical responses. On the basis of frequency dispersion analysis of the capacitance-voltage (CV) characteristics, we conclude that Y2O3 has effectively passivated GaAs surface with a much lower interfacial trap density (Dit) than Al2O3 as the gate dielectric. The quasi-static CV and conductance measurements are in agreement with the above conclusion. We have demonstrated an excellent ALD-Y2O3/GaAs interface with low Dit's of (0.5–2)×1012eV−1cm−2 through the whole GaAs band gap without a mid-gap peak feature.

Ultra-high thermal stability and extremely low Dit on HfO2/p-GaAs(001) interface

Molecular beam epitaxy (MBE) HfO2 films ~1.5nm thick were directly deposited on freshly grown GaAs(001)-4×6 reconstructed surfaces. The hetero-structure exhibits outstanding thermal stability up to 900°C with excellent capacitance-voltage (C-V) and leakage current density-electric field (J-E) characteristics. We have extracted low interfacial trap densities (Dit's) with minimum value of 1.3×1011 eV−1cm−2 from the measured quasi-static C-V (QSCV) characteristics. The smallest frequency dispersion of the C-Vs for the MBE-HfO2/p-GaAs(001) is ~5.2% at frequency range of 500 to 1MHz and no trap-induced humps were observed in the C-Vs, as measured at 100°C and 150°C. Also, the leakage current density remains low of 10−8(A/cm2) at E<±3 (MV/cm). The key to passivate GaAs in attaining low Dit's and high-temperature thermal stability is to ensure the cleanness of GaAs surface prior to the high-κ deposition.

Low interfacial trap density and high-temperature thermal stability in atomic layer deposited single crystal Y2O3/n-GaAs(001)

A low interfacial trap density (Dit) of 2.2 × 1011 eV−1 cm−2 has been achieved with an atomic layer deposited (ALD) single crystal Y2O3 epitaxially on n-GaAs(001), along with a small frequency dispersion of 10.3% (2.6%/decade) at the accumulation region in the capacitance–voltage (C–V) curves. The Dit and frequency dispersion in the C–V curves in this work are the lowest among all of the reported ALD-oxides on n-type GaAs(001). The Dit was measured using the conductance–voltage (G–V) and quasi-static C–V (QSCV) methods. Moreover, the heterostructure was thermally stable with rapid annealing at 900 °C under various durations in He and N2, which has not been achieved in the heterostructures of ALD-Al2O3 or HfO2 on GaAs.

Interface trap density evaluation on bare silicon-on-insulator wafers using the quasi-static capacitance technique

This paper presents a detailed investigation of the quasi-static capacitance-voltage (QSCV) technique in pseudo-metal-oxide-semiconductor field effect transistor (pseudo-MOSFET) configuration for evaluating the interface quality of bare silicon-on-insulator (SOI) wafers, without processing dedicated metal-oxide-semiconductor (MOS) test devices. A physical model is developed that is capable of explaining the experimental results. In addition, frequency effects are used to validate the equations by a systematic comparison between experimental and calculated characteristics, as well as by a direct comparison with the standard high-low frequency approach. An extraction procedure for interface trap density based solely on QSCV experimental results is proposed, and limits of the procedure are discussed. The proposed experimental and analytical procedure is demonstrated by characterizing SOI structures with different geometries and with different qualities of surface passivation of the top silicon film.

Anomalous Staircase CV Characteristics of InGaSb-on-Insulator FET

Quasi-static capacitance voltage (CV) characteristics of In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> GaxSb-on-insulator field-effect transistor (FET) are investigated using 1-D coupled Schrödinger-Poisson equations. Here, we report for the first time the staircase trend in the CV characteristics of such ultrathin-body FET. This observation is well correlated with the gate-bias-dependent electron concentration in different subbands. It is revealed that the staircase trend tends to disappear as the channel thickness increases above 15 nm. While the channel thickness and doping concentration-dependent shifts in CV curves are found to be significant, the composition-dependent shift is almost negligible.

Switch the n-type to ambipolar transfer characteristics by illumination in n-type pentacene-based organic field-effect transistors

This work investigates the suppression of n-channel and the switch of transfer characteristics (from n-type to ambipolar) by illumination in n-type pentacene-based organic field-effect transistors (OFETs). The illumination outcomes differently on the output characteristics of OFETs, which markedly decreases the magnitude of drain current (n-channel) and shifts the turn-on voltage to a higher positive bias in the n-type regime, but induces the formation of p-channel in the p-type regime. We attribute that the trapped negative charges in the device as induced by illumination electrostatically shield the effective electrical field applied to the gate with source/drain electrodes and modulate the device performance. The result of quasi-static capacitance–voltage measurement agrees well with the modulations of the transfer characteristics for n-type OFETs by illumination. In addition, the de-trapping of charges recovers the n-type only output characteristics of pentacene-based OFETs. This study highlights the unique photo responses of n-type pentacene-based OFETs to the development of phototransistors of distinct output characteristics operated in n- and p-type regime.

Ultra-Thin, High Quality HfO2 on Strained-Ge MOS Capacitors with Low Leakage Current

Strained-Ge is a promising channel material for future CMOS nodes due to its very high hole mobility [1] and compatibility with existing processes. In comparison to Si, high quality dielectric interfaces for Ge are challenging due to the lack of an ideal native oxide. In this work, for the first time, we show an extremely-scaled (EOT < 5 Å), high quality dielectric on s-Ge. CV measurements of a MOS capacitor structure show areal capacitance scaling, little hysteresis, and low gate leakage current (< 0.2 A/cm2).The epitaxial structure (shown in Fig. 1(a)) was grown by low-pressure CVD, and the s-Ge layer is compressively strained (2.3% biaxial) due to the lattice mismatch with the relaxed Si0.55Ge0.45 virtual substrate. The epitaxial wafer was cleaved into pieces, and a 5-minute 1:10 (HCl:H2O) clean was performed prior to atomic layer deposition (ALD) of 1 minute O3/~3 nm HfO2 (both at 250 °C), followed by ~10 nm of TiN at 300 °C. After ALD, Al contacts were sputtered and patterned followed by a 30-minute forming gas anneal at 450 °C. The final MOS capacitor structure (Fig. 1(a)) reflects the loss in the s-Ge due to the HCl clean and O3 oxidation.CV measurements of a 100×100 µm MOS capacitor show a CET of 8.6 Å (Fig. 2). Large frequency dispersion exists for frequencies > 50 kHz due to large series resistance likely caused by a 500 meV valence band offset [2] between s-Ge and Si0.55Ge0.45 (Fig. 1(b)). The IV measurements (Fig. 3) show small gate leakage current (< 0.2 A/cm2), which translates to IG < 20 pA/µm for LG = 10 nm, well below ITRS requirements [3].Quasistatic one-dimensional self-consistent coupled Poisson-Schrödinger electrostatic simulations were performed in order to extract EOT. A strain-dependent 6×6 k∙p Hamiltonian (with deformation potentials from [2]) was used to calculate hole quantization in the s-Ge layer. In accordance with [4], a 2.1 eV valence band offset between Ge and GeOx was used in the simulations (Fig. 1(b)). The 500 meV valence band offset between between s-Ge and Si0.55Ge0.45creates a deep quantum well confining most of the holes in the s-Ge layer.Fig. 5 shows the 10 kHz experimental CV in addition to simulated quasistatic CV curves for structures with varying EOT. The mismatch of the simulated and experimental curves in strong hole accumulation is due to both a large series resistance (Rs ~ 0.1 Ω∙cm2) and gate leakage, which causes a sizable error when transforming the measured impedance to a two-element parallel capacitance CP , parallel conductance GP circuit model [5]. A circuit model (inset Fig. 6) incorporating parasitic gate tunneling conductance Gt and series resistance Rs is applied to an ideal simulated CV in order to recover the measured CV result, yielding an extracted EOT of 4.9 Å (Fig. 6). This is the smallest known EOT for a high quality dielectric on s-Ge published to date. Other recent results include a 7-Å EOT on s-Ge [6], and an 8-Å CET on unstrained Ge [7].