Quasi-floating Gate Techniques Research Articles

0.8-V Enhanced bulk-driven folded cascode amplifier with high gain-bandwidth and slew rate

In this study, the proposed bulk-driven amplifier utilizes the bulk-driven flipped voltage follower together with the auxiliary amplifier to form the adaptive biasing input stage. The quasi-floating gate technique to build the class-AB output stage can enhance the gain-bandwidth, DC gain and slew rate of the conventional bulk-driven counterpart. Therefore, the current efficiency is improved. Simulation verification using a 0.18 μm CMOS technology, with a supply voltage of 0.8V, showed a DC gain of 76.6 dB, a CMRR of 106.6 dB, a gain-bandwidth product of 6.78 MHz and an average slew rate of 3.48 V/μs .

Low voltage EX-CCCII based on quasi-floating gate technique and its application as precision rectifier

This paper introduces a novel low-voltage low-power Extra-X Current Controlled Current Conveyor (EX-CCCII) based on quasi floating gate (QFG) MOSFET. The QFG technique is employed in low voltage applications and overcomes the limitation of the floating gate technique. The presented circuit is implemented at a supply voltage of ±0.5 V with a power consumption of 90 µW at 20 µA bias current. As an application, the proposed QFG based EX-CCCII is employed to realize a novel current mode precision rectifier circuit. This circuit can simultaneously provide positive and negative type half wave and full wave rectifiers with the same circuit configuration. Furthermore, the rectifier circuit has low input and high output impedance terminals making it suitable for cascading with other current mode circuits. All the results provided to verify the circuit performance are simulated using CADENCE VIRTUOSO SPECTRE simulator with 0.18 µm UMC CMOS technology process parameters. The simulation results confirm the theoretical concept.

A 1.1 μW biopotential amplifier based on bulk-driven quasi-floating gate technique with extremely low-value of offset voltage

Biopotential amplifier (BPA) remains one of the most crucial blocks for the successful implementation of any of the biomedical systems. However, design of a BPA remains challenging owing to most of the topologies reported in literature displaying high values of noise, consuming high value of power and working in limited range of bandwidth. Thus, circuit topologies capable of providing an optimum and an acceptable combination of these parameters remains a topic of immense interest among researchers. We in this paper, report the results of a BPA designed using Bulk-Driven Quasi-Floating Gate (BDQFG) technique with a special focus on the effect of variation in the values of biasing resistor (Rlarge). Results obtained through mathematical modelling and analysis of the circuit have been verified by conducting simulations in Cadence Analog Design Environment using standard 0.18 µm technology. Circuit design has been optimized for least values of power consumption of the order of 1.1 µW, noise (≈ 3.15 µVRMS), mid-band gain of 39.9 dB (from 0.266 Hz to f-3dB of 2.8 kHz), offset voltage of 455 μV and phase margin of 65.83°.

A CMOS Micro-power, Class-AB “Flipped” Voltage Follower using the quasi floating-gate technique

This paper presents the design and characterization of a new analog voltage follower for low-voltage applications. The main idea is based on the “Flipped” Voltage Follower and the use of the quasi-floating gate technique for achieving class AB operation. A test cell was simulated and fabricated using a 0,5 μm CMOS technology. When the proposed circuit is supplied with VDD = 1,5 V, it presents a power consumption of only 413 μW. Measurement and experimental results show a gain bandwidth product of 10 MHz and a total harmonic distortion of 1,12 % at 1 MHz.

Using Floating Gate and Quasi-Floating Gate Techniques for Rail-to-Rail Tunable CMOS Transconductor Design

Floating-gate and quasi-floating gate MOS transistors can be efficiently employed to design CMOS transconductors. These transistors allow achievement of relevant features in a compact and simple way, such as rail-to-rail input range, continuous transconductance tuning, and class AB operation. This paper illustrates how these techniques can be applied by employing them in the design of two transconductors, which have been fabricated in a 0.5 μm CMOS process. Measurement results confirm the advantages of the proposed approach.